JP2985508B2 - Local oscillation frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a local oscillation frequency synthesizer, and more particularly to a local oscillation frequency synthesizer capable of high-speed frequency switching.

[0002]

2. Description of the Related Art FIG. 4 shows the configuration of a conventional local oscillation frequency synthesizer.

In FIG. 4, a conventional local oscillation frequency synthesizer includes a phase comparator 14 of a PLL loop and a reference frequency from a reference frequency oscillator 16 and a voltage controlled oscillator 6.
Of the voltage controlled oscillator 6 through a loop filter (LPF) 8 by driving a charge pump (CP) 10 with the phase difference signal. The carrier frequency is generated by controlling the voltage value.

In order to switch the frequency at high speed, it is necessary to increase the gain of the loop system. The main parameters include the frequency division ratio and the loop filter. In particular, by responding to the latter by changing the loop filter, the noise bandwidth is increased, so that the sensitivity to the phase difference signal is high, but the noise is easily taken into the system, and the C / N value of the oscillation output is deteriorated. In such a case, a method of improving the C / N value by using a negative device, for example, by adding capacitors 20 and 21 to the signal output unit of the phase comparator and expanding a dead zone, is adopted.

[0005]

In the above-mentioned conventional frequency synthesizer, when the channel (CH) is switched,
Although frequency switching is fast due to the high system gain,
Since the dead zone of the phase comparison is widened, there is a problem that the signal swinging up and down easily trails near the convergence value.

[0006]

According to the present invention, there is provided a local oscillation frequency synthesizer comprising: a reference frequency signal generator for generating a signal having a reference frequency; a voltage controlled oscillator; and a frequency divider for dividing an oscillation frequency from the voltage controlled oscillator. A frequency divider, a phase comparator that compares the phase of the signal from the reference frequency signal generator with the frequency-divided signal from the frequency divider, and a charge pump that receives a phase difference signal from the phase comparator. Each having a loop filter for the output of the charge pump, and controlling the oscillation frequency of the voltage controlled oscillator by a voltage obtained by integrating the phase error from the loop filter.
A frequency synthesizer of more 2 groups L L, and a composite output unit to output a signal obtained by adding the respective output frequency of the synthesizer of the two groups, at the output frequency switching, the 2
Delayed by a predetermined time from the time when one of the synthesizers is coarsely adjusted by switching the frequency change of Δf only instantaneously
Wherein the 1 group simultaneously remainder of the synthesizer of the 2 groups when returning again to the original frequency by switching a frequency change in (-.DELTA.f)
And controls the operation switching frequency change in Delta] f, synth the 2 groups the frequency of the output of the synthesized output unit as a result of
And a control unit for switching to a frequency obtained by adding the output frequencies of the sizers .

[0007]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a diagram showing a flow of a control signal in the present embodiment, and FIG.
FIG. 9 is a diagram illustrating an example of a change in the oscillation frequency of the two PLL synthesizers at the time of channel switching in the present embodiment.

In FIG. 1, this embodiment includes PLL synthesizers 1 and 2, a signal synthesizer 3 for synthesizing signals from the PLL synthesizers 1 and 2, and a controller 4 for controlling the PLL synthesizers 1 and 2. The PLL synthesizers 1 and 2 respectively include reference frequency signal generators 15 and 16 for generating a signal of a reference frequency, and voltage controlled oscillators 5 and 5.
6, frequency divider circuits 11 and 12 for dividing the oscillation frequency from voltage controlled oscillators 5 and 6, reference frequency signal generator 15,
Phase comparators 13 and 14 for comparing the phase of the signal from the frequency divider 16 with the frequency-divided signals from the frequency-dividing circuits 11 and 12; It comprises loop filters 7 and 8, and the oscillation frequency of the voltage controlled oscillators 15 and 16 is controlled by a PLL loop by a voltage obtained by integrating the phase error from the loop filters 7 and 8.

The control unit 4 issues frequency division circuits 11, 1 of the PLL synthesizers 1, 2 in response to a channel (CH) switching command.
2 and a synchronization signal confirmation unit 17 for confirming a synchronization signal from the phase comparator 13.

Next, the operation of this embodiment will be described with reference to FIGS.

The local oscillation frequency synthesizer according to the present embodiment uses the frequency f ₃ = f ₁ + f ₂ obtained by combining the outputs f ₁ and f ₂ of the PLL synthesizers 1 and 2 shown in FIG. I have.

In this embodiment, upon receiving a channel (CH) switching instruction, the control unit 4 changes the carrier frequency Δf.
For the PLL synthesizer 1. The phase comparator 13 sends a synchronization signal to the synchronization signal confirmation unit 17 in the control unit 4 when the phase is pulled to some extent, and coarsely adjusts the oscillation frequency of the PLL synthesizer unit 1 to f ₁ + Δf without convergence. After confirming that the operation has been performed, the control unit 4 instructs the PLL synthesizer unit 1 to output -Δf, P
Instructs the LL synthesizer unit 2 to perform + Δf switching control,
The output of the PLL synthesizer ₁ is returned to f _1, and the output of the PLL synthesizer 2 is converged to f ₂ + Δf.

The output f ₃ of the system converges to f ₃ + Δf as a result, and CH synchronization is established. At this time, the outputs f ₁ and f ₂ of the PLL synthesizers 1 and 2 are shown in the part e of FIG.
Since the signal oscillations near the convergence value of + Δf are mutually symmetric modes, they are canceled out, and the disturbance of the convergence of the output f3 + Δf of the system can be reduced.

By distributing the local oscillation frequency to the PLL synthesizer sections 1 and 2, the oscillation frequency / CH interval ratio of the PLL synthesizer sections 1 and 2 is small and the frequency division ratio is reduced, thereby increasing the gain of the system. In addition, high-speed frequency switching becomes possible.

[0016]

As described above, according to the present invention, a phase comparator, two PLL synthesizers in which a loop filter and a voltage controlled oscillator form a loop, and a frequency switching instruction are received, and both the synthesizers are made independent. , One of the PLL synthesizers is first switched to Δf, and then both PLL synthesizers are symmetrically switched to −Δ.
By providing a control unit that performs an operation of switching between f and + Δf, even when the dead zone of the phase comparison is widened in order to improve the C / N value of the output of the PLL synthesizer, vibration near the convergence value at the time of frequency switching is suppressed. Since the oscillation frequency is distributed to two PLL synthesizers, the gain of the system can be set high, and in addition, stable high-speed frequency switching and the area for securing the C / N value of the oscillation output are enabled. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing a flow of one control signal in the embodiment.

FIG. 3 shows two Ps at the time of channel switching in this embodiment.
FIG. 4 is a diagram illustrating an example of a change in an oscillation frequency of an LL synthesizer unit.

FIG. 4 is a block diagram showing an example of a conventional local oscillation frequency synthesizer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 PLL synthesizer part 2 PLL synthesizer part 3 Signal synthesis part 4 Control part 5, 6 Voltage control oscillator 7, 8 Loop filter 9, 10 Charge pump 11, 12, Divider circuit 13, 14, Phase comparator 15, 16, Reference frequency generation part 17 Synchronization signal confirmation section 18 CH switching command 19 Switching control section 20 Capacitor 21 Capacitor

Claims (1)

(57) [Claims] 1. A reference frequency signal generator for generating a reference frequency signal, a voltage controlled oscillator, a frequency divider for dividing an oscillation frequency from the voltage controlled oscillator, and a signal from the reference frequency signal generator. A phase comparator for comparing the phase of the signal with the frequency-divided signal from the frequency divider, a charge pump receiving the phase difference signal from the phase comparator, and a loop filter for the output of the charge pump. A PL that controls an oscillation frequency of the voltage controlled oscillator by a voltage obtained by integrating a phase error from the loop filter.
Instantaneous frequency synthesizer of more 2 group L, and the composite output unit to output the respective signals obtained by adding the output frequency of the synthesizer of this 2 group, when the output frequency switching, a group of the synthesizer of the 2 groups Only a predetermined time delay from the point of coarse adjustment by switching by the frequency change of Δf
Wherein the 1 group simultaneously remainder of the synthesizer of the 2 groups when returning again to the original frequency by switching a frequency change in (-.DELTA.f)
And controls the operation switching frequency change in Delta] f, synth the 2 groups the frequency of the output of the synthesized output unit as a result of
A local oscillation frequency synthesizer comprising: a control unit configured to switch to a frequency obtained by adding respective output frequencies of the sizers .