JPH06252715A - Variable clock generating circuit - Google Patents

Abstract

PURPOSE:To provide the variable clock generating circuit with small scale circuit configuration by converting a phase difference between an input signal and a reference clock signal into a voltage level and varying a capacitance of a variable capacitor in response to the voltage level. CONSTITUTION:A voltage level detection circuit 4 detects a sawtooth wave voltage level when an edge detection circuit 3 detects an edge of an input signal and the detected voltage level is held by a voltage hold circuit 5. The capacitance of a variable capacitor 12 is changed by the voltage level, resulting that a time constant of 1st and 2nd delay circuits 9a, 9b delaying an output clock signal of a reference signal generating circuit 1 is changed and the delay in the output clock signal is changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit, and more particularly to a variable clock generation circuit for generating a sampling clock phase-locked with an external synchronization signal.

[0002]

2. Description of the Related Art A conventional variable clock generation circuit will be described with reference to the drawings.

FIG. 4 is a block diagram of a conventional variable clock generation circuit, and FIG. 5 is a time chart of clocks generated from the variable clock generation circuit of FIG.

The conventional variable clock generation circuit includes a reference signal generation circuit 1, a delay circuit 15, a phase comparator 16, and
It is composed of a phase selector 17.

The delay circuit 15 delays the output clock signal, which is the reference clock of the reference signal generation circuit 1, by a plurality of delay amounts to generate a plurality of clock signals (delayed clocks 1 to 5) having different phases, and performs phase comparison. The phase selector 16 compares the phases of the plurality of clock signals output from the delay circuit 15 with the input signal, and as a result, the phase selector 17 selects the clock signal having the closest phase to the input signal, for example, the delayed clock 4 in FIG. It is output and is output as a variable clock.

[0006]

In the conventional variable clock generation circuit described above, the delay circuit must generate a plurality of clocks and the phase comparator must compare the phases of the plurality of clock signals with the input signal. There is a problem that the circuit scale becomes large and the cost becomes high.

Furthermore, the number of clock signals generated by the delay circuit affects the phase tracking property of the clock signal to the input signal, and the reliability deteriorates when the number of clock signals generated by the delay circuit is small. There is a point.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned conventional drawbacks, and has a small circuit scale and a variable clock generation which is excellent in phase tracking of a clock signal to an input signal. The purpose is to provide a circuit.

Therefore, the variable clock generating circuit of the present invention detects the edge of the input signal, the reference signal generating circuit for generating the clock signal, the waveform shaping circuit for shaping the output clock signal of the reference signal generating circuit into a sawtooth wave. Edge detection circuit, a voltage level detection circuit that detects the voltage level of the sawtooth wave shaped by the waveform shaping circuit when the edge detection circuit detects an edge of the input signal, and a voltage level that holds the voltage level of the sawtooth wave Hold circuit,
A varicap whose capacitance value changes according to the output voltage level of the voltage level hold circuit and a delay circuit that delays the output clock signal of the reference signal generation circuit and changes the delay amount of the clock signal according to the capacitance value of the varicap. And is provided.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a variable clock generation circuit according to the present invention, FIG. 2 is a graph showing the relationship between the capacitance value and voltage level of the varicap of FIG. 1, and FIG. 3 is the variable clock of FIG. 7 is a timing chart in the case where the phase of the reference clock signal leads the phase of the input signal in the range of ¼ cycle or less in the generation circuit.

In FIG. 1, the variable clock generating circuit of the present embodiment comprises a reference signal generating circuit 1, a waveform shaping circuit 2,
The edge detection circuit 3, the voltage level detection circuit 4, the voltage level hold circuit 5, the constant voltage circuit 6, the polarity determination circuit 7, the comparator 8, the first delay circuit 9a, the second delay circuit 9b, A switch 10 and a bias circuit 11,
It comprises a varicap 12, a resistor 13, and a switch 14.

The reference clock signal output from the reference signal generation circuit 1 is shaped by the waveform shaping circuit 2 into a sawtooth wave having a maximum voltage value of VR and output to the voltage level detection circuit 4. At this time, two sawtooth waves are output in one cycle of the clock signal.

The edge detection circuit 3 detects the edge of the input signal (synchronization signal). When the edge detection circuit 3 detects the edge of the input signal, the polarity determination circuit 7 detects the reference clock signal at the time of edge detection. Detect the voltage level. When the voltage level is "H level", the switch 10 is on the S1 side, and when it is "L level", the switch 1 is
Set 0 to S2 side. As a result, when the voltage level of the reference clock signal at the time of detecting the edge of the input signal is “L level”, that is, when the phase of the reference clock signal is advanced by ½ cycle or more of the phase of the input signal, the reference clock signal is inverted. The generated signal is input to the first delay circuit 9a. That is, by inverting the reference clock signal, the reference clock signal is delayed by 1/2 cycle.

For example, when the phase of the reference clock signal leads the phase of the input signal within a range of ¼ cycle or less, as shown in FIG. 3, the voltage level of the reference clock signal detected by the polarity determination circuit 7 Is at "H level", the switch 10 is on the S1 side, and the reference clock signal is directly input to the first delay circuit 9a.

The voltage level detection circuit 4 is a waveform shaping circuit 2 when the edge detection circuit 3 detects an edge of an input signal.
The voltage level of the sawtooth wave shaped by is detected.

The voltage level detected by the voltage level detection circuit 4 is held by the voltage level hold circuit 5 and output to the comparator circuit 8.

The comparator circuit 8 sets the switch 14 to the S3 side when the voltage level of the voltage level hold circuit 5 is 1/2 VR or less, and the switch 14 when it is 1/2 VR or more.
To the S4 side. As a result, the voltage level hold circuit 5
, The reference clock signal passes through only the first delay circuit 9a and the second delay circuit 9
Do not pass b.

For example, when the phase of the reference clock signal leads the phase of the input signal in the range of ¼ cycle or less, the voltage level of the sawtooth wave detected by the comparator circuit 8 is 1 as shown in FIG. Since it is / 2 VR or more, the switch 14 is on the S4 side, and the reference clock signal passes only the first delay circuit 9a and does not pass the second delay circuit 9b. Here, the first delay circuit 9a and the second delay circuit 9b are circuits that delay the reference clock signal. The operation procedure of the first delay circuit 9a and the second delay circuit 9b is shown below.

The voltage level held by the voltage level hold circuit 5 is passed through the constant voltage circuit 6 to the first delay circuit 9a.
Bias circuit 11 determines the bias voltage level to be applied to the vari gap 12 of the delay circuit 9a. The output voltage of the constant voltage circuit 6 is also output to the bias circuit 11 in the second delay circuit 9b, and the bias voltage level of the second delay circuit is determined by the same procedure as the first delay circuit 9a. Therefore, when the voltage level of the sawtooth wave detected by the voltage level detection circuit 4 changes, the voltage value across the vari gap 12 in the delay circuit 9a changes, and the capacitance value of the varicap 12 changes. Here, the burr gap 12 is an element whose capacitance value changes according to the voltage level applied to both ends thereof, and as shown in FIG.
The capacitance value decreases as the voltage level across both ends increases.

As a result of the above, the varicap 12 and the resistor 13 are provided.
The time constant determined by the value of
The delay amount of the first delay circuit 9a that delays the reference clock signal of is changed. The delay amount of the second delay circuit 9b also changes in the same procedure as in the case of the first delay circuit 9a. Where the first
The maximum delay amount of the delay circuit 9a and the second delay circuit 9b is 1/4.
The time constants of the burr gap 12 and the resistor 13 are set so as to become a cycle. The delay of 1/4 cycle or more is caused by the switch 1 by the polarity detection circuit 7 and the comparator circuit 8 described above.
0, switch 14 is performed.

The phase difference between the reference clock signal and the input signal,
Table 1 shows the relationship between the voltage level of the sawtooth wave and the voltage level of the reference clock signal. Table 1 also shows the states of the switches 10 and 14 at that time.

[0023]

According to the above operation procedure, the reference lock signal is
The first delay circuit 9a and the second delay circuit 9b delay the phase difference from the input signal to synchronize with the phase of the input signal.

[0025]

As described above, the variable clock generation circuit of the present invention converts the phase difference between the input signal and the reference clock signal into a voltage level, and changes the capacitance value of the varicap according to the voltage level. As a result, a clock signal that follows the phase of the input signal can be generated, which can be easily realized with a small-scale circuit configuration, and further, the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a variable clock generation circuit according to the present invention.

FIG. 2 is a graph showing the relationship between the capacitance value and voltage level of the varicap shown in FIG.

3 is a timing chart when the phase of the reference clock signal leads the phase of the input signal within a range of ¼ cycle or less in the variable clock generation circuit of FIG. 1. FIG.

FIG. 4 is a block diagram of a conventional variable clock generation circuit.

5 is a time chart of a clock generated from the variable clock generation circuit of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 reference signal generation circuit 2 waveform shaping circuit 3 edge detection circuit 4 voltage level detection circuit 5 voltage level hold circuit 6 constant voltage circuit 7 polarity determination circuit 8 comparator circuit 9a first delay circuit 9b second delay circuit 10 switch 11 bias circuit 12 Varicap 13 Resistor 14 Switch 15 Delay circuit 16 Phase comparator 17 Phase selector

Claims (1)

[Claims] 1. A reference signal generation circuit for generating a reference clock signal, a waveform shaping circuit for shaping an output clock signal of the reference signal generation circuit into a sawtooth wave, an edge detection circuit for detecting an edge of an input signal, A voltage level detection circuit that detects the voltage level of the sawtooth wave shaped by the waveform shaping circuit when the edge detection circuit detects the edge of the input signal, and a voltage level hold circuit that holds the voltage level of the sawtooth wave, The delay amount of the clock signal is changed according to the capacitance value of the varicap by delaying the output clock signal of the reference signal generating circuit and the varicap whose capacitance value changes according to the output voltage level of the voltage level hold circuit. A variable clock generating circuit, comprising: