JP3070438U - Delay generation circuit - Google Patents

Abstract

(57) [Summary] The present invention provides a delay generation circuit that corrects a linearity error and changes the delay time in linear steps. SOLUTION: A first delay generating circuit capable of delaying and outputting an input signal by changing a delay time by setting data, a second delay generating circuit capable of delaying and outputting an input signal by changing a delay time by setting data, A delay element capable of delaying the signal output from the second delay generation circuit by a predetermined time and outputting the signal; and selecting a signal output from the delay element or a signal output from the second delay generation circuit. And a phase comparing means for comparing the phase of a selected output signal of the switch with the output signal delayed by the first delay generating circuit.

Description

[Detailed description of the invention]

[0001]

[Technical field to which the invention belongs]

 The present invention relates to a delay generation circuit that corrects a linearity error when a signal is delayed and output in steps according to setting data.

[0002]

[Prior art]

 The configuration and operation of an example of a conventional delay generation circuit will be described with reference to FIGS. 7 and 8. FIG. As shown in FIG. 7, the conventional delay generation circuit includes a constant current source U, switches S1 and S2, a capacitor C, a comparison voltage source Vr, and a comparator CP.

[0005] The switches S1 and S2 are controlled by an input signal IN. For example, when the input signal changes from LOW to HIGH, the switches S1 / S2 are controlled from OFF / ON to ON / OFF.

[0004] The capacitor C is discharged when the switches S1 / S2 are OFF / ON, and charged by the constant current source U when the switches S1 / S2 are ON / OFF.

[0005] The comparison voltage source Vr is a voltage source that controls a comparison voltage generated by the delay setting data D (n).

The comparator CP compares the voltage of the signal at the + input terminal with the comparison voltage at the − input terminal, and when the voltage of the signal at the + input terminal exceeds the comparison voltage at the − input terminal. And the output voltage is inverted.

Next, the operation of the conventional delay generating circuit shown in FIG. 7 will be described. For example, at time 0, when the input signal changes from LOW to HIGH, the switches S1 / S2 are controlled from OFF / ON to ON / OFF, so that the capacitor C is charged by the constant current source U from the discharge state. Then, the voltage rises, and at time t exceeding the comparison voltage, the output voltage of the comparator CP is inverted from LOW to HIGH.

Therefore, by sequentially changing the generation voltage of the comparison voltage source Vr in steps according to the delay setting data D (n), it is possible to provide a delay generation circuit that generates an output signal by delaying it in steps. However, the resolution of the delay time delayed in steps can be realized by reducing the resolution of the voltage generated by the comparison voltage source Vr, but the linearity of the delay time is not improved.

For example, as shown in FIG. 8, delay setting data D (n) for step-changing the generated voltage of the comparison voltage source Vr is set to D (0), D (1),... D (5). At this time, the delay time ideally changes linearly as shown by the solid line, but actually changes as shown by the dotted line, so that a linearity error occurs. Factors that cause the linearity error include the voltage dependence of the capacitance of the capacitor C and the fact that the output impedance of the constant current source U is not infinite.

[0010]

[Problems to be solved by the invention]

 As described above, the conventional delay generation circuit has a practical problem that the delay time does not linearly occur with respect to the setting data for changing the voltage generated by the comparison voltage source Vr in steps. Accordingly, the present invention has been made in view of such a problem, and an object of the present invention is to provide a delay generation circuit that corrects a linearity error so that a delay time is generated linearly.

[0011]

Means for Solving the Problems In order to achieve the above object, the present invention provides a first delay generating circuit capable of delaying and outputting an input signal by changing a delay time according to setting data, and A second delay generation circuit capable of delaying and outputting an input signal by changing a delay time, a delay element capable of delaying a signal output from the second delay generation circuit by a predetermined time, and outputting the delayed signal; A switch for selecting and outputting the signal output delayed by the second delay generation circuit or the signal output delayed by the second delay generation circuit, and comparing the phase of the output signal selected by the switch with the output signal delayed by the first delay generation circuit And a phase comparing means for generating a delay time in steps of the delay time of the delay element.

[0012]

[Embodiment of the invention]

 Embodiments of the present invention will be described in the following examples.

[0013]

【Example】

 An embodiment of the delay generation circuit according to the present invention will be described with reference to FIGS. As shown in FIG. 1, the delay generation circuit of the present embodiment includes a delay generation circuit A10, a delay generation circuit B20, a delay element 30, a switch SW, a flip-flop 40, a low-pass filter 50, a voltmeter 60 It consists of: Here, the flip-flop 40, the low-pass filter 50, and the voltmeter 60 are configuration examples of the phase comparison unit.

The delay generation circuit A 10 and the delay generation circuit B 20 are circuits for generating the signals of the input IN by delay output according to the setting data DA (n) and the setting data DB (n), respectively. Here, each of the delay generation circuit A10 and the delay generation circuit B20 may be configured by, for example, a delay generation circuit having a linearity error described in the related art. However, the delay generation circuit A10 and the delay generation circuit B20 have sufficient step resolution of the delay time.

The delay element 30 is an element for delaying the phase of a signal by a predetermined time, and includes, for example, a delay line.

Next, each component example of the phase comparison means will be described. The flip-flop 40 uses, for example, a D-type flip-flop data input and a clock input as a phase comparison signal as a phase comparison circuit.

The low-pass filter 50 receives the output of the flip-flop 40 with a longer time constant and outputs it as a DC voltage.

The voltmeter 60 is a high-resolution voltmeter that measures a voltage when the phases of the compared signals match each other, and uses, for example, a digital voltmeter. Here, if the input part of the voltmeter 60 has a function of a low-pass filter, the low-pass filter 50 is unnecessary.

Next, a method of measuring a voltage when the phases of the signals compared in the phase comparing means match will be described with reference to FIGS. As shown in FIG. 3, when the time of the rising point of the signal input to the data D of the flip-flop 40 is set to 0 and the state of the signal of the clock CK is changed from the advanced state to the delayed state, As shown in (5), the voltage measured by the voltmeter 60 changes from a high voltage to a low voltage via the voltage Vc when the phase difference is zero.

Therefore, as shown in FIG. 2, when the same clock signal is inputted by connecting the data input D of the flip-flop 40 and the clock input CK, the voltage of the Q output of the flip-flop 40, that is, the phase becomes The voltage Vc at the time of coincidence, which can be determined by measuring with the voltmeter 60.

Next, the operation of the delay generation circuit shown in FIG. 1 of the present embodiment will be described in the following paragraphs with reference to the flowchart of FIG. However, it is assumed that the voltage Vc when the phases of the signals match is determined in advance by the phase comparing means. Further, a predetermined delay time of the delay element 30 is set to τ.

(1) The initial value of n is set to n = 0, and the end value of n is set to n = m, and the initial data DA (n) is set in the delay generation circuit A10 (step 100).

(2) Connect the switch SW to the a side (Step 200).

(3) The setting data of the delay generation circuit B20 is scanned, and the phase of the signal delayed by the delay generation circuit A10 matches the phase of the signal delayed by the delay generation circuit B20. (N) is obtained when the voltage measured by the voltmeter 60 becomes Vc, and is fixed to the delay setting data DB (n) at that time (step 300).

(4) Connect the switch SW to the b side (step 400).

(5) By setting n to n + 1, the setting data of the delay generation circuit A 10 is scanned, and the phase of the signal delayed by the delay generation circuit B 20 and the delay element 30 is delayed by the delay generation circuit A 10. The setting data DA (n) having the same phase as the signal is obtained by measuring the voltage of the voltmeter 60 to the voltage Vc, and is fixed to the delay setting data DA (n) at that time (step 500).

(6) If n is smaller than the final value m, return to step 200 and repeat until step 500. If n is equal to or greater than the final value m, the process ends (step 600).

In this embodiment, since the delay time of the setting data DB (0) and the delay time of the setting data DA (0) are the same, the delay time of the setting data DB (0) and the delay time of the delay element 30 The delay time of the sum of the delay time and the delay time of the setting data DA (0) and the delay time of the delay element 30 is the delay time of the setting data DA (1). Therefore, the delay time of the present delay generation circuit is the same as sequentially adding the delay time τ of the delay element 30 from the delay time of the setting data DA (0). As a result, as shown in FIG. 6, when the delay setting data DA (0), DA (1),... DA (5) are changed, a linear delay time with the resolution of the delay time τ of the delay element 30 is obtained. Can occur.

By the way, the delay generation circuit of the present embodiment can reduce the resolution by reducing the delay time τ of the delay element 30. However, when a further lower resolution is required, a desired value can be obtained by performing data interpolation. A linear delay time can be generated with a resolution of.

[0030]

[Effect of the invention]

 The present invention is embodied in the form described above and has the following effects. That is, since two delay generating circuits are provided and the delay time is corrected at the step of the delay element, it is possible to obtain a delay generating circuit having no linearity error in which the delay time changes at the step of the delay element.

[Brief description of the drawings]

FIG. 1 is a block diagram of a delay generation circuit according to the present invention.

FIG. 2 is a block diagram of a phase comparison unit.

FIG. 3 is a timing chart showing a phase difference.

FIG. 4 is an output voltage characteristic diagram of a flip-flop due to a phase difference.

FIG. 5 is a flowchart of a method for correcting a delay generation circuit according to the present invention;

FIG. 6 is a characteristic diagram of the delay generation circuit of the present invention.

FIG. 7 is a diagram of a conventional delay generation circuit.

FIG. 8 is a characteristic diagram of a conventional delay generation circuit.

[Explanation of symbols]

 Reference Signs List 10 delay generation circuit A 20 delay generation circuit B 30 delay element 40 flip-flop 50 low-pass filter 60 voltmeter

Claims (1)

[Utility model registration claims] 1. A first delay generating circuit capable of delaying and outputting an input signal by changing a delay time according to setting data, and a second delay generating circuit capable of delaying and outputting an input signal by changing a delay time according to setting data. A delay element capable of further delaying the signal output from the second delay generation circuit for a predetermined time and outputting the selected signal; and selecting a signal output from the delay element or a signal output from the second delay generation circuit. And a phase comparing means for comparing the phase of the selected output signal of the switch with the output signal delayed by the first delay generating circuit. A delay generation circuit characterized by being able to generate time.