JPH06252358A - Manufacture of semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve the withstand voltage of the capacity of a memory cell by forming a storage electrode by taper etching, and inclining the sidewall of the storage electrode. CONSTITUTION:After formation of a contact hole in the interlayer insulating film 7 in a source region 5, a storage electrode 8 is formed by sticking a polysilicon film all over the surface and patterning it. The polysilicon film in the region to serve as the storage electrode 8 is covered with a photoresist, and using it as an etching-resist mask, the polysilicon film is tapered by etching, and the side face of the storage electrode 8 is inclined. As a result of such taper etching, the sidewall of the storage electrode 8 becomes an incline at 30-45 deg. to the surface of the flat interlayer insulating film 7. Next, a cell plate electrode 10 is formed by sticking a capacitive insulating film 9 and a polysilicon film all over the surface and then, patterning them. Since it becomes easy for oxidation to occur at the corners 8A and 8B of the storage electrode 8, the pinhole of the capacitive insulating film 9 is reinforced by an oxide film, and the withstand voltage of the capacity of a memory cell can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for manufacturing a semiconductor memory device in which a withstand voltage defect of a capacitive insulating film of a memory cell is improved.

[0002]

2. Description of the Related Art A conventional method for manufacturing a semiconductor memory device having a memory cell having a stack structure is disclosed in, for example, Japanese Patent Laid-Open No. 4-7.
It is known from Japanese Patent No. 3964 (H01L 27/108) and the like. A conventional method for manufacturing a semiconductor memory device will be described with reference to FIGS.

In FIG. 6, a thick oxide film (22) is formed by a LOCOS method in a field region on a semiconductor substrate (21), and a thin gate oxide film (23) is formed in an active region forming a memory cell. In FIG. 7, after depositing a polysilicon film on the entire surface by the CVD method, impurities such as phosphorus are diffused to render the polysilicon film conductive. Next, this polysilicon film is patterned to form the gate electrode (24) of the MOS transistor of the memory cell.

In FIG. 8, after oxidizing the surface of the gate electrode (24), phosphorus is used by using the gate electrode (24) as a mask.
A source region (25) and a drain region (2) that form a MOS transistor of a memory cell by ion-implanting arsenic or the like.
6) is formed. Then, an interlayer insulating film (27) made of a silicon oxide film is attached to the entire surface by the CVD method. In FIG. 9, a contact hole is formed in the interlayer insulating film (27) in the source region (26), and then a polysilicon film is formed on the entire surface by CVD.
Then, the storage electrode (28) is formed by etching.

In FIG. 10, a capacitive insulating film (29) made of a silicon nitride film and a polysilicon film are deposited on the entire surface and then patterned to form a cell plate electrode (30).
To form.

[0006]

In the method of manufacturing a semiconductor memory device as described above, the storage electrode (28) is formed by etching substantially perpendicularly to the surface of the interlayer insulating film (27). , Two corners (28) formed above and below the edge of the storage electrode (28).
A, 28B) are close to a right angle. Therefore, when the capacitive insulating film (29) is formed on the storage electrode (28) having such corners, the capacitive insulating film (29) on these portions is bent at a substantially right angle, which causes stress. In addition, there is a problem that a breakdown voltage defect due to a weak spot is likely to occur.

Further, when the surface of the capacitance insulating film (29) is oxidized to reinforce the pinhole, the capacitance insulating film (29) on these portions is hard to be oxidized due to the influence of stress, so that the pinhole is formed. There was also a problem that the pressure resistance was not improved without being reinforced.

[0008]

The present invention has been made in view of the above problems, and the storage electrode (8) is formed by taper etching, and the side wall of the storage electrode (8) is slanted. The present invention provides a method for manufacturing a semiconductor memory device with improved capacity breakdown resistance.

[0009]

According to the present invention, the step of taper-etching the polysilicon film to form the storage electrode (8) whose sidewalls are slanted forms the upper and lower corners (8A, 8B) of the end of the storage electrode (8). Since the breakage of the capacitive insulating film (9) formed on the portion becomes small, the stress applied to the capacitive insulating film (9) at this portion becomes small, and oxidation easily occurs, so that the withstand voltage of the capacitance of the memory cell is improved. it can.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor memory device according to the present invention will be described below with reference to FIGS. In FIG. 1, a thick oxide film (2) is formed by a LOCOS method in a field region on a P-type semiconductor substrate (1), and a thin gate oxide film (3) is formed in an active region forming a memory cell. In this step, the semiconductor substrate (1) is covered with a pad oxide film of about 500Å and a silicon nitride film attached by the LPCVD method of about 1000Å, and the silicon nitride film is patterned so as to cover only the active region. Then, a thick oxide film (2) of about 6000 Å is formed in the field region by selective oxidation. The active region of the semiconductor substrate (1) has about 170
The Å gate oxide film (3) is formed by thermal oxidation.

In FIG. 2, after a polysilicon film is deposited on the entire surface by the LPCVD method, impurities such as phosphorus are diffused to make the polysilicon film conductive. Then, the polysilicon film is patterned to form the MOS of the memory cell.
The gate electrode (4) of the transistor is formed. That is, in this step, a polysilicon film of about 2000 Å is deposited on the entire surface by the LPCVD method to dope into the N ⁺ type. This gate electrode (4) functions as a word line of the memory.

In FIG. 3, after the surface of the gate electrode (4) is oxidized, phosphorus, arsenic and the like are ion-implanted by using the gate electrode (4) as a mask to form a source region (5) and a drain forming a MOS transistor of a memory cell. Form a region (6). After that, an interlayer insulating film (7) made of a silicon oxide film is deposited on the entire surface by LPCVD. More specifically, phosphorus is ion-implanted using the gate electrode (4) as a mask, a sidewall is further formed on the gate electrode (4), and then arsenic is ion-implanted to form an LDD structure (not shown).
A source region (5) and a drain region (6) are formed. The interlayer insulating film (7) is a silicon oxide film of about 3000 Å
To some extent, it adheres to the entire surface by the LPCVD method.

In FIG. 4, after forming a contact hole in the interlayer insulating film (7) of the source region (5), a polysilicon film is deposited on the entire surface by a CVD method and patterned to form a storage electrode (8). To do. In this step, a contact hole is formed in the interlayer insulating film (7) on the source region (5) and the gate oxide film (3) using a photoresist, and a polysilicon film is formed on the entire surface by LPCVD to a thickness of about 3000 Å. It is attached. After that, the polysilicon film has increased conductivity due to diffusion of impurities of phosphorus.

Next, regarding the feature of the present invention,
The polysilicon film in the region to be the storage electrode (8) is covered with a photoresist, and the polysilicon film is taper-etched using the photoresist as an etching resistant mask to incline the side surface of the storage electrode (8). Here, as conditions for taper etching of the polysilicon film, conditions for wet etching may be applied, or conditions for dry isotropic etching may be applied. In the case of wet etching, for example, etching is performed using an etching solution in which nitric acid, hydrofluoric acid and acetic acid are mixed at a weight ratio of 70: 44: 99.5. In the case of dry etching, for example, CF ₄ gas with a flow rate of 390 SCCM and O ₂ gas with a flow rate of 80 SCCM are mixed and used, and plasma etching is performed under the conditions of a pressure of 1 Pascal and a power of 500 W. This is the so-called CDE (Chemical Dry Etching)
The etching apparatus for can be applied. In addition, RIE (Reac
Even when an etching device for tive ion etching is used, taper etching can be performed by selecting the gas and flow rate. For example, O ₂ , He, Cl ₂ and SF ₆ gases are mixed at a flow rate of 10 SCCM, 50 SCCM, 12 SCCM and 40 SCCM, respectively,
Plasma etching is performed under the conditions of a pressure of 500 mTorr and a power of 150 W.

As a result of such taper etching, the side wall of the storage electrode (8) becomes an inclined surface of about 30 to 45 degrees with respect to the surface of the flat interlayer insulating film (7). In FIG. 5, a capacitive insulating film (9) made of a silicon nitride film and a polysilicon film are deposited on the entire surface and then patterned to form a cell plate electrode (10). In this step, a silicon nitride film of about 120 Å formed by the LPCVD method is attached to the entire surface and dry oxidation is performed at 900 ° C. for 30 minutes. In this step, the pinholes of the silicon nitride film attached to the side walls of the storage electrode (8) are reinforced by the oxide film,
A good quality capacitor insulating film can be obtained. After that, LPCV on the entire surface
A polysilicon film of about 1500 Å is deposited by the D method, and N ⁺ type is doped. Subsequently, a region of the polysilicon film, which will be the cell plate electrode (10), is covered with a photoresist,
Using this as a mask, the polysilicon film and the silicon nitride film are etched to form a cell plate electrode (10).

As has been clarified in this step, since the side wall of the storage electrode (8) is an inclined surface, capacitive insulation at the upper and lower corners (8A, 8B) of the end of the storage electrode (8). The breakage of the film (9) is reduced, so that the stress applied to the capacitive insulating film (9) at this portion is reduced. Further, this facilitates the oxidation of the capacitive insulating film (9) at the corners (8A, 8B), so that the pinhole of the capacitive insulating film (9) is sufficiently reinforced by the oxide film.
Therefore, the breakdown voltage of the capacity of the memory cell can be improved.

[0017]

As described above, according to the present invention,
By the step of taper-etching the polysilicon film and forming the storage electrode with the sidewalls inclined, the bending of the capacitance insulating film on the upper and lower corners of the end of the storage electrode becomes small, and as a result, the stress applied to the capacitance insulating film is reduced. Since the size of the memory cell becomes small and it is easily oxidized, the withstand voltage of the capacity of the memory cell can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to the present invention.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to the present invention.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to the present invention.

FIG. 4 is a cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the present invention.

FIG. 5 is a cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the present invention.

FIG. 6 is a cross-sectional view illustrating a method of manufacturing a conventional semiconductor memory device.

FIG. 7 is a cross-sectional view illustrating the method of manufacturing the conventional semiconductor memory device.

FIG. 8 is a cross-sectional view illustrating the method of manufacturing the conventional semiconductor memory device.

FIG. 9 is a cross-sectional view illustrating the method of manufacturing the conventional semiconductor memory device.

FIG. 10 is a cross-sectional view illustrating the method of manufacturing the conventional semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Thick oxide film 3 Gate oxide film 4 Gate electrode 5 Source region 6 Drain region 7 Interlayer insulating film 8 Storage electrode 9 Capacitive insulating film 10 Cell plate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H01L 21/28 V 7376-4M 27/04 C 8427-4M

Claims (2)

[Claims] 1. A step of forming a MOS transistor of a memory cell on a semiconductor substrate, a step of forming an interlayer insulating film so as to cover the MOS transistor, and a contact with a source region of the MOS transistor,
Forming a polysilicon film so as to cover the entire surface of the interlayer insulation, forming a storage electrode having a sidewall inclined by taper-etching the polysilicon film, and covering the storage electrode A method of manufacturing a semiconductor memory device, comprising: a step of forming a capacitive insulating film; a step of oxidizing the capacitive insulating film; and a step of forming a cell plate electrode so as to cover the capacitive insulating film. . 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the capacitance insulating film is formed of a silicon nitride film.