JPH05109760A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent etching of an element isolating film in a side wall spacer forming process and thereby prevent formation of a parasitic MOS transistor in a semiconductor device comprising MOSFET having a side wall spacer at the main surface of a semiconductor substrate. CONSTITUTION:A side wall spacer 8 at the side wall of a gate electrode 4 has a double-layer structure comprising a lower layer consisting of a silicon oxide film 6 and an upper layer consisting of a silicon nitride film 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a semiconductor device, and more particularly to the structure of a MOSFET having a sidewall spacer.

[0002]

2. Description of the Related Art MOS having a sidewall spacer
A conventional structure of a semiconductor device having a FET is shown in FIG.

LDD structure MOSFE is formed on the semiconductor substrate 1.
After forming the low concentration region 5 of the source / drain region of T,
A sidewall spacer 10 formed by anisotropically etching a silicon oxide film of about 5000 Å is formed on the sidewall of the gate electrode 4, and the gate electrode 4 and the sidewall spacer 10 are used as a mask. Source·
A high concentration region 9 of the drain region is formed.

As described above, conventionally, the sidewall spacer is formed using only the silicon oxide film.

[0005]

However, forming a sidewall spacer using only a silicon oxide film as in the prior art has the following problems.

After forming the sidewall spacers by anisotropic etching of the silicon oxide film, an ion implantation process is performed to form high concentration regions of the source / drain regions. In this ion implantation step, if there is an etching residue of the silicon oxide film in the sidewall spacer formation step of the previous step, impurities will not sufficiently enter the semiconductor substrate in the ion implantation step, and the resistance of the source / drain regions will be reduced. Because the value becomes high, MOS
The transistor characteristics of the FET deteriorate. Further, when the impurity diffusion layer formed at the same time as the source / drain regions is used as a resistance element, the resistance value of this resistance element becomes high.

Therefore, in order to form low resistance source / drain regions and obtain good transistor characteristics,
In order to obtain a resistance element having a stable resistance value, it is necessary to prevent the silicon oxide film from remaining on the source / drain regions in the sidewall spacer forming step. Therefore, it is necessary to perform over-etching when forming the sidewall spacers in consideration of the variation in the film thickness of the silicon oxide film forming the sidewall spacers and the variation in the etching rate.

However, due to this over-etching,
The element isolation film made of silicon oxide film is also etched,
Since the thickness of the element isolation film becomes thin, the element isolation characteristics deteriorate and the parasitic MOS transistor is easily formed.

The conventional method of forming the sidewall spacers only with the silicon oxide film has such a problem.

Therefore, the present invention is intended to solve these problems, and it is an object of the present invention to provide a stable and low resistance semiconductor device including a MOSFET having a sidewall spacer on a semiconductor substrate. Na sauce
It is an object of the present invention to provide a semiconductor device having a drain region and, as a result, a MOSFET having good transistor characteristics and a resistance element having a stable resistance value.

[0011]

The semiconductor device of the present invention comprises:
M having a sidewall spacer on the main surface of a semiconductor substrate
In a semiconductor device including an OSFET, the sidewall spacer is characterized by having a two-layer structure in which a lower layer is a silicon oxide film and an upper layer is a silicon nitride film.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a structural sectional view of a semiconductor device according to the present invention, showing an example of a MOSFET having a source / drain region of an LDD structure.

An element isolation film 2, a gate oxide film 3, and a gate electrode 4 made of polycrystalline silicon are formed on a semiconductor substrate 1, and a lower layer of a silicon oxide film 6 and an upper layer of a gate electrode 4 are formed on a sidewall of the gate electrode 4. A sidewall spacer 8 made of a silicon nitride film 7 is formed, and further, the source / drain region of the LDD structure has a low concentration region 5 formed using the gate electrode 4 as a mask, the gate electrode 4 and the sidewall. The high-concentration region 9 is formed by using the spacer 8 as a mask.

An embodiment of the semiconductor device manufacturing method of the present invention will be described with reference to FIGS. 2 (a) to 2 (d).

First, as shown in FIG. 2A, the semiconductor substrate 1
A device isolation film 2, a gate oxide film 3, and a gate electrode 4 made of polycrystalline silicon are formed on the upper surface of the device, and low concentration regions 5 of the source / drain regions of the MOSFET are formed in a self-aligned manner using the gate electrode 4 as a mask.

Next, when the silicon nitride film is over-etched, the silicon oxide film 6 for preventing the low-concentration regions 5 of the source / drain regions and the gate electrode 4 from being etched is formed by a chemical vapor deposition method. To a thickness of about 500Å, and then a chemical vapor deposition method is used to form a silicon nitride film 7 of about 5000Å. This state is shown in FIG.

Next, the anisotropic etching of the silicon nitride film is performed by dry etching using SF ₆ gas or NF ₃ gas to form a silicon nitride film which will become the sidewall spacer 8 only on the side wall of the gate electrode 4. leave. At this time, since the etching rate of the silicon oxide film is about 1/10 of the etching rate of the silicon nitride film, even if the silicon nitride film is over-etched by 20%, the underlying silicon oxide film is etched only about 100Å. Next, the silicon oxide film on the low concentration regions 5 of the source / drain regions and on the gate electrode 4 is removed using an aqueous solution of hydrofluoric acid. At this time, the film thickness of the silicon oxide film is about 400 to 500 Å, which is smaller than the film thickness when the sidewall spacer is formed only by the conventional silicon oxide film. The film thickness at which the separation film is etched is extremely small compared to the conventional one. The state after etching the silicon oxide film is shown in FIG.

Next, as shown in FIG. 2D, the gate electrode 4
Also, the high-concentration regions 9 of the source / drain regions of the MOSFET are formed by ion implantation in a self-aligned manner using the sidewall spacers 8 as a mask.

After that, a MOSFET having an LDD structure can be obtained through a normal MOSFET formation process.

Although the specific description has been given based on the embodiment,
The present invention is not limited to the above-described embodiments. For example, the structure of the MOSFET is not limited to the LDD structure, but all MOSFETs having a side wall spacer on the side wall of the gate electrode such as a gate overlap LDD structure.
Can adapt at T.

[0022]

As described above, according to the present invention, a MOS having a sidewall spacer on the main surface of a semiconductor substrate.
In the semiconductor device including the FET, by forming the sidewall spacer with the two-layer structure of the silicon oxide film and the silicon nitride film, it is possible to prevent the element isolation film from being etched in the sidewall spacer formation step. It has a great effect that formation of a parasitic MOS transistor can be prevented.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a structure of a semiconductor device of the present invention.

FIG. 2 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a sectional view showing the structure of a conventional semiconductor device.

[Explanation of symbols]

1 semiconductor substrate 2 element isolation film 3 gate oxide film 4 gate electrode 5 low concentration region of source / drain region 6 silicon oxide film 7 silicon nitride film 8 sidewall spacer composed of silicon oxide film and silicon nitride film 9 source / drain region High concentration region 10 Sidewall spacer made of silicon oxide film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 21/318 C 8518-4M 27/088 8225-4M H01L 29/78 301 G

Claims (1)

[Claims] 1. A semiconductor device comprising a MOSFET having a sidewall spacer on a side wall of a gate electrode, wherein the sidewall spacer has a two-layer structure in which a lower layer is a silicon oxide film and an upper layer is a silicon nitride film. A semiconductor device characterized by.