JPH06245099A - Delay line device - Google Patents

Abstract

PURPOSE:To provide a delay line device usable in common regardless of the broadcasting system of television broadcasting. CONSTITUTION:This device is provided with a synchronizing signal detection means 2 for detecting synchronizing signals from among input signals and taking out the synchronizing signals, a PLL circuit 6 for outputting clock signals whose frequency is the multiple of the frequency of horizontal. synchronizing signals synchronized with the horizontal synchronizing signals of the synchronizing signals based on the detected synchronizing signals, a charge coupled element device circuit 12 for delaying and outputting the input signals and a driving pulse generation means 10 for generating driving pulses for driving the charge coupled element device circuit based on the clock signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay line device using a charge coupled device, and more particularly to a signal processing device for video signals.

[0002]

2. Description of the Related Art An example of a conventional delay line device is shown in FIG. The delay line device 40 includes a bias generation circuit 44, a clock driver 50, a charge coupled device 52, and a source follower circuit 54. The bias generation circuit 44 biases the input signal so that the dynamic range is widened. A video signal or a chroma signal is used as the input signal. The clock driver 50 generates drive pulses φ ₁ and φ ₂ for driving the charge coupled device 52 based on a clock input from the outside. The charge coupled device 52 delays the input signal by a predetermined time and sends it to the source follower circuit 54. The source follower circuit 54 current-amplifies the output of the charge coupled device 52 and outputs it to the outside. The delay time is a value determined by the number of stages of the charge coupled device and the frequency of the clock input.

Another example of the conventional delay line device is shown in FIG. This delay line device 41 is obtained by newly providing a PLL circuit 46 in the delay line device 40 shown in FIG. The PLL circuit 46 includes a comparator 47, a voltage controlled oscillator (hereinafter, also referred to as VCO) 48, and a 1/3 frequency divider 49, and has a frequency three times the frequency of a clock input input from the outside. The clock is generated, and this clock is sent to the clock driver 50. Therefore, in this delay line device 41, the charge coupled device 52 is driven at a frequency three times the frequency of the clock input inputted from the outside.

[0004]

Generally, the delay time required for the signal processing of the video signal which is the input signal of the above-mentioned delay line device is 1 times the frequency of the horizontal synchronizing signal in the video signal.
Double or double is required. The frequency of this horizontal synchronizing signal is the TV broadcasting system (for example, NTSC
Method or PAL method).

On the other hand, in the conventional delay line device, the charge coupled device is driven by the frequency of the clock input from the outside or a frequency which is a multiple thereof.

Therefore, when the conventional delay line device is used for the video signal processing of television broadcasting of different systems, it is necessary to change the number of stages of the charge coupled device or the frequency of the clock input. However, since the frequency of the clock input cannot be changed, the number of stages of the charge-coupled device has been changed in actuality. This means making a delay line device according to the television broadcasting system.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a delay line device which can be commonly used regardless of the television broadcasting system.

[0008]

A delay line device according to the present invention detects a synchronization signal from an input signal and extracts the synchronization signal, and a synchronization signal detection means for detecting the synchronization signal and the synchronization signal based on the detected synchronization signal. Synchronize with the signal horizontal sync signal,
A PLL circuit that outputs a clock signal having a frequency that is a multiple of the frequency of the horizontal synchronization signal, a charge-coupled device circuit that delays and outputs the input signal, and a drive that drives the charge-coupled device circuit based on the clock signal. Drive pulse generating means for generating a pulse.

[0009]

According to the delay line device of the present invention thus constructed, a signal synchronized with the horizontal synchronizing signal is generated and the charge coupled device circuit is driven based on this signal. As a result, it can be commonly used for different types of television broadcasting.

[0010]

FIG. 1 shows the configuration of a first embodiment of a delay line device according to the present invention. The delay line device 1 of this embodiment includes a horizontal synchronization signal detector 2, a bias generation circuit 4, a PLL circuit 6, a clock driver 10, a charge coupled device 12, and a charge coupled device 12.
The source follower circuit 14 is provided. The horizontal sync signal detector 2 extracts only the horizontal sync signal S ₂ from the video signal which is the input signal S ₁ . The bias generation circuit 4 biases the input signal S ₁ so that the dynamic range is widened. The PLL circuit 6 includes a phase comparator 7, a voltage controlled oscillator (also referred to as VCO) 8 and a frequency divider 9, and the frequency of the horizontal synchronizing signal S ₂ is based on the extracted horizontal synchronizing signal S ₂ . A clock signal S ₃ of a multiple of ₁ is generated, and this clock signal S ₃ is sent to the clock driver 10. The clock driver 10 generates drive pulses φ ₁ and φ ₂ based on the clock signal S ₃ to generate the charge coupled device 1
Drive 2 The charge coupled device 12 delays the input signal S ₁ for a predetermined time and sends it to the source follower circuit 14.

The delay time depends on the number of stages of the charge coupled device 12 and the clock signal S ₃ output from the PLL circuit 6.
Determined by the frequency of. Source follower circuit 14
Current-amplifies the output of the charge-coupled device 12.

Next, the operation of this embodiment will be described with reference to FIG. Here, the number of stages of the charge coupled device 12 is 910 bits, and the frequency divider 9 frequency-divides the output signal of the VCO 8 by 1/910. When the input signal S ₁ shown in FIG. 3A is input to the delay line device 1, the horizontal synchronizing signal detector ₂ extracts the horizontal synchronizing signal S ₂ shown in FIG. Is sent to the phase comparator 7.

On the other hand, the signal S ₃ output from the VCO 8 is frequency-divided by the frequency divider 9 by 1/910, and the frequency-divided signal S ₄ is sent to the phase comparator 7 (see FIG. 3 (d)). . Then, in the phase comparator 7, the phases of the signal S ₂ and the signal S ₄ are compared, and a control signal such that the phase difference becomes zero is output from the phase comparator 7 to the VCO 8. As a result, the VCO 8 outputs the clock signal S ₃ synchronized with the horizontal synchronizing signal and having a frequency 910 times the frequency of the horizontal synchronizing signal. Then, based on this clock signal S ₃ , the drive pulses φ ₁ and φ ₂ from the clock driver 10
Is output and the charge coupled device 12 is driven. Then,
A signal obtained by delaying the input signal S ₁ by one cycle of the horizontal synchronizing signal is output from the charge coupled device 12, and this signal is current-amplified by the source follower circuit 14 to be delayed by the delay line device 1.
(See FIG. 3E). That is, FIG.
The G region of the input signal S _{1 in} (a) is the signal S _{5 in} FIG. 3 (e).
Then, the horizontal synchronizing signal is output to the H region with a delay of one cycle.

In the above embodiment, the charge coupled device 12 is used.
Although the number of stages of the charge-coupled device 12 is 1820 bits and the frequency of the frequency divider 9 is 1/910, the horizontal synchronizing signal is A signal delayed by the period can be obtained as the output signal S ₅ of the delay line device 1.

As described above, according to this embodiment, the signal synchronized with the horizontal synchronizing signal is generated and the charge-coupled device 12 is driven based on this signal. Can be used.

The configuration of the second embodiment of the delay line device according to the present invention is shown in FIG. The delay line device 1A of this embodiment is used when the input signal S ₁ includes a horizontal synchronizing signal and a vertical synchronizing signal. In the delay line device 1 shown in FIG. A synchronization signal detector 2A is provided instead of 2, and a phase comparator 7A is provided instead of the phase comparator 7.

The synchronizing signal detector 2A extracts a synchronizing signal S ₂ ′, that is, a horizontal synchronizing signal and a vertical synchronizing signal from the input signal S ₁ input to the delay line device 1A. Further, the phase comparator 7A, based on the extracted synchronizing signal S ₂ ′, the vertical synchronizing signal input from the outside, and the signal S ₄ output from the frequency divider 9, outputs a horizontal synchronizing signal and a frequency divider 9 Control signal such that the phase difference from the signal S ₄ from
Send to O8. That is, the phase comparator 7A operates so as to eliminate the influence of the vertical synchronizing signal.

Since the delay line device 1A of the second embodiment also generates a signal synchronized with the horizontal synchronizing signal and drives the charge coupled device 12 based on this signal, it is commonly used for television broadcasting of different systems. Can be used.

[0019]

According to the present invention, since a signal synchronized with the horizontal synchronizing signal is generated and the charge coupled device is driven based on this signal, it can be commonly used for television broadcasting of different systems. .

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of a delay line device according to the present invention.

FIG. 2 is a block diagram showing the configuration of a second embodiment of the delay line device according to the present invention.

FIG. 3 is a timing chart explaining the operation of the first embodiment.

FIG. 4 is a block diagram showing an example of a conventional delay line device.

FIG. 5 is a block diagram showing another example of a conventional delay line device.

[Explanation of symbols]

 1 Delay Line Device 2 Horizontal Sync Signal Detector 4 Bias Generation Circuit 6 PLL Circuit 7 Phase Comparator 8 Voltage Controlled Oscillator (VCO) 9 Frequency Divider 10 Clock Driver 12 Charge Coupled Device 14 Source Follower Circuit

Claims (1)

[Claims] 1. A horizontal synchronization signal detecting means for detecting a synchronization signal from an input signal and extracting the synchronization signal, and the horizontal synchronization for synchronizing with the horizontal synchronization signal of the synchronization signal based on the detected synchronization signal. A PLL circuit that outputs a clock signal having a frequency that is a multiple of the frequency of the signal, a charge-coupled device circuit that delays and outputs the input signal, and a drive pulse that drives the charge-coupled device circuit based on the clock signal And a drive pulse generating means for operating the delay line device.