JPH06244302A - Injection-molded printed board - Google Patents

Injection-molded printed board

Info

Publication number
JPH06244302A
JPH06244302A JP50A JP2870293A JPH06244302A JP H06244302 A JPH06244302 A JP H06244302A JP 50 A JP50 A JP 50A JP 2870293 A JP2870293 A JP 2870293A JP H06244302 A JPH06244302 A JP H06244302A
Authority
JP
Japan
Prior art keywords
bare chip
semiconductor bare
injection
substrate
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50A
Other languages
Japanese (ja)
Inventor
Tomohiro Inoue
智広 井上
Shigenari Takami
茂成 高見
Takeshi Kasahara
健 笠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP50A priority Critical patent/JPH06244302A/en
Publication of JPH06244302A publication Critical patent/JPH06244302A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent reduction in the workability and bonding reliability of the wire bonding of a semiconductor pair chip to be mounted on an injection- molded printed board. CONSTITUTION:In an injection-molded printed board O, recesses 9a and 9b are provided at the position where the semiconductor chip 3 is to be mounted and at the corresponding position on the rear of the board, and the thickness of the board in the position where the semiconductor chip 3 is to be mounted is made about 2mm or less. As a result, when the semiconductor chip and a conductor pattern are connected by wire bonding on the injection-molded printed board, the heat applied from the rear of the board sufficiently propagates to the semiconductor chip and the conductor pattern in a short time, and thus, reduction in the workability and bonding reliability of the wire bonding can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体ベアチップを実
装する射出成形プリント基板の構造に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of an injection-molded printed circuit board on which a semiconductor bare chip is mounted.

【0002】[0002]

【従来の技術】半導体ベアチップを従来のプリント基板
に実装した例を図3に基づき説明する。図3(a)は半
導体ベアチップの実装基板として多く用いられているガ
ラスエポキシ基板に実装した例で、このガラスエポキシ
基板1は元来、厚みが均一な基板であり、半導体ベアチ
ップ3を実装する場合、基板厚みは、1.6mm以下の
ものが用いられている。これはワイヤーボンディング
は、基板裏面から半導体ベアチップ3を加熱しながら行
わなければならないため、その熱が半導体ベアチップ3
に十分伝わるように考慮したものである。ボンダーから
の熱が伝わりにくいと、昇温に時間がかかり作業性が低
下すると共に、到達温度が低くなりボンドのはがれ等が
発生し、ワイヤーボンディングの接合信頼性が低下す
る。なお、2a,2bは基板表面に設けた導体パター
ン、4は半導体ベアチップ3を導体パターン2aに固定
するダイボンドペースト、5は半導体ベアチップ3の電
極パッドと導体パターン2bを接続するボンディングワ
イヤー、6は半導体ベアチップ3及びボンディングワイ
ヤー5を保護する封止樹脂である。
2. Description of the Related Art An example in which a semiconductor bare chip is mounted on a conventional printed board will be described with reference to FIG. FIG. 3A shows an example of mounting on a glass epoxy substrate which is often used as a mounting substrate for a semiconductor bare chip. The glass epoxy substrate 1 is originally a substrate having a uniform thickness, and the semiconductor bare chip 3 is mounted on the glass epoxy substrate 1. A substrate having a thickness of 1.6 mm or less is used. This is because wire bonding must be performed while heating the semiconductor bare chip 3 from the back surface of the substrate, so that heat is applied to the semiconductor bare chip 3.
It has been taken into consideration so that it can be fully transmitted. If the heat from the bonder is difficult to be transferred, it takes a long time to raise the temperature, which lowers the workability, lowers the reached temperature, causes peeling of the bond, and reduces the bonding reliability of the wire bonding. 2a and 2b are conductor patterns provided on the substrate surface, 4 is a die bond paste for fixing the semiconductor bare chip 3 to the conductor pattern 2a, 5 is a bonding wire for connecting the electrode pad of the semiconductor bare chip 3 and the conductor pattern 2b, and 6 is a semiconductor It is a sealing resin that protects the bare chip 3 and the bonding wire 5.

【0003】また、異なる従来例を図3(b)に示す。
この例は、電力の消費が大きいパワーデバイスの半導体
ベアチップを実装する場合のもので、図中、7は放熱性
の良いAl等の金属製のベース基板、8はエポキシ樹脂
等の絶縁層であり、その他の構成は図3(a)と同様で
あるので同等構成については同符号を付している。この
基板は、例えば、ベース基板7上に絶縁層8を形成後、
その上に銅箔を接着し、不要な銅箔をエッチング除去す
ることにより導体パターン2a,2bを形成して製造さ
れる。この基板の場合、ベース基板7が金属製で半導体
ベアチップ3に基板裏面から熱を伝えやすいため、上述
のようなワイヤーボンディング時の作業性及び接合信頼
性の低下の不具合は発生しないが、基板全面にわたって
金属製のベース基板を設ける必要があり、導体パターン
設計にも制約を与えていた。
Further, another conventional example is shown in FIG.
This example is for mounting a semiconductor bare chip of a power device that consumes a large amount of power. In the figure, 7 is a metal base substrate such as Al having good heat dissipation, and 8 is an insulating layer such as epoxy resin. Since other configurations are the same as those in FIG. 3A, the same reference numerals are given to the same configurations. In this substrate, for example, after the insulating layer 8 is formed on the base substrate 7,
It is manufactured by bonding a copper foil thereon and removing unnecessary copper foil by etching to form the conductor patterns 2a and 2b. In the case of this substrate, since the base substrate 7 is made of metal and heat is easily transferred to the semiconductor bare chip 3 from the back surface of the substrate, the above-described problems of deterioration in workability and bonding reliability during wire bonding do not occur, but the entire substrate surface It was necessary to provide a metal base substrate over the entire length, which also constrained the conductor pattern design.

【0004】一方、射出成形プリント基板に半導体ベア
チップを実装する場合を図3(c)に示す。図中、9は
射出成形プリント基板で、通常ポリエーテルイミド樹
脂、液晶ポリマー、ポリフェニレンサルファイド樹脂等
の高耐熱熱可塑性樹脂がその材料として用いられるが、
図3(c)は、かかる基板の板厚が厚い箇所(略2mm
を越える箇所)に半導体ベアチップ3が実装された状態
を示すものである。この場合、基板が樹脂製で熱伝導が
悪いため、基板裏面からの熱が半導体ベアチップ3に伝
わりにくく、上述のようなワイヤーボンディング時の不
具合が発生することになる。その他、従来例と同等構成
については同符号を付している。この例に使用される射
出成形プリント基板9は、例えば、射出成形された成形
品にCuメッキを全面に施し、不要部分をエッチングに
より除去して導体パターン2a,2bを形成した後、ワ
イヤーボンディングに必要なNi及びAuメッキを導体
パターン2a,2b上に施すという工程によって製造さ
れる。
On the other hand, FIG. 3C shows a case where a semiconductor bare chip is mounted on an injection-molded printed board. In the figure, 9 is an injection molded printed circuit board, which is usually made of high heat resistant thermoplastic resin such as polyetherimide resin, liquid crystal polymer and polyphenylene sulfide resin.
FIG. 3C shows a portion where the plate thickness of the substrate is large (approximately 2 mm).
2 shows a state in which the semiconductor bare chip 3 is mounted on a portion (exceeding the point). In this case, since the substrate is made of resin and the heat conduction is poor, heat from the rear surface of the substrate is difficult to be transferred to the semiconductor bare chip 3, and the above-described problem at the time of wire bonding occurs. In addition, the same components as those in the conventional example are designated by the same reference numerals. The injection-molded printed circuit board 9 used in this example is, for example, wire-bonded after the injection-molded product is plated with Cu and the unnecessary portions are removed by etching to form the conductor patterns 2a and 2b. It is manufactured by a process of performing necessary Ni and Au plating on the conductor patterns 2a and 2b.

【0005】[0005]

【発明が解決しようとする課題】上記のように、従来の
射出成形プリント基板に半導体ベアチップを実装する場
合、基板板厚の厚い箇所に実装すると、基板裏側から加
えた熱が半導体ベアチップ及びそれと接続する導体パタ
ーンに伝わりにくいため、ワイヤーボンディングの作業
性及び接合信頼性の低下を招いていた。
As described above, when a semiconductor bare chip is mounted on a conventional injection-molded printed circuit board, if the semiconductor bare chip is mounted on a thick part of the board, the heat applied from the backside of the board is connected to the semiconductor bare chip and it. Since it is difficult to reach the conductive pattern, the workability of wire bonding and the joint reliability are deteriorated.

【0006】本発明は、上記問題点に鑑みなされたもの
で、その目的とするところは、半導体ベアチップ及び導
体パターンの昇温不足によるワイヤーボンディングの作
業性及び接合信頼性の低下を防止できる射出成形プリン
ト基板の構造を提供することにある。
The present invention has been made in view of the above problems. An object of the present invention is to perform injection molding capable of preventing workability and bonding reliability of wire bonding from being lowered due to insufficient temperature rise of a semiconductor bare chip and a conductor pattern. It is to provide a structure of a printed circuit board.

【0007】[0007]

【課題を解決するための手段】上記課題を解決するため
本発明は、半導体ベアチップを実装する射出成形プリン
ト基板において、前記半導体ベアチップ実装位置及びそ
の基板裏側位置の少なくとも一方に凹部を形成して、前
記半導体ベアチップ実装位置の基板板厚を略2mm以下
としたことを特徴とするものである。
In order to solve the above-mentioned problems, the present invention provides an injection-molded printed circuit board for mounting a semiconductor bare chip, wherein a recess is formed in at least one of the semiconductor bare chip mounting position and the substrate backside position, The board thickness at the semiconductor bare chip mounting position is approximately 2 mm or less.

【0008】また、異なる手段として、半導体ベアチッ
プを実装する射出成形プリント基板において、前記半導
体ベアチップ実装位置及びその基板裏側位置で、少なく
とも基板裏側位置に凹部を形成して、前記半導体ベアチ
ップ実装位置の基板板厚を略2mm以下とし、前記基板
裏側位置の前記凹部に熱伝導性の良い良熱伝導体を配置
したことを特徴とするものである。
As another means, in an injection-molded printed circuit board on which a semiconductor bare chip is mounted, a recess is formed at least at the substrate backside position at the semiconductor bare chip mounting position and the substrate backside position, and the substrate at the semiconductor bare chip mounting position is formed. The plate thickness is set to about 2 mm or less, and a good thermal conductor having good thermal conductivity is arranged in the concave portion on the back side of the substrate.

【0009】[0009]

【作用】本発明の射出成形プリント基板において、半導
体ベアチップ実装位置やその基板裏側位置に形成した凹
部は、半導体ベアチップ実装位置の基板板厚を局部的に
薄くし、ワイヤーボンディングのために基板裏側から加
えた熱が半導体ベアチップや導体パターンに伝わりやす
くする。
In the injection-molded printed circuit board of the present invention, the recesses formed at the semiconductor bare chip mounting position and the substrate back side position locally thin the board thickness at the semiconductor bare chip mounting position, and the wire is bonded from the back side of the substrate for wire bonding. Makes it easier for the applied heat to be transferred to the semiconductor bare chip and conductor pattern.

【0010】また、半導体ベアチップ実装位置の基板裏
側の凹部に配置された熱伝導性の良い良熱伝導体は、ワ
イヤーボンディングのために基板裏側から加えた熱が半
導体ベアチップや導体パターンに伝わりやすくする。
Further, the good thermal conductor having good thermal conductivity arranged in the recess on the back side of the substrate at the semiconductor bare chip mounting position facilitates the transfer of heat applied from the back side of the substrate for wire bonding to the semiconductor bare chip and the conductor pattern. .

【0011】[0011]

【実施例】図1は本発明の一例を示すもので、図3
(c)の従来例に対して、射出成形プリント基板9の半
導体ベアチップ3の実装位置及びその基板裏側位置に凹
部9a,9bを形成し、実装位置の基板板厚を略2mm
以下としたことを特徴とするものであり、その他の構成
は、前記従来例と同等であるため同一構成に同符号を付
すことにより説明を省略する。
FIG. 1 shows an example of the present invention.
As compared with the conventional example of (c), recesses 9a and 9b are formed at the mounting position of the semiconductor bare chip 3 of the injection molded printed circuit board 9 and the position on the back side of the substrate, and the board thickness at the mounting position is approximately 2 mm.
Since the other configurations are the same as those of the conventional example, the description thereof will be omitted by giving the same reference numerals to the same configurations.

【0012】半導体ベアチップ3は従来と同様に、Ag
ペースト等のダイボンドペースト4を介して射出成形プ
リント基板9の凹部9aに実装された後、Agワイヤー
等のワイヤーボンディングにより導体パターン2bと接
続され、半導体ベアチップ3及びボンディングワイヤー
5の保護のため樹脂封止されるが、ワイヤーボンディン
グ時、半導体ベアチップ3及び導体パターン2bの温度
は、基板裏側の凹部9bからの加熱によって、ワイヤー
ボンディングに必要な温度にまで短時間で上昇するた
め、ワイヤーボンディングの作業性及び接合信頼性の低
下を引き起こすことがない。
The semiconductor bare chip 3 is made of Ag as in the conventional case.
After being mounted in the recess 9a of the injection-molded printed circuit board 9 through the die-bonding paste 4 such as paste, it is connected to the conductor pattern 2b by wire bonding such as Ag wire, and is sealed with resin to protect the semiconductor bare chip 3 and the bonding wire 5. However, at the time of wire bonding, the temperature of the semiconductor bare chip 3 and the conductor pattern 2b rises to the temperature required for wire bonding in a short time by heating from the recess 9b on the back side of the substrate. Also, it does not cause a decrease in joint reliability.

【0013】なお、凹部9a,9bの形状は、上記実施
例に限定されるものではなく、半導体ベアチップ3及び
導体パターン2a,2bの大きさ及び位置、ボンディン
グ装置の形状、加熱方法等の条件に合うように変えれば
よい。
The shapes of the recesses 9a and 9b are not limited to those in the above-described embodiment, but may be changed depending on the size and position of the semiconductor bare chip 3 and the conductor patterns 2a and 2b, the shape of the bonding apparatus, the heating method and the like. Just change it to fit.

【0014】図2は異なる実施例を示すもので、射出成
形プリント基板9の半導体ベアチップ3実装位置裏側に
形成された凹部にCu等の熱伝導性の良い部材を良熱伝
導体10として一体成形したものであり、従来例と同等
の構成については、同符号を付している。
FIG. 2 shows a different embodiment, in which a member having good thermal conductivity such as Cu is integrally molded as a good thermal conductor 10 in a recess formed on the rear side of the mounting position of the semiconductor bare chip 3 on the injection molded printed board 9. The same components as those of the conventional example are designated by the same reference numerals.

【0015】この例でも半導体ベアチップ3実装位置の
基板板厚は、略2mm以下に設定されているので、図1
の例と同様にワイヤーボンディング時の不具合を防止す
ることができる。また、この良熱伝導体10は、半導体
ベアチップ3から発生する熱を放熱する作用もあるの
で、発熱量の大きいパワーデバイスの半導体ベアチップ
3を実装する場合に適している。
Also in this example, the board thickness at the mounting position of the semiconductor bare chip 3 is set to about 2 mm or less.
Similar to the example of 1, the problem at the time of wire bonding can be prevented. Further, since the good thermal conductor 10 also has a function of radiating the heat generated from the semiconductor bare chip 3, it is suitable for mounting the semiconductor bare chip 3 of a power device having a large heat generation amount.

【0016】良熱伝導体10の材料は、Cuに限定され
るものではなく、Alや金属以外の材料も適用できる。
また、この例では、良熱伝導体10を一体成形により基
板の凹部に配置したが、基板成形後に取り付けるように
してもよい。
The material of the good thermal conductor 10 is not limited to Cu, and materials other than Al and metal can be applied.
Further, in this example, the good thermal conductor 10 is arranged in the recess of the substrate by integral molding, but it may be attached after molding the substrate.

【0017】また、射出成形プリント基板は図1のよう
に構成しておき、この基板を機器に組み込んだ状態で基
板裏側の凹部に熱伝導率の良い別部材が当接するように
構成してもよい。
Alternatively, the injection-molded printed circuit board may be constructed as shown in FIG. 1 and another member having a high thermal conductivity may be brought into contact with the concave portion on the back side of the board in a state where the board is incorporated in a device. Good.

【0018】[0018]

【発明の効果】以上のように構成することで、射出成形
プリント基板上で半導体ベアチップと導体パターンをワ
イヤーボンディングにより接続する際、基板裏側から加
えた熱が半導体ベアチップ及び導体パターンに短時間に
十分伝わるため、ワイヤーボンディングの作業性及び接
合信頼性の低下を防止することができる。
As described above, when the semiconductor bare chip and the conductor pattern are connected by wire bonding on the injection-molded printed circuit board, the heat applied from the back side of the substrate is sufficiently applied to the semiconductor bare chip and the conductor pattern in a short time. Since it is transmitted, it is possible to prevent the workability of wire bonding and the decrease of the joint reliability.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の射出成形プリント基板を用いて半導体
ベアチップを実装した一例を示す断面図である。
FIG. 1 is a cross-sectional view showing an example in which a semiconductor bare chip is mounted using an injection-molded printed board according to the present invention.

【図2】本発明の射出成形プリント基板を用いて半導体
ベアチップを実装した異なる例を示す断面図である。
FIG. 2 is a cross-sectional view showing another example in which a semiconductor bare chip is mounted using the injection-molded printed board of the present invention.

【図3】(a)は従来のプリント基板に半導体ベアチッ
プを実装した一例を示す断面図、(b)は従来のプリン
ト基板に半導体ベアチップを実装した異なる例を示す断
面図であり、(c)は従来の射出成形プリント基板に半
導体ベアチップを実装した一例を示す断面図である。
FIG. 3A is a sectional view showing an example in which a semiconductor bare chip is mounted on a conventional printed circuit board, FIG. 3B is a sectional view showing a different example in which a semiconductor bare chip is mounted on a conventional printed circuit board, and FIG. FIG. 6 is a cross-sectional view showing an example in which a semiconductor bare chip is mounted on a conventional injection-molded printed board.

【符号の説明】[Explanation of symbols]

1 プリント基板 2a,2b 導体パターン 3 半導体ベアチップ 4 ダイボンドペースト 5 ボンディングワイヤー 6 封止樹脂 7 ベース基板 8 絶縁層 9 射出成形プリント基板 9a,9b 凹部 10 良熱伝導体 1 Printed Circuit Boards 2a, 2b Conductor Pattern 3 Semiconductor Bare Chip 4 Die Bond Paste 5 Bonding Wire 6 Sealing Resin 7 Base Board 8 Insulation Layer 9 Injection Molded Printed Circuit Boards 9a, 9b Recess 10 Good Thermal Conductor

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体ベアチップを実装する射出成形プ
リント基板において、前記半導体ベアチップ実装位置及
びその基板裏側位置の少なくとも一方に凹部を形成し
て、前記半導体ベアチップ実装位置の基板板厚を略2m
m以下としたことを特徴とする射出成形プリント基板。
1. In an injection-molded printed circuit board on which a semiconductor bare chip is mounted, a recess is formed in at least one of the semiconductor bare chip mounting position and the substrate backside position, and the board thickness of the semiconductor bare chip mounting position is approximately 2 m.
An injection-molded printed circuit board characterized by having a thickness of m or less.
【請求項2】 半導体ベアチップを実装する射出成形プ
リント基板において、前記半導体ベアチップ実装位置及
びその基板裏側位置で、少なくとも基板裏側位置に凹部
を形成して、前記半導体ベアチップ実装位置の基板板厚
を略2mm以下とし、前記基板裏側位置の前記凹部に熱
伝導性の良い良熱伝導体を配置したことを特徴とする射
出成形プリント基板。
2. In an injection-molded printed circuit board on which a semiconductor bare chip is mounted, a recess is formed at least at the substrate backside position at the semiconductor bare chip mounting position and the substrate backside position thereof, and the substrate board thickness at the semiconductor bare chip mounting position is substantially equal. An injection-molded printed circuit board having a length of 2 mm or less, and a good thermal conductor having good thermal conductivity being disposed in the recessed portion at the back side of the substrate.
JP50A 1993-02-18 1993-02-18 Injection-molded printed board Pending JPH06244302A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50A JPH06244302A (en) 1993-02-18 1993-02-18 Injection-molded printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50A JPH06244302A (en) 1993-02-18 1993-02-18 Injection-molded printed board

Publications (1)

Publication Number Publication Date
JPH06244302A true JPH06244302A (en) 1994-09-02

Family

ID=12255799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50A Pending JPH06244302A (en) 1993-02-18 1993-02-18 Injection-molded printed board

Country Status (1)

Country Link
JP (1) JPH06244302A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6094354A (en) * 1996-12-03 2000-07-25 Nec Corporation Chip component mounting board, chip component mounting structure, and method of manufacturing chip component mounting board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6094354A (en) * 1996-12-03 2000-07-25 Nec Corporation Chip component mounting board, chip component mounting structure, and method of manufacturing chip component mounting board

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