JPH0624196B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a through hole that connects upper layer wiring and lower layer wiring of a multilayer wiring to each other.

[Conventional technology]

In general, the formation of through holes requires a large opening from the bottom to the top so that good coverage characteristics can be obtained. There are two conventional methods for obtaining a through hole of this shape. One of them is a method of directly opening the interlayer insulating film by using an isotropic etching technique,
The other is a method in which the photolithography process and the etching process of the interlayer insulating film are repeated a plurality of times to gradually expand the opening.

2 (a)-(b) and 3 (a)-(f) are process sequence diagrams for explaining a conventional through-hole forming method, respectively.
It corresponds to each of the above two methods. The first isotropic etching method will be described with reference to FIG.
As shown in (a), a lower layer wiring 2 is first formed on a semiconductor substrate 1 and then an interlayer insulating film 3 mainly made of silicon oxide is formed.
And the flattening film 4 are respectively formed. The flattening film 4 is mainly composed of a silica coating film and acts so as to smooth the steps of the interlayer insulating film 3 by heat treatment. Then, as shown in FIG. 2 (b), etching with a liquid mainly containing hydrofluoric acid is performed using the photoresist film 8 as a mask, and the upper portion of the interlayer insulating film 3 is isotropically removed by etching. Immediately thereafter, if reactive ion etching is performed using the photoresist film 8 as a mask, a through hole that is largely opened upward from the lower portion as shown in FIG. 2 (c) is opened. Accordingly, by depositing the upper layer wiring 6 on this, a semiconductor device having the structural wiring shown in FIG. 2D can be obtained.

Further, when the method of expanding the opening stepwise is used, the lower layer wiring 2, the interlayer insulating film 3 and the planarizing film (silica) 4 are first formed on the semiconductor substrate as in the above method. [Fig. 3 (a)]. Then, as shown in FIG. 3B, an opening having a diameter larger than desired is formed on the interlayer insulating film 3 using the photoresist film 8 as a mask. Reactive ion etching is used to form this opening, and it is taken into consideration that side etching does not occur in the flattening film 4. Here, the photoresist film 8 is removed, and a through hole is opened as shown in FIG. 3 (C) by using the photoresist film 8'which has been newly reapplied by carrying out photolithography again. Therefore, if the upper layer wiring 6 is finally formed on the through hole opening, the wiring structure shown in FIG. 3D is obtained.

[Problems to be solved by the invention]

However, in the forming method using the first isotropic etching technique, the etching rate with hydrofluoric acid is
Since the flattening film 4 is several times larger than the above, the flattening film 4 in the upper layer is etched in a shape wider than desired. That is, the side etching often causes the step to be removed, resulting in a failure such as a step break in the upper layer wiring 6 or a short circuit between the wirings. In addition, according to the second stepwise widening of the opening, in this method, the photoresist process is performed a plurality of times, so that misalignment of the photo mask is likely to occur, and the misalignment between the opening and the stepped portion between the openings is increased. This occurs as an unavoidable problem in manufacturing. If such a deviation occurs in the manufacturing stage, a portion where it is difficult to cover the upper layer wiring 6 is formed in the through hole step portion, so that a conduction failure accident often occurs.

FIG. 4 and FIG. 5 are schematic diagrams of defective shapes generated by the conventional through hole forming method, and the above description is made clearer with reference to the drawings. Conventionally, these problems have been that the occurrence of defects is minimized by increasing the design margin, but with respect to the trend of miniaturization of elements, which is rapidly progressing recently, It becomes a serious obstacle.

In view of the above situation, an object of the present invention is to provide a method of manufacturing a semiconductor device including a step of forming a through hole that does not cause etching deviation in the opening.

[Means for solving problems]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a lower layer wiring on a semiconductor substrate, a step of forming an interlayer insulating film and a planarizing film on the lower layer wiring, respectively, and a polymer film on the planarizing film. A step of forming a laminated film of insulating films,
A patterning step of selectively opening the insulating film; an oxygen gas plasma etching step of selectively opening the polymer film through an opening pattern of the insulating film; and a laminated opening pattern of the insulating film and the polymer film. And a through-hole forming step including an anisotropic etching step of opening the laminated film of the planarizing film and the interlayer insulating film to the depth reaching the lower wiring surface in parallel with the removal of the insulating film. .

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

1 (a) to 1 (f) are process sequence diagrams showing one embodiment of the present invention. First, as shown in FIG. 1A, a lower layer wiring 2 is formed on the surface of a semiconductor substrate 1, and an interlayer insulating film 3, a flat film 4, a dry-etching resistant polymer film 5 and an insulating film 7 are sequentially formed on the lower wiring 2. Put it on. At this time, the insulating film 7 has the same etching rate as that of the interlayer insulating film 3 by the reactive ion etching, and the film thickness is set to about half of that of the interlayer insulating film 3. It can be easily grown by using an ordinary means such as a plasma CVD method or a sputtering method. Then, as shown in FIG. 1B, only the uppermost insulating film 7 is opened by using the photolithography technique. Here, the photoresist 8 is removed, the side etching of the polymer film 5 is performed as shown in FIG. 1 (c) by using the oxygen gas plasma technique, and then the reactive ion etching method is performed as shown in FIG. 1 (d). Thus, the insulating film 7 is removed and the interlayer insulating film 3 is opened at the same time. In this case, after the insulating film 7 is completely removed, if reactive ion etching is continued, the stepwise etching is performed as shown in FIG. That is, since holes are formed on the lower layer wiring 2 until reaching the lower layer wiring 2, and at the same time, the peripheral portion is also formed with a stepwise opened upper portion, the upper layer wiring 6 is removed after the polymer film 5 is removed. By forming the above, a semiconductor device having an ideal through hole having a structure as shown in FIG. 1 (f) can be obtained.

〔The invention's effect〕

As described in detail above, according to the present invention, only anisotropic etching technology (reactive plasma etching technology) is used as an etching means when a through hole is opened, and only one photo etching is performed.・ Since a cross-sectional shape that gradually expands from the lower part to the upper part can be achieved by a lithographic method, a side etching phenomenon of a planarizing film that occurs when the interlayer insulating film is isotropically etched with hydrofluoric acid or multiple photo It is possible to avoid misalignment that occurs when the through holes are opened stepwise by using a lithography process. Therefore, a defect such as step breakage, short circuit or disconnection of the upper layer wiring does not occur, so that a large mask design margin is not required at all, and miniaturization of the semiconductor element can be easily achieved with extremely high production efficiency.

[Brief description of drawings]

1 (a) to 1 (f) are process sequence diagrams showing one embodiment of the present invention,
2 (a) to (d) and 3 (a) to (d) are process sequence diagrams for explaining a conventional through hole forming method, and FIGS. 4 and 5 are conventional process diagrams. It is a model figure of the defective shape generated by the through hole forming method. 1 ... semiconductor substrate, 2 ... lower layer wiring, 3 ... interlayer insulating film, 4 ... planarizing film (silica), 5 ... polymer film, 6 ...
... Upper layer wiring, 7 ... Insulating film, 8,8 '... Photo resist film.

Claims (1)

[Claims] 1. A step of forming a lower layer wiring on a semiconductor substrate, a step of forming an interlayer insulating film and a planarizing film on the lower layer wiring, respectively, and a laminated film of a polymer film and an insulating film on the planarizing film. A patterning step of selectively opening the insulating film, and an oxygen gas selectively opening the polymer film through an opening pattern of the insulating film.
Anisotropic process of opening the laminated film of the planarization film and the interlayer insulating film to the depth reaching the lower wiring surface in parallel with the removal of the insulating film through the plasma etching step and the laminated opening pattern of the insulating film and the polymer film And a through hole forming step including a conductive etching step.