JPH06237272A - Receiver - Google Patents

Abstract

PURPOSE:To save the current consumption of an FSK receiver by interruptedly operating a PLL local oscillation circuit which generates the local oscillation frequency of the FSK receiver which orthogonally detects and demodulates an FSK modulated wave. CONSTITUTION:A PLL circuit 109, a VCO 111, and a loop filter 112 constitute a PLL local oscillation circuit to output the local oscillation frequency. A 90 deg. phase shifter 108 sends two local oscillation frequencies, which have 90 deg. phase difference by phase shift, to mixer circuits 102a and 102b. After a base band signal is sent, a demodulated signal is outputted through LPFs 103a and 103b, limiter circuits 104a and 104b, a demodulating circuit 105, an LPF 106, and a comparator 107. A frequency detecting circuit 110 uses the base band signal to detect the difference between the line frequency and the PLL local oscillation frequency. Only when this difference exceeds a set value, the PLL operation is normally performed to secure the synchronism; and while the synchronism is secured, the PLL operation is stopped to keep the synchronism securing state by the free-running output of the VCO 111.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to receivers, and more particularly to P.
F using the local oscillation frequency generated by the LL circuit
Quadrature detection reception system FS for quadrature detection demodulation of SK modulated wave
Regarding the K receiver.

[0002]

2. Description of the Related Art In recent years, advances in integrated circuit technology have made receivers smaller. However, taking the wireless unit as an example, since the circuit basic method is the same, it is the current situation that the miniaturization is approaching due to the existence of elements that cannot be integrated or are difficult to integrate.

For example, in a super-heterodyne receiver, high frequency and intermediate frequency filters require a large area. A quadrature detection reception system has been proposed for this reduction in size and weight.

In the quadrature detection reception system, the line frequency to be received and the local oscillation frequency are made equal, a beat between the reception frequency and the local oscillation frequency is extracted by a mixer, and then a low pass filter (LPF) is applied to extract only the baseband signal. In this method, the beat is extracted, the amplitude is limited by a limiter circuit, and then demodulated to obtain a demodulated signal.

This quadrature detection reception system is characterized in that there is no image frequency because the intermediate frequency becomes zero because the local oscillation frequency and the line frequency match. This means that no high selective filter for attenuating the image frequency is required in the high frequency amplifier and the intermediate frequency amplifier.

Further, since the intermediate frequency of the channel filter for attenuating the adjacent channel interference wave is zero, it can be constituted by an active filter of low frequency, which can be realized on an integrated circuit.

Next, as a conventional technique combined with this quadrature detection reception, a PLL (Phase Locked L) capable of receiving many line frequencies with one crystal oscillator.
loop, phase-locked loop) for local oscillation circuit
There is a K receiver.

When the line frequency is set depending on the area like the selective call receiver, when the called party moves to another area, the selective call receiver with the fixed local oscillation frequency cannot call. On the other hand, the selective call receiver using the PLL in the local oscillation circuit can call the call without any problem.

[0009]

By using the above-mentioned quadrature detection reception system, it is possible to reduce high frequency filters, intermediate frequency filters, etc., so that the size and weight of the receiver can be reduced. Become.

Further, by using the quadrature detection reception system, a high frequency filter and the like are not required, so that it is not necessary to change the high frequency filter for each frequency, which is required in the single super hetero die system.

However, compared with a fixed crystal oscillator circuit, the PLL oscillator circuit has a problem that the current consumption increases because of the PLL control. Especially, in a selective call receiver which is battery driven and has a small battery capacity. However, the battery life was extremely short, which was a big problem.

The object of the present invention is to solve the above-mentioned problems,
It is an object of the present invention to provide a receiver capable of remarkably suppressing current consumption even if the local oscillation frequency of the PLL is used.

Still another object of the present invention is to provide a quadrature detection reception type FSK receiver which can be expected to have a long life.

[0014]

According to the present invention, a modulated wave having a line frequency, the line frequency being modulated by a baseband signal of a binary digital signal, is received, and reproduced from the modulated wave. In a receiver equipped with a demodulation unit for obtaining a digital signal, a predetermined control is performed when an offset amount of the baseband signal from the line frequency is obtained and the offset amount is not within a predetermined range. An offset amount detection circuit that outputs a signal, a controllable local oscillation unit that secures a phase locked loop for the modulated wave, and sends a signal having a local oscillation frequency to the demodulation unit, the local oscillation unit, and the It is provided between the offset amount detection circuit and when the control signal is received, the position of the local oscillation unit is longer for a longer time than when the control signal is not received. The synchronization loop to the operating state, the receiver is obtained, characterized in that it comprises an operation control unit to ensure the local oscillation frequency.

In the receiver of the present invention, the local oscillating means is configured as a phase locked loop including a voltage controlled oscillator, a loop filter and a PLL circuit, and the P
The LL circuit outputs an error signal to the loop filter as a reference oscillator, a variable frequency divider for the output of the voltage controlled oscillator, and a difference between the frequency division output of the reference oscillator and the output of the variable frequency divider. And a configuration including a phase comparator.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the embodiment shown in FIG. 1, the input FSK
A quadrature detection demodulation unit 100 is provided which performs quadrature detection reception on the line frequency of the modulated wave and demodulates it to obtain a data signal. The illustrated quadrature detection demodulation unit 100 includes a high frequency amplifier 101 including an antenna, mixer circuits 102 and 102b, L.
PFs 103a and 103b, limiter circuits 104a and 10
4b, demodulation circuit 105, LPF 106, comparator circuit 107, and 90-degree phase shifter 108. Further, a frequency detecting circuit 110 and a frequency detecting circuit 110 which are PLL local oscillating means for providing a local oscillating frequency that is equal to the line frequency necessary for the quadrature detecting / demodulating section 100 and is in phase synchronization by the PLL operation.
The reception control circuit 11 constituting the PLL intermittent operation means for intermittently controlling the operation of the PLL local oscillation means based on the output of
3 and 3 are provided.

Here, the PLL local oscillating means is a voltage controlled oscillator (VCO) 111, a loop filter 112, and P.
It has an LL circuit 109.

Next, the operation of this embodiment will be described.
First, the detection operation of the quadrature detection reception system will be described.

FSK frequency-modulated with baseband signal by binary digital signal of mark or space
The received wave as a modulated wave is amplified by the high frequency amplifier 101 and input to the mixer circuits 102a and 102b, respectively.

As for the local oscillation frequency, the output of the VCO 111 is input to the 90-degree phase shifter 108, and the phase is +45.
And the mixer circuits 102a and 102a are rotated by -45 degrees.
Input to b. With such a circuit configuration, the local oscillation frequencies are supplied to the two mixer circuits 102a and 102b with a phase difference of 90 degrees from each other, and the input signal is frequency-converted into a baseband signal and output.

Since the line frequency and the local oscillation frequency substantially coincide with each other, the baseband signal becomes a beat frequency. The LPFs 103a and 103b extract only the baseband signal and limit the noise band.

The baseband signals are input to limiter circuits 104a and 104b, respectively, and binarized signals I and Q are obtained.

The signal waveform is as shown in FIG. 2, for example. Here, the data represents a modulated signal. Two
It is shown that the frequency detection as shown in FIG. 2 is performed by inputting the binarized signals I and Q to the demodulation circuit 105.

The demodulation circuit 105 shown in FIG. 1 can be configured by a D flip-flop as shown in FIG.

When the clock input CL of the D flip-flop of FIG. 3 is the binarized signal I and the data input D is the binarized signal Q, the output when the data is extracted at the rising edge of the clock is the output L of FIG. And binarized signals I and Q
It can be seen that the output L is also changed and the data is demodulated when the phase of is changed by 90 degrees. In the above description, the case where the binarized signal Q is demodulated has been described.
Data input D and clock input CL for the binarized signal I
Therefore, the binarized signal I can be demodulated by the illustrated D flip-flop.

The demodulated signal thus demodulated passes through the LPF 106 for removing noise, is binarized by the comparator 107, and is output as a binary digital signal.

Next, the operation of the PLL circuit 109 will be described with reference to FIGS.

In FIG. 4, reference numeral 20 is a variable frequency divider, 2
1 is a reference oscillator, 22 is a phase comparator, 23 is a reference frequency divider, 24 is a PLL control circuit, and 25 is a frequency designation ROM.
(Read Only Memory).

The phase comparator 22 compares the phase difference between the output signal of the variable frequency divider 20 which divides the oscillation frequency of the VCO 111 and the output signal of the reference frequency divider 23 which divides the oscillation frequency of the reference oscillator 21. Then, the error voltage is obtained by passing the error signal PD through the loop filter 112 (FIG. 1).

The VCO 111 shown in FIG. 1 controls the oscillation frequency by using this error voltage as a control voltage, and is fed back to the PLL circuit 109 so that the error signal is always constant.

Further, the variable frequency divider 20 can change its frequency division ratio by the frequency designating signal D provided from the PLL control circuit 24. This frequency designating signal D
The oscillation frequency of the VCO 11 corresponding to is obtained.

The PLL control circuit 24 is a frequency designation ROM.
The frequency designation signal S is read from 25.

Now, the oscillation frequency of the reference oscillator 21 is set to 10
If the frequency is set to kHz and the number of bits of the frequency designation signal S is 14 bits, the maximum set frequency is (2 ¹⁵ −1) × 10 kHz = 327.67 MHz.

A PLL on / off signal (hereinafter referred to as PLLBS) given from the reception control circuit 113 turns on / off the PLL operation, and the phase comparator 2 in the off state.
The output state of 2 is set to a high impedance state. Similarly, a VCO on / off signal (VCOBS) given from the reception control circuit 113 turns on / off the operation of the VCO 111. The reception on / off signal (RFBS) is given to the power supply circuit of the quadrature detection reception circuit, and the reception operation is turned on / off by turning on / off this power supply circuit.

Next, the frequency detection circuit 110 will be described with reference to FIG.
Will be described.

The basic operation of this circuit is the limiter circuit 104.
The binarized signal I output by a or the limiter circuit 104
By detecting the frequency of the output signal Q of b, the offset frequency of the deviation of the local oscillation frequency from the line frequency is detected, and only when this offset frequency becomes a certain value or more, the PLL circuit 109 which has stopped operating is activated. Therefore, the oscillation frequency of the PLL local oscillation circuit is tracked and synchronized with the line frequency.

FIG. 6 shows waveforms at various parts of the frequency detection circuit 110. A description will be given based on this.

The binarized signal Q is the output of the limiter circuit 104b and has an offset frequency Δ which is a deviation from the line frequency.
F shall be included. That is, the frequency of the binarized signal Q in the mark or space is ± FD-ΔF.

The demodulation circuit 10 used in the frequency detection circuit 110 of FIG. 5 has a delay circuit 61 having a delay time T as shown in FIG. 7 and an exclusive OR (EX-OR) gate 62.
Is a differential detection circuit composed of

Demodulation circuit 1 in frequency detection circuit 110
The output of 0 becomes a pulse wave having a pulse width T shown by D in FIG. The output D of the demodulation circuit 10 is shown in FIG.
, The LPF11 voltage output O proportional to the frequency of the binarized signal Q input as shown in FIG.
Can be obtained. The average value of the LPF11 voltage output becomes the voltage output of the FD that is independent of the offset frequency ΔF. This means that the frequencies of the binarized signal Q are FD-ΔF and | -F.
Since it is D-ΔF |, the frequency average value is FD.

To obtain the average value A of the LPF11 voltage output O, the LPF11 voltage output O is supplied to the average value circuit 12, as shown in FIG. The time constant of this circuit is set in consideration of conditions such as the reception bandwidth. The configuration in this embodiment is a primary RC integrating circuit including a resistor 63 and a capacitor 64 as shown in FIG.

The average value A is input to the offset circuit 13 as shown in FIG.
An offset voltage of ΔV is added.

As shown in FIG. 10, the offset circuit 13 is composed of a voltage follower 65 that receives the average value A, resistors 62 and 63, and constant current circuits 66 and 67, and outputs output voltages VH and VL. In this case, the output voltages VH and VL are represented by VH = A + ΔV and VL = A−ΔV.

Specifically, the average value A is the voltage
Through the follower 65, the resistors 68 and 69 and the constant current circuit 66,
The offset voltage ± ΔV is generated by 67.

In the frequency detection circuit 110, the output voltages VH and VL of the offset circuit 13 are given to the two comparator circuits 14 and 15. Comparator 14, 1
5 is a transistor 77, 78, as shown in FIG.
A differential amplifier including resistors 75 and 76 and a constant current circuit 79, and a level shift circuit including a transistor 80 and a resistor 81. As shown in FIG. 11, the comparator circuits 14 and 15 have VH and LDF1 respectively.
The first voltage output O, VL and the LPF 11 voltage output O are input and VOH, VOL are output. In this embodiment, VOH is at a high level when O <VH, and VOL is O.
It is set to be high level when> VL.

VOL and VOH are NA as shown in FIG.
The control signal F input to the ND gate 16 and output from the NAND gate 16 only when both VOL and VOH are high.
L goes low. This indicates that the control signal FL becomes low when the deviation of the LPF 11 voltage output O is within ΔV from the average value A.

The above is shown by raising specific numerical values.

Assuming that the demodulation sensitivity in the demodulation circuit 10 in FIGS. 5 and 7 is KD (V / kHz), the LPF 11 voltage output O is O = KD · Δf, and when ΔV> KD · Δf, the control signal FL is low. Becomes

KD = 10 mV / kHz, ΔV = 10 mV
Then, the FL signal becomes high when Δf> 1 kHz.

Next, the operation of the reception control circuit 113 will be described with reference to FIG.
This will be described with reference to the timing chart of No. 2.

Generally, the phase lock pull-in time of the PLL circuit is shorter as the frequency error of the VCO in the free running state is smaller.

In the case of a synchronization system as shown in FIG. 12,
It is assumed that the desired data belongs to three groups indicated by circles among groups 1, 2, and 3.

At the conventional timing, as shown by the broken line, the phase synchronization pull-in time of the PLL circuit is taken into consideration as shown by the broken line.
The L on / off signal (PLLBS) and the VCO on / off signal (VCOBS) are set to T2 depending on the data fetch timing.
It started up a few seconds earlier, and it was down at the end of the group.

In the present embodiment, when the synchronization is established, the frequency error of the VCO is small and the phase synchronization pull-in time is short, so that the PLL on / off signal is compressed at the timing of T1 seconds which is compressed from T2. (PLLBS) and VCO on / off signal (VCOBS) rise.

Next, at the data fetch timing, the PLL
Turn on / off signal (PLLLBS) off to turn on VCO11
Free run 1. At this time, since the output of the phase comparator 22 of the PLL circuit 109 is in a high impedance state, V
The control voltage for CO111 is retained. This intermittent control significantly reduces the operating current during reception.

Next, VCO1 is affected by leakage current, disturbance, etc.
A case will be described where the control voltage for 11 decreases and the VCO frequency changes.

When the VCO frequency changes during reception, for example, as shown in FIG. 12, when the VCO frequency decreases and the offset frequency Δf exceeds the set value of the threshold value indicating the deviation of the phase synchronization, the frequency detection circuit 110 operates. The output control signal FL is turned on (high level).

When the control signal FL is turned on, the reception control circuit 113 turns on / off the PLL at the timing of the next group 3.
Off signal (PLLBS), VCO on / off signal (VC
The start timing of OBS) is set to T0 and is set longer than T1 to ensure that the phase synchronization of the PLL circuit is pulled in.

In this way, in the phase synchronization holding state, the PLL operation is stopped and the VCO 11 is free run to secure the local oscillation frequency, and the PLL operation is performed when the phase synchronization deviates from the correct state. Intermittent PLL operation that secures a local oscillation frequency is performed.

FIG. 13 shows the configuration of the reception control circuit 113 which performs the above-mentioned operation. The reception control circuit 113
Receiving the received data from the comparator 107 (FIG. 1),
A synchronization circuit 113a for performing a synchronization operation such as bit synchronization,
An intermittent operation circuit 113b, and an intermittent operation circuit 113b.
Generates RFSB, VCOBS, and PLLBS shown in FIG. 12 from the timing signal from the synchronization circuit 113a and the control signal FL from the frequency detection circuit 110.
The intermittent operation circuit 113b can be easily configured by combining a timer and a logic circuit.

In the embodiment, the demodulation section describes only the quadrature detection reception system, but the present invention is also applicable to a system which does not perform quadrature detection. The demodulated modulated wave is not limited to the FSK modulated wave, but may be the PSK modulated wave or the like.

[0063]

As described above, according to the present invention, the operation of the PLL local oscillation circuit for performing the quadrature detection demodulation on the input of the FSK modulated wave and generating the local oscillation frequency necessary for the quadrature detection demodulation is phase-locked. If it is secured, the PLL operation is stopped, and it is activated only when the phase synchronization is lost.
By performing the intermittent operation to supply the output of O, the PLL
This has the effect of enabling quadrature detection demodulation with significantly reduced power consumption required for operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the demodulation circuit 105 in FIG.

3 is a block diagram showing a configuration of a demodulation circuit 105 in FIG.

4 is a block diagram showing a configuration of a PLL circuit 109 of FIG.

5 is a block diagram showing a configuration of a frequency detection circuit 110 of FIG.

FIG. 6 is a waveform diagram for explaining the operation of the frequency detection circuit 110 of FIG.

7 is a block diagram showing a configuration of a demodulation circuit 10 of FIG.

8 is a circuit diagram of the LPF 11 of FIG.

9 is a circuit diagram of an average value circuit 12 of FIG.

10 is a circuit diagram of the offset circuit 13 of FIG.

11 is a circuit diagram of comparator circuits 14 and 15 of FIG.

12 is a timing chart for explaining the operation of the reception control circuit 113 in FIG.

13 is a block diagram showing a configuration of a reception control circuit 113 which performs the operation of FIG.

[Explanation of symbols]

 10 Demodulation circuit 11 LPF 12 Average value circuit 13 Offset circuit 14, 15 Comparator circuit 16 NAND gate 20 Variable frequency divider 21 Reference oscillator 22 Phase comparator 23 Reference frequency divider 24 PLL control circuit 25 Frequency designation ROM 100 Quadrature detection demodulation section 101 high frequency amplifier 102a, 102b mixer circuit 103a, 103b LPF 104a, 104b limiter circuit 105 demodulation circuit 106 LPF 107 comparator circuit 108 90 degree phase shifter 109 PLL circuit 110 frequency detection circuit 111 VCO 112 loop filter 113 reception control circuit

Claims (6)

[Claims] 1. A line frequency is set, and the line frequency is set to 2
In a receiver including a demodulation unit for receiving a modulated wave modulated by a baseband signal of a digital signal of a value and obtaining a reproduced digital signal from the modulated wave, from the line frequency of the baseband signal Of the offset amount, when the offset amount is not within a predetermined range, an offset amount detection circuit that outputs a predetermined control signal, and a phase locked loop for the modulated wave is secured,
The controllable local oscillator that transmits a signal having a local oscillation frequency to the demodulator is provided between the local oscillator and the offset amount detection circuit, and when the control signal is received, the control is performed. A receiver comprising: an operation control unit that keeps the local oscillation frequency by operating the phase-locked loop of the local oscillation unit for a long time, as compared with the case where no signal is received. 2. The phase-locked loop of the local oscillator means according to claim 1, wherein the phase-locked loop includes a voltage-controlled oscillator, a loop filter, and a PLL circuit, and the operation control means includes the PLL circuit as the voltage-controlled oscillator. A receiver characterized in that the operating state of the PLL circuit and the voltage-controlled oscillator becomes longer when receiving the control signal, as compared with the operating state of the PLL circuit. 3. The PLL circuit according to claim 2, wherein:
Prior to receiving the desired baseband signal, it is activated and
On the other hand, the receiver is characterized in that the voltage controlled oscillator is in an operating state during reception of the desired baseband signal and maintains the local oscillation frequency. 4. An FSK receiver for receiving a line frequency of an FSK modulated wave which is frequency-modulated by a baseband signal of a binary digital signal, wherein a phase locked loop for the FSK modulated wave is secured and the line frequency is substantially the same. PLL local oscillation means for outputting the same local oscillation frequency,
The local oscillation frequency has a phase difference of 90 degrees from each other.
Quadrature detection demodulation means for converting into two signals and demodulating and extracting the baseband signal of the FSK modulated wave by mixing these two signals with the FSK modulated wave; and the line frequency based on the demodulated and extracted baseband signal. And a frequency difference between the local oscillation frequency and a frequency detection means for outputting a predetermined control signal when the frequency difference exceeds a set value and indicates a deviation of phase synchronization by the phase locked loop, and the control signal. The local oscillation frequency is held in a state in which the phase locked loop operation of the PLL local oscillation means is activated, and when the input of the control signal is absent, it indicates that the phase locked loop ensures the phase locked state. PLL intermittent operation means for holding the local oscillation frequency while the loop operation is stopped FSK receiver and features. 5. The PLL local oscillation means according to claim 4, wherein the voltage controlled oscillator, the loop filter, and the PLL.
And a variable divider for the output of the voltage controlled oscillator, a divided output of the reference oscillator and an output of the variable divider. An FSK receiver including a phase comparator that outputs an error signal of a difference between the phase difference and the phase difference to the loop filter. 6. The frequency detection means according to claim 4, wherein the frequency detection means superimposes an offset voltage corresponding to an allowable value of deviation from the line frequency on an average value voltage of the frequency detection signal of the baseband signal, An FSK receiver characterized in that the presence or absence of output of the control signal is determined based on a result of comparison with a signal.