JPS63316521A - Frequency error detecting circuit - Google Patents

Abstract

PURPOSE:To obtain a frequency error with good accuracy even when a convergence period is long by dividing the product of the sum and the number of the times of controls at two burst periods of the convergence period until a phase control action is converged from the leading of a receiving burst signal, with a burst period. CONSTITUTION:A DPLL circuit 11 receives a master clock and a receiving signal, increases/decreases a pulse to a master clock in accordance with the difference between both, executes the control to synchronize a phase and generates its own clock. A convergence period counting part 3 receives a signal from the circuit 11, obtains a convergence period tr1 until a DPLL control is converged from the leading of a first burst and in the same way, a convergence period tr2 of a next period, obtains a number Nd of the times of the control of DPLL, an arithmetic processing part 4 executes the operation of N=NdX[(tr1+tr2)/tb+1], and calculates and outputs a frequency error N at a burst period tb.

Description

[Detailed Description of the Invention] [Summary] It relates to a circuit that detects frequency errors for controlling DPLL in a time division direction control transmission system, and in particular, a frequency error detection circuit that can accurately detect frequency errors of a transmission clock from received data. Regarding the circuit, the purpose is to provide a frequency error detection circuit that can accurately detect frequency errors even when the convergence period of phase control in a DPLL circuit is long. In a DPLL circuit that increases or decreases pulses to generate a clock that is phase-synchronized with a received signal, there is a convergence period counter that counts the period from the beginning of the received burst signal until the phase control of the DPLL circuit converges, and a burnet period tb. The frequency error N is calculated from the first convergence period tsl at the beginning, the second convergence period ts2 at the beginning of the next burst period, and the number of DPLL controls Nd in the second convergence period using the relational expression %) and an arithmetic processing section.

[Industrial application field]

The present invention provides D
The present invention relates to a frequency error detection circuit for controlling a PLL, and particularly to a frequency error detection circuit that can accurately detect a frequency error of a transmission clock from received data.

A communication device using the time-division direction control transmission method (Bin-Bong transmission method) is equipped with a digital phase-locked circuit (DPLL circuit), and during the training period when setting up the line, etc.
Each time a burst is received, the DPLL is brought into a pull-in state to achieve phase synchronization with the signal of the other station, and is allowed to run freely for the remainder of one burst period to generate the own station clock.

Since a phase error corresponding to the frequency error of the master clock occurs during the free-running period, the DPLL circuit is controlled by detecting this frequency error, but it is possible to accurately detect the frequency error in this case. is necessary.

[Conventional technology]

FIG. 4 shows the configuration of a conventional frequency error detection circuit.

The DPLL control unit 1 generates two types of reference clocks, 0-phase and π-phase, having the same frequency and opposite phases from a master clock having a frequency n times that of the received data input signal. O
One of the phase and π-phase reference clocks is always selected and input to the n frequency divider circuit 2, where the frequency is divided by n. This frequency-divided output is fed back to the DPLL control unit 1, and the received signal and the output clock of the n frequency divider circuit 2 are
The phase with 7 is compared. If the phase of the frequency-divided output is delayed, for example, if the reference clock that has been output up to that time is 0 phase, it is switched to the π phase and output as d. On the other hand, if the phase of the divided output is leading, 0
At the same time as changing from phase to π phase, the π phase reference clock pulse is masked once. In this way, the pulses of the master clock are deleted or inserted according to the phase advance or lag between the received signal and the output clock of the n-frequency divider circuit 2, and the phase of the received signal and the frequency-divided output gradually changes. When they approach and match, control of reference clock switching is stopped. Thereafter, the DPLL control unit 1 continues to output the reference clock that was being output at that time, and enters a free running state. The output of the n frequency divider circuit 2 is used as a desired internal clock signal.

Further, the convergence period counting section 3 monitors the direction of phase control in the DPLL control section 1, and determines the end of the phase control when the control direction is reversed. At the same time, the convergence period counting section 3 counts the number of times the reference clock is switched in the DPLL control section 1 from the beginning of the received signal burst to the end of phase control. This counting result indicates the frequency error between the received signal and the internal clock signal, and is used to control the oscillation frequency of the master clock.

As described above, conventionally, frequency error detection in this type of device has been performed for frequency errors during the free running period in one burst cycle.

However, the error value detected in this way does not include frequency fluctuations during the convergence period, and therefore does not accurately represent the frequency error.

[Problem that the invention seeks to solve]

As described above, in the conventional frequency error detection circuit, the detected frequency error output does not accurately represent the frequency error between the received signal and the internal clock, and the accuracy deteriorates significantly especially when the convergence period is long. As a result, the accuracy of the generated clock frequency is low, and there is a problem in that data transmission and reception using the time division direction control transmission method may not be performed smoothly.

An object of the present invention is to provide a frequency error detection circuit that can accurately detect frequency errors even when the convergence period of phase control in a DPLL circuit is long.

[Means for solving problems] FIG. 1 explains the basic configuration of the present invention.

11 is a digital phase synchronization circuit (DPLL circuit)
It has a well-known configuration, and controls the master clock to increase or decrease pulses to synchronize the phase with the received signal according to the frequency error between the master clock and the received signal,
It generates its own clock.

A convergence period counting section 3 counts the period from the beginning of the received burst signal until the phase control of the DPLL circuit 11 converges.

Reference numeral 4 denotes an arithmetic processing unit which calculates the processing from the first convergence period tsI at the beginning of the burst period tb, the second convergence period ts2 at the beginning of the next burst period, and the number of times Nd of DPLL control in the second convergence period. The frequency error N is calculated and output based on the following relational expression %)).

[For production]

When the phase control operation is started from the beginning of the received burst signal and converged in the convergence period tsl, and the phase control operation is started again from the beginning of the next burst period and converged in the convergence period ts2, the second convergence period The frequency error N is calculated by multiplying the DPLL control number Nd by the count k, but by using -((trl + tr2) / l b) + 1 as the count at this time, the convergence period is long. frequency error can be determined with high accuracy even in the case of

〔Example〕

FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, in which the same parts as in FIG. 4 are designated by the same numbers, and 4 is an arithmetic processing section.

In the circuit shown in FIG.
operates in the same manner as explained with reference to FIG. Generates clock output. The convergence period counting section 3 counts the number of times the reference clock changes during the period from the beginning of the received burst signal to the end of the phase control in the DPLL control section 1, and uses the counting result to indicate the frequency error between the received signal and the internal clock signal. Output as error data.

This data is used to control the oscillation frequency of the master clock.

FIG. 3 illustrates the detection of frequency error (N) according to the present invention. When starting up the device during line setup, etc., the DPLL is controlled from the beginning of the burst until the phase control for the received signal of the divided clock converges, and the convergence period calculated by the convergence period counting section 3 is defined as trl. do.

After the phase relationship is stabilized, self-running is performed to the beginning of the next burst, and the DPLL is controlled until the phase side control converges again at the beginning of the next burst, and the convergence period calculated by the convergence period counting section 3 is tr2, and the number of times Nd of DPLL control in the DPLL control section 1 at this time, that is, the number of times the reference clock is switched, is determined. The DPLL control number Nd thus obtained includes an error as described above, and the product obtained by multiplying this by the phase accuracy error coefficient k becomes the accurate frequency error in the everst period. In other words, the frequency error N for one burst period tb is:
It is determined by the following formula.

N=Ndxk =Nax (((tr++tr2)/lb)+1) The arithmetic processing unit 4 performs arithmetic processing according to equation (11) to obtain the frequency error N and output it as error data.

This error data is used to control the oscillation frequency of the master clock.

As shown in Fig. 3, the phase error may be large at the beginning of DPLL control, and in such a case, the initial convergence period trl is long, so the free-running period in one burst period becomes short. This includes a free-running error, and if the DPLL control number Nd obtained in the next convergence period is directly used as the frequency error, there is a risk that the frequency correction will be inaccurate. However, in the present invention, the frequency error N for one burst period is calculated by taking this period into consideration using equation (1).
Therefore, accurate error data can be obtained, and by controlling the oscillation frequency of the master clock using this data, stable transmission and reception can be performed in the time division control transmission system.

〔Effect of the invention〕

As explained above, according to the present invention, the convergence period from the beginning of the received burst signal until the phase control operation converges is determined for two consecutive burst periods, and the sum of both convergence periods and the burst period is calculated during the burst period. Since the frequency error is calculated by multiplying the DPLL control number by the coefficient obtained by dividing by .

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, FIG. 3 is a diagram explaining frequency error detection according to the present invention, and FIG. 4 is a diagram showing the configuration of an embodiment of the invention. FIG. 2 is a diagram showing a conventional frequency error detection circuit. 1-DPLL control section 2.=n frequency dividing section 3-convergence period coefficient section 4-arithmetic processing section 1l-DPLL circuit

Claims (1)

[Claims] A digital phase synchronization circuit (11) (hereinafter abbreviated as DPLL circuit) that generates a clock that is phase-synchronized with the received signal by increasing or decreasing pulses with respect to the master clock according to the frequency error between the master clock and the received signal. ), a convergence period counter (3) that counts the period from the beginning of the received burst signal until the phase control of the DPLL circuit converges; and a first convergence period (tb) at the beginning of the burst period (tb).
ts_1), a second convergence period (ts_2) at the beginning of the next burst period, and D in the second convergence period.
From the PLL control number (Nd), the relational expression N=Nd×[{(tr_1+tr_2)/tb}+1]
Arithmetic processing unit (4) that calculates the frequency error (N) by
A frequency error detection circuit comprising: