JPH06236412A - Electric circuit information providing method - Google Patents

Abstract

PURPOSE:To provide electric circuit information useful for design work and to improve efficiency in the design work thereby when a hierarchically designed electric circuit is designed. CONSTITUTION:The hierarchically designed electric circuit is set as a target. A user such as a designer, etc., selects the wiring part of the electric circuit with desired hierarchy first. The kind of wiring part selection is decided in steps 110, 120, etc. After that, tracing from a selected wiring part to an input side is performed sequentially as executing processing, for example, in steps 120, 122, 124 repeatedly, and also, a tracing result is displayed to the user. The connection relation of wiring can be recognized even for different hierarchies with the comparatively small steps of operating procedures.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises, for example, a graphic display device for displaying an electric circuit diagram, and confirms the display of at least a part of an electric circuit being designed, while considering, for example, a predetermined hierarchical design. CAD for circuit design (computer
The present invention relates to an electric circuit information presenting method capable of presenting logic circuit information useful for design work at the time of designing using an aided design) device, thereby improving design work efficiency.

[0002]

2. Description of the Related Art Conventionally, analog circuits such as communication devices, digital circuits such as computer devices and peripheral equipment thereof, and high-power circuits such as power transmission and distribution have been extremely complicated. For example, some digital circuits (logic circuits) incorporated in semiconductor integrated circuits are more complicated. Further, in recent years, as the degree of integration of semiconductor integrated circuits has become higher and higher, the work of designing semiconductor integrated circuits has also increased, and the content of design work of semiconductor integrated circuits for realizing the required specifications has become complicated. There is.

Various methods have been conventionally proposed as a method for designing an electric circuit such as a logic circuit incorporated in a semiconductor integrated circuit. For example, there is a top-down method in which detailed configurations and logic circuits are sequentially designed based on predetermined functions, performances, and logics. Further, there is a so-called bottom-up method of gradually designing into a large-scale configuration while combining already proven logic blocks. Further, in these top-down method and bottom-up method, there is a so-called hierarchical design method in which each step in sequentially designing a detailed configuration and a logic circuit is made clearer.

On the other hand, LSI (large scale integrated c
There are remarkable advances in various digital technologies such as design technology and manufacturing technology. For example, in recent years, a very high performance CPU (central processing u
nit) is one chip. Further, there is a remarkable increase in the storage capacity of the semiconductor memory device, and digital technology is rapidly advancing in various aspects. Also, for example, software technology related to man-machine interface,
Various software technologies are also advancing rapidly.

Due to such advances in digital technology and software technology, for example, EWS (engineering workstat)
CAD device using a computer device such as
It has been widely used in various design fields such as electric circuit design. In a CAD device for electric circuit design, for example, a CAD device used for designing a logic circuit to be incorporated in a semiconductor integrated circuit, the concept of hierarchical design as described above is the basis. For example, in a CAD device for electric circuit design, consideration is given to defining a block by a set of adjacent circuit elements and sequentially designing using block symbols corresponding to the block.

Japanese Unexamined Patent Publication No. 1-261782 discloses a technique relating to an interface method of hierarchical design information when a circuit design is divided into mounting level units such as an LSI, a board, and a mother board, and each mounting level is hierarchically designed. . In Japanese Patent Laid-Open No. 1-261782, the mounting level such as an LSI, a board, and a mother board is called a module. When the information necessary for circuit design for each module is stored in a design file and designed, the mounting level is set to Small related modules are defined as lower modules, and larger modules are defined as upper modules. In addition, for a signal name given to an input / output pin serving as a boundary between the upper and lower modules, the lower module traces the signal and defines the attribute of the signal. When designing the upper module, the attribute added to the signal name given to the input / output pin of the lower module is extracted using the signal name as a key. Further, it is possible to interface with a lower module. The above-mentioned Japanese Patent Laid-Open No. 1-2617
According to No. 82, it is possible to take an interface between upper and lower modules by a method in which the change work does not occur as much as possible even during the circuit design, and without designating all the internal information of the lower module at the time of designing the upper module. is there.

In Japanese Patent Laid-Open No. 2-128275, a hierarchical circuit diagram representation is input, and for macroblocks having a hierarchy in the circuit diagram, the function of expanding and displaying the internal circuit of the macroblock, and the hierarchy up and down. There is disclosed a technique relating to a circuit diagram display device having a function of automatically adjusting the scale of. This technique solves the problem that it is inconvenient to see the matching of terminals between the upper and lower layers of a hierarchically designed circuit because separate drawings are provided above and below the layer.

Further, Japanese Laid-Open Patent Publication No. 3-52073 discloses a technique relating to a circuit diagram generation method for generating a circuit diagram in which the hierarchy is expanded when a circuit diagram described hierarchically is given. . In JP-A-3-52073, first,
It has an input means for inputting a circuit diagram described hierarchically. Further, there is a duplicating means for duplicating the circuit diagrams other than the uppermost one of the hierarchically described circuit diagrams input by the inputting device by the number of used circuits. Also, the signal names of the interfaces are made to match between the upper and lower layers of the hierarchically described circuit diagram input by the input unit and the circuit diagram duplicated by the duplicating unit, and the duplicated circuit diagram is obtained. A name conversion unit that makes the signal name and the symbol name of the item unique is provided. Further, interface symbol conversion means for changing the connection between the upper and lower layers of the circuit diagram generated as a result of the name conversion means by the name conversion means to a jump tab is provided.
Further, the circuit diagram re-editing means for re-editing the circuit diagram generated as the conversion result by the interface symbol converting means is provided. The circuit diagram re-editing means is provided with an output means for outputting a circuit diagram in a form in which the hierarchy generated as a result of the re-editing is expanded. As described above,
According to No. 73, by modifying a part of the hierarchically described circuit diagram, a circuit diagram in which the hierarchy is expanded is generated, and the image is almost the same as the original hierarchically described circuit diagram. It is possible to obtain a circuit diagram in a form in which the hierarchy of is expanded.

Further, Japanese Patent Laid-Open No. 4-77873 discloses a technique relating to a method for creating a global net of hierarchical function blocks by expanding hierarchical function blocks to create a global net. In Japanese Patent Laid-Open No. 4-78773, first, for each functional block of each layer except the lowest layer, when the functional block is a parent and the functional block one layer below the functional block is a child, A first step of creating a pre-deployment table by registering the parent and child functional block names, the pin names of the parent and child functional blocks, and the local name of the net connecting the pins is provided. Further, the method further comprises a second step of referring to the pre-expansion table and creating a hierarchy table indicating a parent-child relationship of the functional blocks of all hierarchies. By referring to the pre-expansion table and the functional blocks, the global net name of the parent layer is given to the net of the child layer connected to the net of the parent layer in order from the upper layer to the lower layer. A third step of creating a global net table by assigning a new global net name to a net that is closed only in the child hierarchy without being connected to the net of the hierarchy is provided. According to the above-mentioned Japanese Patent Laid-Open No. 4-77873, it is possible to provide a method for creating a global net of hierarchical functional blocks, which can improve the memory use efficiency and create a global net at a higher speed.

Japanese Unexamined Patent Publication No. 4-113471 discloses a technique relating to a circuit element connection search system having a circuit element connection search mechanism for detecting a connection between the layers of a hierarchically designed logic circuit diagram and displaying it on an output device. ing. For example, the circuit element connection search mechanism is emphasized by changing the color of the connection search unit that automatically searches for the connection between the layers of the logic circuit and the terminal and signal line of the internal circuit of the connected layer. And a circuit diagram display unit for displaying on the output device. This technology increases the number of steps when analyzing a circuit diagram that traces the connections between circuit layers,
It also solves the problem that the connection cannot be traced manually.

[0011]

However, including the conventional hierarchical design method as described above, when designing an electric circuit which has been conventionally hierarchically designed, the wiring connection relation between different hierarchies is traced. Was difficult.

For example, in a design work using a CAD device that is equipped with a graphic display device for displaying an electric circuit diagram and performs a hierarchical design while confirming the display of at least a part of the electric circuit being designed, the electric power of a certain hierarchy is At the time of designing a circuit, it was difficult to trace the connection relation to the upper layer of the layer. Further, it is difficult to trace the wiring connection relationship with a layer higher than a certain layer under design by a plurality of layers.

Therefore, for example, in a logic simulation of a hierarchically designed logic circuit, when a problem such as a timing error occurs in a specific wiring (specific net) of an intermediate hierarchy (intermediate block), another wiring is changed from this wiring. It was difficult to investigate the cause of such a problem by tracing the hierarchy. Further, for example, it is difficult to check the connection relationship from such wiring to the input / output terminals of the entire logic circuit under design.

Conventionally, for example, in a CAD device for electric circuit design in consideration of hierarchical design, when tracing the connection relation of wiring between different layers, the wiring is displayed from the display of the electric circuit of the layer being displayed at that time. It was necessary to perform a complicated operation of switching the display to the display of the electric circuit in a different hierarchy to which the trace destination of the connection relation of 1 is displayed. Alternatively, even in a CAD device using a multi-window system, the operation of displaying an electric circuit in a trace destination hierarchy of a wiring connection relationship is still complicated.

C using a multi-window system
When tracing the wiring connection in the AD device,
Even if the electric circuits of different layers are displayed in the respective windows, it is difficult to find the connection relationship because the electric circuits are displayed independently. In particular, when a large amount of wiring is formed in the displayed electric circuit, it is extremely difficult to find out which wiring has a connection relationship between electric circuits of different layers displayed in different windows. .

At this time, it may be possible to change the display color of the wiring to be traced. However, such an operation of changing the display color requires a plurality of key inputs and the like, which is complicated and reduces work efficiency.

The above-mentioned Japanese Patent Laid-Open No. 4-113471 discloses a circuit element connection search mechanism for detecting a connection between the layers of a hierarchically designed logic circuit diagram and displaying it on an output device. However, this changes the display color of the wiring to be traced as described above. Therefore, it does not present sufficient information in the work of hierarchical design, and it is not possible to go up a plurality of cells and investigate the signal propagation.

The present invention has been made to solve the above-mentioned conventional problems, and when designing a hierarchically designed electrical circuit, it is possible to present electrical circuit information useful for design work. It is an object of the present invention to provide an electric circuit information presentation method capable of improving the design work efficiency.

[0019]

According to the present invention, a wiring location of an already-designed electric circuit portion of a currently-designed electric circuit which has already been specified is selected in advance, and an input side or an output side is selected from the selected wiring location. To one of the, sequentially performs a net trace process to trace the pins of the terminals and cells connected to the net of interest, also from the selected location to either the input side or the output side, By sequentially performing the in-cell trace process of tracing the pin of the cell of interest and repeating the net trace process and the in-cell trace process, by presenting the trace result of the net trace process obtained during this, the problem Has been achieved.

Further, in the electric circuit information presentation method, the trace result narrowing condition is set in advance,
At the time of the presentation of the trace result of the net trace processing, by presenting the presentation contents that are narrowed down by the trace result narrowing-down condition, the problem is achieved and the electric circuit information to be presented is displayed. It has improved usability.

Further, in the electric circuit information presenting method, an electric circuit portion display area for displaying the electric circuit portion currently under design on the display screen used for displaying the electric circuit to the user, and the electric circuit portion display. An electric circuit information presenting area that is adjacent to or surrounding the area is set, and while the electric circuit portion currently being designed is displayed in the electric circuit portion display area, while the electric circuit information presenting area is displayed,
At least the terminal name of the currently-designed partial external terminal in the currently-designed electrical circuit outside the currently-designed electrical circuit portion is displayed, and among the nets in the currently-designed electrical circuit portion,
The external connection wiring connected to the outside of the electric circuit portion in the current design is selected as the selected wiring portion to be the net trace processing or the intra-cell trace processing target,
While repeating the net trace process and the in-cell trace process, based on the trace result of the net trace process obtained during this, the external connection wiring,
By presenting the connection relationship with the currently-designed partial external terminal to the electrical circuit information presentation area, the above problem is achieved and the usefulness of the electrical circuit information presented is further improved. .

[0022]

The present invention has been made by analyzing the contents of work in designing a hierarchically designed electric circuit in order to improve the efficiency of design work using a predetermined CAD device for electric circuit design, for example. It is a thing. Such a hierarchical design has various features due to its detailed configuration and the property of more clearly separating electric circuits (logical circuits), but also has some problems. This is as described above.

Further, as a result of studying to solve such problems, CAD for electric circuit design in consideration of hierarchical design.
In the device, by presenting electrical circuit information useful for design work to the designer with relatively few operations,
We focus on improving the design work efficiency. In particular,
In the present invention, the trace result of the wiring connection relation between different layers is presented to the designer.

As a result, wiring connection relations between different layers can be compared with a smaller number of operation steps compared to the conventional operation of changing the display contents related to the trace of an electric circuit over a large number of layers and tracing the wiring visually. It is possible to grasp the information easily and thereby improve the design work efficiency.

In the present invention, the present invention is not limited to the presentation form of the electric circuit information for improving the design work efficiency. That is, it suffices if it can be presented in a form that the designer can recognize during the design work. For example, in a CAD device for electric circuit design using a multi-window system, the electric circuit information obtained is presented in a window different from the electric circuit display of a predetermined hierarchy which is already displayed in a certain window. It may be one that does. Alternatively, the obtained electric circuit information may be additionally displayed in addition to the display of the electric circuit of a certain layer which is already being displayed. Alternatively, the documents may be arranged in a predetermined order and collectively printed out in a report form. Further, when presenting such electric circuit information, the presented contents may be narrowed down by a preset trace result narrowing-down condition or the like.

In the present invention, there is no particular limitation on the selection of the wiring location of the object to be traced in order to obtain the object to be presented to the user as electric circuit information. For example, the designer may select and input the wiring portion to be traced, as in the first embodiment described later. In FIG. 12, which will be described later, of the first embodiment, the designer selects the output pin of the cell S6 as the wiring point in order to trace the desired wiring point in order to obtain the electric circuit information presentation. or,
The selection of such wiring location may be as in the second embodiment described later. In the second embodiment, among the nets in the currently designed electric circuit portion displayed on the CRT display screen, the external connection wiring connected to the outside of the currently designed electric circuit is wired as described above. The wiring location is selected automatically.

[0027]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 and FIG. 2 are CAD for electric circuit design of the first embodiment to which the electric circuit information presenting method of the present invention is applied.
It is a flowchart which shows the input signal name display process of an apparatus.

In the flow charts of FIGS. 1 and 2, particularly, with respect to an electric circuit of a certain hierarchy displayed on the CRT, input pins and output pins of cells such as logic gates, and the entire electric circuit being designed are described. CA for electric circuit design of the present embodiment, such as input terminals and output terminals, wiring (net) connecting these input pins, output pins, input terminals, output terminals, etc.
The input signal name display process in the said CAD device for electric circuit designs performed based on the wiring location selection of a D user is shown. That is, in these FIG. 1 and FIG. 2, the processing content of tracing from the selected wiring location to the input side based on the wiring location selection as described above and presenting the trace result obtained as a result is shown. ing.

In the flow chart of FIG. 1, first, in steps 110 and 112 of FIG. 1 or step 130 of FIG. 2, the type of wiring location selection made by the designer for the embodiment is determined. That is, whether the operation performed by the designer is the output pin selection of a predetermined cell in the logic circuit diagram or the input pin selection of a predetermined cell, or the wiring (net) in the logic circuit. Is selected.

First, when it is determined in step 110 that the output pin has been selected, in step 116,
Register the output pin name. This is to register the name of the selected output pin in the output pin name file. Then, in step 118, the output pin name registered in step 116 is changed to
Is used to perform in-cell trace processing described later in detail. When the in-cell trace processing is completed, next step 120
Go to.

On the other hand, when it is determined in step 112 that the input pin has been selected, the input pin name is registered in step 114. The input pin name registration is
The name of the input pin selected by the designer is registered in the input pin name file. Step 114
After the processing of (1) is completed, the process proceeds to step 120.

If it is determined in step 130 that the net has been selected, the process proceeds to step 132. In step 132, the input terminals are displayed according to the selected net. The processing of step 132 is to trace the input terminals for the entire logic circuit under design connected to the net selected by the designer, and if there is such an input terminal, display it on the CRT. is there.

Following step 132, step 134
Then, the output pin name is registered according to the selected net. The process of step 134 is to trace the output pins of cells in the logic circuit connected to the net selected by the designer and register the names of such output pins found in the output pin name file. It is a thing. Step 1
After the end of 34, in step 136, the intra-cell trace processing described later in detail with reference to FIG. 3 is performed.

After the end of the in-cell tracing process of step 136, the process proceeds to step 120 of FIG.

Steps 120, 122 and 1 of FIG.
The processing indicated by 24 is repeatedly executed until it is determined in step 122 that there is no output pin registration. By repeating the execution in this way, it is possible to sequentially trace from the wiring location selected by the designer to the input side. Further, during this period, it is possible to obtain electric circuit information useful for grasping the wiring connection relationship between different layers.

First, in step 120, as shown in FIG.
Is used to perform net trace processing described later in detail. The net trace processing is performed on a predetermined net by sequentially tracing input terminals for the entire logic circuit being designed and output pins of cells in the logic circuit being designed, which are connected to the input. The terminal name is displayed and the name of the output pin is registered.

After the step 120 is completed, in the step 122, it is judged whether or not the output pin is registered. This determination in step 122 is to determine whether or not there is a registration in the output pin name file as a result of the processing in step 120. If it is determined that there is no registration in the determination, it is determined that the trace in which the logic circuit under design is sequentially performed on the input side is finished, and the processing shown in the flowchart is finished.

If it is determined in step 122 that the output pin has been registered, then in step 124, an in-cell trace process which will be described later in detail with reference to FIG. 3 is performed. The in-cell trace processing is to trace the input pin of a predetermined cell and register the traced input pin name in the input pin name file.

FIG. 3 is a flow chart showing the above-mentioned intra-cell trace processing performed in the first embodiment.

The in-cell trace processing shown in FIG. 3 is the processing performed in steps 118 and 124 of FIG. 1 and step 136 of FIG. The in-cell trace processing traces the input pin in the corresponding cell based on the output pin name file registered before execution of the in-cell trace processing, and changes the name of the input pin to the input pin name file. It is to register with F.

First, in step 150 of FIG. 3,
When executing the in-cell trace processing, the input pin name file written by the in-cell trace processing is all cleared.

Then, in step 152, the cells to which the respective output pins belong are first read according to the registration made in the output pin name file. Also, for the cell found in this way, find its input pin,
The name is registered in the input pin name file.

After the processing in step 152 is completed, in step 154, the output pin name file used as the input file in the in-cell trace processing is all cleared.

FIG. 4 is a flow chart showing the net trace processing performed in the first embodiment.

The net trace process shown in FIG. 4 is the process performed in step 120 of FIG. The net trace processing is performed according to the input pin name file registered when performing the net trace processing. That is, the input pin names registered in the input pin name file are read one by one, and the wiring, that is, the net connected to this is found. Moreover, the input terminal for the entire logic circuit under design connected to the net is found and displayed.

After step 160, step 162
Then, the registration in the output pin name file is performed according to the registration in the input pin name file that is performed when performing the net trace processing. This reads the input pin names registered in the input pin name file one by one, and first finds a net connected to the input pin. Also, the output pin of another cell connected to the found net is found, and the name of the output pin is registered in the output pin name file.

As described above, according to the input signal name display processing of the first embodiment described above with reference to the flowcharts of FIGS. 1 to 4, the logic circuit under design is input to the input side according to the selection of the wiring location by the designer. The trace result can be obtained by sequentially tracing to. In this embodiment, in particular, the names of the input terminals of the entire logic circuit being set are
The trace result can be presented to the designer. During tracing to the input side shown in FIGS. 1 to 4, the name of the traced cell and the names of the input pin and the output pin of the traced cell are presented to the designer as electric circuit information. You may do it.

FIGS. 5 and 6 are flow charts showing the output signal name display processing performed in the first embodiment.

The output signal name display processing shown in FIG. 5 and FIG. 6 is useful for design work while tracing sequentially from the selected wiring location to the output side according to the wiring location selection made by the designer. The electric circuit information is presented. In this embodiment, in particular, the output terminals of the entire logic circuit under design on the output side from the wiring location are traced and the names thereof are displayed.

In the output signal name display processing, first, in the steps 210 and 212, and in the step 230 of FIG. 6, the wiring location selection made by the designer is the input of the cell in the logic circuit being designed. It is determined whether the pin is selected, the output pin of the cell in the logic circuit under design is selected, or the net in the logic circuit under design is selected.

First, if it is determined in step 210 that the input pin is selected, then in step 216, the name of the input pin selected by the designer is registered in the input pin name file. Then, in step 218, an intra-cell trace process which will be described later in detail using the flowchart of FIG. 7 is performed. The in-cell trace processing finds the cell of the input pin registered in the input pin name file when performing the in-cell trace processing,
The output pin name of the cell is registered. After completion of step 218, the process proceeds to step 220.

If it is determined in step 212 that the output pin is selected, then in step 214, the output pin name is registered. The output pin name registration is to register the name of the output pin selected by the designer in the output pin name file. After completion of step 214, the process proceeds to step 220.

If it is determined in step 230 that the net has been selected, then in step 232, the output terminals are displayed according to the selected net. This is to trace and display the output terminals of the entire logic circuit under design connected to the net selected by the designer.

After the step 232 is completed, in step 234, the input pin name is registered according to the selected net. The input pin name registration is to trace the input pin of the cell connected to the net selected by the designer and register the name of the input pin in the input pin name file.

After step 234, in step 236, an in-cell trace process, which will be described later in detail with reference to the flowchart of FIG. 7, is performed. In the in-cell trace process, the input pin names in the input pin name file registered when performing the in-cell trace process are taken out one by one, and the output pin name of the cell of the input pin is set as the output pin name. It is to register sequentially to a file.
After completion of step 236, the process proceeds to step 220.

Steps 220, 222 and 2 of FIG.
24 is repeatedly executed until it is determined in step 222 that there is no input pin registration. By repeating the execution in this way, the wiring location selected by the designer as described above is sequentially traced to the output side, and electric circuit information useful for the design work is presented during this period. Specifically, for the entire logic circuit under design,
The name of the traced output terminal is displayed to the designer.

First, at step 220, a net trace process which will be described later in detail with reference to the flowchart of FIG. 8 is performed. In performing the net trace processing, the net trace processing sequentially traces the output terminals connected to the output pins in the registered output pin name file and the input pins of other cells, and traces the output terminals of the traced output terminals. The name is displayed.

After the step 220 is completed, it is determined in step 222 whether or not the input pin is registered. The determination of the presence or absence of the input pin registration is to determine whether or not the input pin name file is registered as the execution result of step 220. When it is determined that the input pin is not registered, the series of processes shown in FIGS. 5 and 6 are all ended. On the other hand, if it is determined in step 222 that the input pin is registered, then in step 224, in-cell tracing processing, which will be described later in detail with reference to FIG. 7, is performed. The in-cell trace processing finds the cell of the registered input pin according to the input pin name file registered in advance when performing the in-cell trace processing, and outputs the name of the output pin of the found cell, It is to be registered in the output pin name file.

FIG. 7 is a flow chart showing the in-cell trace processing performed in the first embodiment.

In the flow chart of FIG. 7, the above-mentioned FIG.
218, 224 and step 23 of FIG.
The in-cell trace processing performed at 6 is shown. In the in-cell trace processing, the input pin names in the input pin name file registered when performing the in-cell trace processing are read one by one, the cell of the input pin is found, and the name of the output pin of the cell is read. Is registered in the output pin name file.

In step 250 of FIG. 7, first, the output pin name file which is the output file of the in-cell trace processing is all cleared.

Next, at step 252, input pin names are taken out one by one from the input pin name file registered in advance for performing the in-cell trace processing, the cell of the input pin is found, and the output of the cell is made. Register the pin name in the output pin name file. The process shown in step 252 is performed for all the input pins registered in the input pin name file.

Following step 252, step 25
In 4, the input pin name file used as the input file for the in-cell trace processing is all cleared.

FIG. 8 is a flow chart showing the net trace processing performed in the first embodiment.

The net trace process shown in the flow chart of FIG. 8 is the process performed in step 220 of FIG. In step 260 of FIG. 8, first, according to the output pin name file registered in advance when performing the net trace processing,
Display output terminals. This is to read the output pin names registered in the output pin name file one by one,
The net connected to the output pin is found, the output terminal for the entire logic circuit under design connected to the net is found, and the found output terminal is displayed.

After such step 260, in step 262, the input pin name is registered according to the output pin name registration. This is to read the output pin names one by one in the output pin name file registered in advance when performing the net trace processing, and first find the net connected to the output pin. Further, the input pin of the cell connected to the found net is found, and the name of the found input pin is registered in the input pin name file.

As described above with reference to FIGS. 5 to 8, according to the output signal name display processing performed in the first embodiment, from the wiring location selected by the designer to the wiring location, It is possible to sequentially trace to the output side, find the output terminal for the entire logic circuit under design, and display it. Therefore, by such a display, the designer can immediately recognize which output terminal of the entire logic circuit under design the wiring location selected is related to.

In the output signal name display processing, the output terminal of the wiring location selected as described above is displayed, but other information is traced,
It may be displayed. That is, during the output signal name display processing as shown in FIG. 5 and FIG. 6, the traced cell name, the input pin name of the traced cell, and the output pin name are registered in some file. Alternatively, this may be displayed to the designer.

In the input signal name display processing described above with reference to FIGS. 1 to 4 and the output signal name display processing described above with reference to FIGS. In order to prevent unnecessary increase in the electric circuit information presented to the designer, the display content displayed to the designer is narrowed down by the preset trace result narrowing condition. The trace result narrowing condition is registered in advance in the trace result narrowing condition file by a designer or the like. Also, steps 132 and 134 of FIG. 2, step 152 of FIG. 3, steps 160 and 162 of FIG. 4, steps 232 and 234 of FIG. 6, step 252 of FIG. 7, step 260 of FIG. At 262, the trace result narrowing-down condition is used.

FIG. 9 is a block diagram showing a hardware configuration used in the CAD device for electric circuit design of the first embodiment.

In the first embodiment, in the hardware as shown in FIG. 9, the CAD for electric circuit design as shown in the flow charts in FIGS. 1 to 8 is used.
The device is realized.

As shown in FIG. 9, the hardware of the CAD device for electric circuit design mainly consists of a CPU (ce
ntral processing unit) 50, a main storage device 52,
Hard disk device 54, optical disk device 56, floppy disk device 58, input / output device 60, keyboard 62, CRT control device 64a, and CRT 64b.
And a system bus 70. A digitizer is connected to the input / output device 60.

The CPU 50 executes the program modules and the like according to the present embodiment, which are read from the hard disk device 54 and are stored in the main storage device 52. The hard disk device 54 stores the program module according to the present embodiment, drawing data of an electric circuit diagram such as a user electric circuit, data regarding a block symbol generated or used in hierarchical design, and the like. According to the above, the data is read out to the main storage device 52. The optical disk device 56 is used for backing up program modules and data stored in the hard disk device 54. The floppy disk device 56 is used for transferring various program modules and data to and from other computer systems.

The input / output device 60 includes various peripheral devices,
For example, the digitizer or the like is connected. The digitizer is used by an electric circuit designer to input two-dimensional coordinates. The digitizer is, for example, the CRT6.
It is used for inputting the selection by the electric circuit designer of the wiring location in the user circuit while checking the electric circuit diagram displayed in 4b. The keyboard 62 is used to operate the CAD device for electric circuit design and to set various data. The CRT controller 64a and the CRT 64b controlled by the CRT controller 64a
Is a bitmap display device and can display not only letters such as numbers but also figures such as electric circuit diagrams being designed, graphs and images.

The system bus 70 is connected to the CP
U50, the main storage device 52, the hard disk device 54, the optical disk device 56, the floppy disk device 58, the input / output device 60, the keyboard 62 and the CRT control device 64a when transferring data or the like. Used for. Further, the CAD for designing the electric circuit
In the apparatus, a multi-window system is used, and by opening a plurality of windows (sheets), for example, an electric circuit designer can also perform a plurality of operations in parallel.

The CA for electric circuit design of the first embodiment will be described below.
The operation of the first embodiment will be described by using an example of a logic circuit targeted by the D device.

FIG. 10 is a logic circuit diagram showing the entire logic circuit targeted by the first embodiment.

In FIG. 10, "DATA1" ...
"DATA3", "SEL", "CLK" and "CT"
L "is an input terminal for the entire logic circuit shown in FIG. 10. On the other hand," OUT1 "to" OUT ".
3 "is an output terminal of the entire logic circuit shown in FIG. 10. Incidentally, these" DATA1 "to" DAT ".
A3 "," SEL "," CLK "," CTL "," OU "
T1 "to" OUT3 "are not only input terminal names or output terminal names, but also signal names. The entire logic circuit shown in Fig. 10 includes cells S1 to S3 and a block B1. It is composed by.

The cell S1 is a multiplexer.
In the cell S1, when the signal SEL is in the H state, the signal DATA1 is selected to the input I1 of the block B1. On the other hand, when the signal SEL is in the L state, the cell S1 outputs the signal DATA to the input I1 of the block B1.
Select 3.

The cell S2 is a buffer gate.
The cell S3 is a tri-state buffer gate. The S3 operates as a buffer gate when the output pin O2 of the block B1 is in the H state, and outputs the H state or the L state according to the input. On the other hand, output pin O
When 2 is in the L state, the output of the cell S3 is in the high impedance state. The block B1 has an input pin I
1 to 14 and output pins O1 and O2.

FIG. 11 is a logic circuit diagram of a block in the logic circuit example targeted by the first embodiment.

FIG. 11 shows a logic circuit diagram of the block B1 used in the logic circuit shown in FIG. The block B1 includes cells S4 to S4.
It is composed of 8. The cell S4 is a D-type flip-flop. The cell S5 is a tri-state buffer gate. The cells S6 and S7 are AND gates. The cell S8 is an OR gate.

FIG. 12 is a diagram showing a CRT display when the wiring location is selected in the first embodiment.

FIG. 12 shows the CR in the logic circuit example of the first embodiment shown in FIGS. 10 and 11 when the designer according to the present invention selects the wiring location.
An example of display on T64b is shown. In particular, the cell S
After the designer selects the wiring points of the output pins of 6, the trace of the target logic circuit and the trace obtained by the trace are obtained by the series of processes described above with reference to the flowcharts of FIGS. A display of electrical circuit information is shown.

In particular, as the trace result, "DATA
The trace results of the input signals of "1" and "DATA2" are displayed, and the trace results of the output signals of "OUT1" and "OUT2" are shown.

These trace results are sequentially traced from the output pin of the cell S6 whose wiring location has been selected by the designer to the input side, and the resulting input signal of the input terminal for the entire logic circuit is obtained. It is shown. or,
From the output pin of the cell S6 whose wiring location is selected,
Traces to the output side sequentially, and the trace result of the output signal relating to the output terminal for the entire target logic circuit obtained as a result is displayed.

When performing the trace shown in FIG. 12, the following trace result narrowing-down conditions are set in advance.

(1) Clock signal input pin of the cell S4 (D-type flip-flop) (2) Cell S5 (tri-state buffer gate)
(3) Selector signal input pin of the cell S1 (multiplexer)

Therefore, when the output pin of the cell S6 is selected at the wiring location and the trace of the connection relation related thereto is performed, the trace corresponding to the above trace result narrowing condition is not performed. Therefore, the trace result narrowing is performed. The electric circuit information related to the condition is not presented. This prevents the displayed information from unnecessarily increasing.

As described above, according to the first embodiment, the designer selects the wiring location for the logic circuit of a certain hierarchy displayed on the CRT 64b, so that the selected wiring location is selected. It is possible to trace the connection relationship of the wirings regarding the different layers. The trace result can be displayed on the logic circuit diagram being displayed on the CRT 64b, and the circuit information useful for the design work can be presented. In addition, the selection of the wiring location by the designer at this time is carried out while confirming the display of the logic circuit on the CRT 64b, which is a relatively simple operation with a small number of operations using the aforementioned digitizer. There is. Therefore, according to the first embodiment, the present invention can be applied to improve the design work efficiency of the logic circuit design.

FIG. 13 is a flow chart showing the overall processing of the CAD device for electric circuit design of the second embodiment to which the electric circuit information presenting method of the present invention is applied.

The second embodiment is made by using the hardware shown in FIG. 9 like the first embodiment. Particularly, in the second embodiment, it is possible to display an arbitrary circuit portion in an electric circuit under design (hereinafter, referred to as an electric circuit under design), that is, the electric circuit under present design on the CRT 64b. There is.

Further, regarding such an electric circuit part currently under design, a connection destination of a wiring connected to the outside (hereinafter referred to as an external connection wiring) and a signal propagation relation (hereinafter, these relations are connected to each other). (Referred to as "relationship") and trace them sequentially. In addition, based on the trace result, the connection relationship between the external connection wiring and the terminal in the electric circuit under design outside the electric circuit part under current design (hereinafter, referred to as a partial external terminal under current design) is shown. The information is displayed in a predetermined electric circuit information presentation area on the CRT 64b.

In the second embodiment, as will be described later in detail with reference to FIG. 17, etc., the display screen of the CRT 64b has the electric circuit under design within the range specified in the electric circuit under design. An electric circuit portion display area for displaying a portion and an electric circuit information presentation area adjacent to or surrounding the electric circuit portion display area are set.

First, in step 310 of FIG. 13, the electric circuit displayed on the CRT 64b,
In particular, with respect to the entire electric circuit being designed, the current external terminal under design, that is, all terminals outside the current electrical circuit part of the selected part are About.

In the following step 312, the external connection wiring connected to the outside of the currently designed electric circuit portion is extracted from the nets (wiring) in the currently designed electric circuit portion.

When the terminal currently under design and the external connection wiring are extracted in these steps 310 and 312, in the following steps 314, 316 and 318, the input signal name display processing shown in FIG. The output signal name display processing shown in FIG. 5 is performed. Such processing is performed for all the external connection wirings extracted in step 312.

The input signal name display processing and the output signal name display processing performed in the second embodiment are partially different from those in the first embodiment. That is, in the second embodiment, as in the first embodiment, during the input signal name display processing or the actual signal name display processing, the traced items are not particularly displayed, and these will be described later. In step 324, it is displayed collectively. Therefore, in the second embodiment, the step 13 shown in FIGS.
2 and the above-mentioned FIG.
16 in the net trace processing shown in FIG.
0, the step 232 of displaying the output signal name shown in FIG. 5 and FIG. 6, and the net trace processing step 260 of FIG. However, in order to perform the display in step 324 of FIG. 13, which will be described later, what is to be displayed is stored in the memory.

In step 314, the step 3
When it is determined that all the trace processing has been completed for the external connection wiring absorbed in 12, the process proceeds to step 322.

In step 322, the electric circuit portion currently under design which is currently being designed by the user is displayed in the electric circuit portion display area on the screen of the CRT 64b. Then, in step 324, the terminal name and the terminal name thereof are traced to the electric circuit information presenting area adjacent to or surrounding the electric circuit partial display area according to the trace results made in steps 314, 316 and 318. Display the symbol.

Further, when the terminal name and its symbol are displayed in this way, in the following step 326, such a symbol of the terminal and the corresponding one of the external connection wirings are connected by a predetermined automatic wiring process. To do.

FIG. 14 is a logic circuit diagram showing an overall example of a logic circuit targeted by the second embodiment.

In FIG. 14, "DATA1",
"DATA2", "CLK", "CTRL", "SE"
L "is an input terminal of the entire logic circuit shown in Fig. 14. On the other hand," OUT1 "and" OUT2 "are
It is an output terminal of the entire logic circuit shown in FIG. Note that these are the input terminal names or the output terminal names and the signal names.

The entire logic circuit shown in FIG. 14 is composed of cells S10 to S12 and a block B2. The cell S10 is a multiplexer. The cell 11 is a buffer gate. The cell S12 is a tri-state buffer gate.

FIG. 15 is a logic circuit diagram of a block in the logic circuit example targeted by the first embodiment.

FIG. 15 shows a logic circuit diagram of the above-mentioned block B2 used in the logic circuit shown in FIG. The block B2 includes cells S13 to S18.
It is composed of. The cell S13 is a D-type flip-flop. The cells S14 and S16 are ANDed
It is a logic gate. The cell S15 is a tri-state buffer gate. The cell S17 is an OR logic gate. The cell S18 is a buffer gate.

FIG. 16 is a diagram showing a CRT display when an electric circuit portion of a desired design place is displayed in the second embodiment.

In FIG. 16, among the circuits in the block B2 shown in FIG.
The portion indicated by the alternate long and short dash line 34 is displayed as the electric circuit portion in the current design. Therefore, this FIG.
The cells S13 and S14 shown in FIG. 15 are those in the block B2 shown in FIG.

Further, in FIG. 16, the solid line 20 is
The whole display screen of the CRT 64b is shown. The inside of the one-dot chain line 24 is the circuit portion display area for displaying the electric circuit portion currently under design. In addition, the one-dot chain line 2
The outside of 4 is an electric circuit information presentation area that surrounds such an electric circuit partial display area.

Further, in such an electric circuit information presenting area, the outside of the broken line 28 shows the terminal name of the terminal under the current design and the terminal outside the present design under terminal display area 30 where the symbol is displayed. Is.

In the electric circuit information presentation area, inside the broken line 28, that is, the broken line 28 and the alternate long and short dash line 24.
Between and, the connection relationship between the currently-designed partial external terminal and the external connection wiring of the currently-designed electrical circuit portion displayed in the electrical circuit portion display area is displayed. That is, in the flowchart of FIG.
The connection relationships are shown by the trace results obtained at 14, 316 and 318. Further, such a connection relation is displayed by the automatic wiring made in step 326.

In FIG. 16, the following connection relationships are displayed in particular.

(1) The input D of the cell S13 depends on signals from the input terminals DATA1 and SEL and has a connection relationship.

(2) The input CK of the cell S13 depends on the input terminal CLK and has a connection relation.

(3) One input of the cell S14 depends on the signal of the input terminal DATA2 and has a connection relation.

(4) The output of the cell S14 influences the signal of the output terminal OUT1 and has a connection relation.

As described above, according to the second embodiment, with respect to the currently designed electric circuit portion displayed on the CRT 64b, the currently designed electric circuit portion outside the currently designed electric circuit portion is under design. The connection relationship of the partial external terminals can be traced regardless of the hierarchical relationship of the hierarchy. Further, the trace result can be displayed particularly in the electric circuit information presentation area on the CRT 64b, and the circuit information useful for the design work can be presented. Therefore, the first
According to the embodiment, the present invention can be applied to improve the logic circuit design work efficiency.

The design of the electric circuit partial display area and the circuit information presenting area on the display screen in this embodiment is not shown in FIG. 16 of the second embodiment. For example, the display screens 20a to 20d shown in FIG. 17 may be used.

On the display screen 20a, the electric circuit portion display area is on the right side of the alternate long and short dash line. The left side of the one-dot chain line is the electric circuit information presentation area. In the electric circuit information presentation area, the currently designed partial external terminal is displayed to the left of the broken line, and the connection relationship between the currently designed partial external terminal and the external connection wiring is displayed to the right of the broken line. To be done.

In the display screen 20b, the left side of the alternate long and short dash line is the electric circuit portion display area.
The electric circuit information presentation area is on the right side of the one-dot chain line. Especially in the electric circuit information presentation area,
The partial external terminal currently under design is displayed on the right side of the broken line.
Further, on the left side of the broken line, the connection relationship between the currently-designed partial external terminal and the external connection wiring is displayed.

On the display screen 20c, the electric circuit portion display area is located above the alternate long and short dash line. Below the one-dot chain line is the circuit information presentation area.
In the electric circuit information presentation area, the currently-designed partial external terminal is displayed below the broken line, and the connection relationship between the currently-designed partial external terminal and the external connection wiring is shown above the broken line.

On the display screen 20d, the upper right side of the alternate long and short dash line is the electric circuit portion display area, and the lower left side of the alternate long and short dash line is the electrical circuit information presentation area. In the electric circuit information presentation area, the currently designed partial external terminal is displayed on the lower left side of the broken line, and the connection relationship between the currently designed partial external terminal and the external connection wiring is displayed on the upper right side of the broken line. To be done.

[0124]

As described above, according to the present invention, electric circuit information useful for design work can be presented when designing a hierarchically designed electric circuit, thereby improving the design work. It is possible to obtain an excellent effect of being able to.

[Brief description of drawings]

FIG. 1 is a first flowchart showing an input signal name display process of a first embodiment of a CAD device for electric circuit design to which the present invention is applied.

FIG. 2 is a second flowchart showing the input signal name display processing.

FIG. 3 is a flowchart showing in-cell trace processing performed during the input signal name display processing.

FIG. 4 is a flowchart showing a net trace process performed during the input signal name display process.

FIG. 5 is a first flowchart showing an output signal name display process performed in the first embodiment.

FIG. 6 is a second flowchart showing the output signal name display processing.

FIG. 7 is a flowchart showing an in-cell trace process performed during the output signal name display process.

FIG. 8 is a flowchart showing a net trace process performed during the output signal name display process.

FIG. 9 is a block diagram showing a hardware configuration used in the first embodiment.

FIG. 10 is a logic circuit diagram showing an entire example of a logic circuit targeted by the first embodiment.

FIG. 11 is a logic circuit diagram of a block used in the logic circuit diagram example of the first embodiment.

FIG. 12 is a diagram showing an example of a CRT display when a wiring location is selected in the block of the first embodiment.

FIG. 13 is a flowchart showing the overall processing of a second embodiment of a CAD device for electric circuit design to which the present invention is applied.

FIG. 14 is a logic circuit diagram showing an entire example of a logic circuit targeted by the second embodiment.

FIG. 15 is a logic circuit diagram of a block used in the logic circuit diagram example of the second embodiment.

FIG. 16 is a diagram showing an example of a CRT display when an electric circuit part in the current design in a block used in the logic circuit diagram example of the second embodiment and electric circuit information thereof is presented.

FIG. 17 is a diagram showing a setting example of an electric circuit partial display area and an electric circuit information presentation area on the display screen of the CRT of the second embodiment.

[Explanation of symbols]

20, 20a to 20d ... CRT display screen 22 ... Electrical circuit under design (whole) 24 ... Electrical circuit partial display area 28 ... Current designing partial external terminal connection relation display area 30 ... Current designing partial external terminal display area 32 ... Block 2 Electric circuit 34 ... Zoom expansion range 50 ... CPU 52 ... Main memory device 54 ... Hard disk device 56 ... Optical disk device 58 ... Floppy disk device 60 ... Input / output device 62 ... Keyboard 64a ... CRT control device 64b ... CRT S1-S8 ... Cell B1, B2 ... Blocks DATA1 to DATA3, SEL, CLK, CTL ... Input terminals for the entire logic circuit example OUT1 to OUT3 ... Overall output terminals of the logic circuit example I1 to I4 ... Input pins O1, O2 of the block ... Output pin

Claims (3)

[Claims] 1. A wiring location of an already-designed electric circuit portion of an electric circuit under design, which has already been specified, is selected in advance, and the selected wiring location is sequentially input to either an input side or an output side. , Performs net trace processing that traces the terminals and cell pins connected to the target net, and also traces the pin of the target cell sequentially from the selected location to either the input side or the output side. The electrical circuit information presenting method is characterized in that the tracing result of the net trace processing obtained during this period is presented while repeating the intra-cell tracing processing and repeating the net tracing processing and the intra-cell tracing processing. 2. The trace result narrowing-down condition according to claim 1, wherein when presenting the trace result of the net trace processing, the presented content is narrowed down by the trace result narrowing-down condition. A method for presenting electrical circuit information, characterized by presenting a product. 3. The electric circuit part display area for displaying the electric circuit part currently under design and the electric circuit part display area on the display screen used for displaying the electric circuit to the user. An electric circuit information presenting area that is adjacent to or surrounds the electric circuit information presenting area, and displays the electric circuit portion under current design in the electric circuit portion display area, while the electric circuit information presenting area is displayed in the electric circuit information presenting area. Displaying at least the terminal name of the current external terminal under design in the electrical circuit under design outside the circuit portion, to the outside of the current electrical circuit portion under design of the net in the current electrical circuit portion under design. The external connection wiring connected to
Select as the selected wiring point to be the target of the net trace processing or the intra-cell trace processing, and repeat the net trace processing and the intra-cell trace processing to obtain the trace result of the net trace processing obtained during this period. Based on the external connection wiring,
A method of presenting electrical circuit information, which presents a connection relationship with the currently-designed partial external terminal to the electrical circuit information presentation area.