JPH06232413A - Flash eeprom and manufacture thereof - Google Patents

Flash eeprom and manufacture thereof

Info

Publication number
JPH06232413A
JPH06232413A JP33770593A JP33770593A JPH06232413A JP H06232413 A JPH06232413 A JP H06232413A JP 33770593 A JP33770593 A JP 33770593A JP 33770593 A JP33770593 A JP 33770593A JP H06232413 A JPH06232413 A JP H06232413A
Authority
JP
Japan
Prior art keywords
gate
semiconductor substrate
formed
drain
interlayer insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33770593A
Other languages
Japanese (ja)
Inventor
Hyun Chou Il
ヒュン チョウ イル
Original Assignee
Hyundai Electron Ind Co Ltd
ヒュンダイ エレクトロニクス インダストリーズ カンパニー リミテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to KR920027323 priority Critical
Priority to KR1992-27323 priority
Application filed by Hyundai Electron Ind Co Ltd, ヒュンダイ エレクトロニクス インダストリーズ カンパニー リミテッド filed Critical Hyundai Electron Ind Co Ltd
Publication of JPH06232413A publication Critical patent/JPH06232413A/en
Pending legal-status Critical Current

Links

Abstract

(57) [Summary] [Purpose] Even if over-erasure occurs, it does not affect the operation and allows operation at a low voltage. The auxiliary gate 9 is in contact with an interlayer insulating film, and an auxiliary gate is formed above a predetermined region of the source and drain via a gate oxide film to form a gate electrode having a spacer structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to electronically recording information,
Regarding an erasable non-volatile memory cell, in particular, a flash EPROM (electrically erasable) capable of storing a large amount of information by minimizing the size of the cell
programmable ROM: hereinafter abbreviated as EEPROM) and its manufacturing method.

[0002]

2. Description of the Related Art Generally, an EEPROM is a portable computer, a memory card required for mobile communication or the like, an image card for an electronic still camera, or a hard disk used for a personal computer. Applicable to alternative solid-state disks.

An equivalent circuit diagram and a sectional view of a memory cell of a conventional flash EEPROM are shown in FIGS. 10 and 11, respectively. 10 and 11, 1 is a semiconductor substrate, 2 is a source, 3 is a drain, 4 is a gate oxide film, 5 is a floating gate, 6 is an interlayer oxide film, and 7 is a control gate.

In the flash EEPROM, information is stored in the floating gate 5 by hot carrier injection, and the control gate 7 controls the electrons injected into the floating gate 6 to read out data for programming and erasing.

[0005]

However, in such a conventional flash EEPROM, overerasure may occur at the time of erasing. In order to prevent overerasure,
When erasing, a complex and time-consuming algorithm must be applied. In addition, conventional flash EEPRO
In M, since it is necessary to apply a relatively high voltage between the source and the drain, an unnecessary interference phenomenon occurs between cells at the time of storage or erasing, and the reliability of the element is deteriorated. Furthermore, in the future, it is expected that the required power supply voltage will decrease from 5V to 3V in the system design, but it is almost impossible to operate at 3V with existing flash EEPROM cells, and it is necessary to drive at 3V. We have to be able to respond.

The present invention has been made in view of the conventional problems as described above, and does not affect the operation even if overerasure occurs, and the flash EEPRO can be operated at a low voltage.
It is an object of the present invention to provide M and its manufacturing method.

[0007]

Therefore, according to the present invention, in a flash EEPROM, a semiconductor substrate and impurities of a form different from that of the semiconductor substrate are ion-implanted from the surface to the inside of the semiconductor substrate at high concentration. A source surrounded by a first low-concentration impurity region in which an impurity of the same form as that of the semiconductor substrate is implanted at a low concentration, and the source are formed inside the semiconductor substrate from the surface of the semiconductor substrate with a predetermined interval, The second low-concentration impurity region in which the impurity in the form different from that of the semiconductor substrate is ion-implanted in high concentration and the impurity in the form different from that of the semiconductor substrate is injected in low concentration A gate oxide film formed on an upper portion up to the drain, on the low-concentration impurity region, on a semiconductor substrate between the source and the drain, and a second
A floating gate formed on the low-concentration impurity region via a gate oxide film, a first interlayer insulating film formed on the electrode of the floating gate, and a control gate formed on the first interlayer insulating film. And a second interlayer insulating film 8 that is formed in a direction perpendicular to the surface of the semiconductor substrate 1 so as to cover the sidewalls of the floating gate 5 and the control gate 7, and insulates the floating gate 5 and the control gate 7.
And an auxiliary gate 9 formed in contact with the interlayer insulating film 8 and above the predetermined region of the source 2 and the drain 3 with a gate oxide film 4 interposed therebetween.

In the flash EEPROM,
A semiconductor substrate and a first low-concentration formed by implanting a high-concentration ion of an impurity different in form from the semiconductor substrate into the surface of the semiconductor substrate and injecting a low-concentration impurity of the same form as the semiconductor substrate. A source surrounded by the impurity region, and a drain which is formed inside the semiconductor substrate from the surface of the semiconductor substrate at a predetermined distance from the source, and in which a high concentration ion-implanted impurity of a different form from the semiconductor substrate is implanted; On the low-concentration impurity region, on the semiconductor substrate between the source and the drain, and on a gate oxide film formed on a part of the drain, on the low-concentration impurity region, and on the semiconductor substrate between the source and the drain. And a part of the drain, a floating gate formed via a gate oxide film, a first interlayer insulating film formed on the floating gate, and a first interlayer insulating film And formed control gate, is formed in a vertical direction with respect to the floating gate 5 and the side wall so as to cover the semiconductor substrate 1 of the surface of the control gate 7,
Second for insulating the floating gate 5 from the control gate 7
An interlayer insulating film 8 and an auxiliary gate 9 which is in contact with the interlayer insulating film 8 and is formed above the predetermined regions of the source 2 and the drain 3 with a gate oxide film 4 interposed therebetween are configured. .

The flash EEPR according to the present invention
In a method of manufacturing an OM, a floating / control gate forming step of sequentially forming a gate oxide film, a floating gate, a first interlayer insulating film, and a control gate on a semiconductor substrate, and a step of forming the floating gate and the control gate electrode. Second formation of a second interlayer insulating film for insulating the side wall
An interlayer insulating film forming step, a polysilicon film is vapor-deposited on the entire surface, and the polysilicon film is anisotropically etched so that the polysilicon film has a spacer shape on the side surface of the second interlayer insulating film. Forming a source / drain by injecting a high-concentration impurity into the semiconductor substrate 1 to form a source and a drain; Ions of an impurity form different from that of the first low-concentration impurity forming a first low-concentration impurity region below the electrode of the gate by selectively injecting into the electrode side of the source gate with an inclination with respect to the auxiliary gate. And a region forming step.

Further, between the floating / control gate forming step and the second interlayer insulating film forming step, a low concentration impurity is injected into a predetermined region of the semiconductor substrate where a drain is to be formed to form a second low concentration impurity region. You may make it further include the 2nd low concentration impurity formation process of forming.

[0011]

According to the above structure, the flash EEPROM having the drain surrounded by the second low concentration impurity region.
In M, the tunneling of electrons occurs between the auxiliary gate 9 and the floating gate 5 at the time of erasing due to the auxiliary gate formed above the predetermined region of the source and drain.
Excess electrons retained in the floating gate 5 are removed. Even if over-erasing occurs, the channel existing under the auxiliary gate 9 maintains a non-conducting state unless a voltage above a certain level is applied to the auxiliary gate 9, so that the operating characteristics are particularly affected. do not do.

This effect is the same in the flash EEPROM in which the second low concentration impurity region is not formed.
Further, if manufactured by the above manufacturing method, a flash EEPROM having an auxiliary gate is formed.

[0013]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. As shown in FIGS. 1 and 2, the flash EEPROM of this embodiment according to the present invention is formed by adding an auxiliary gate electrode to the laminated gate electrode of a general flash EEPROM.

In FIG. 1, a conventional flash EEPR is shown.
Similar to the OM, the source 2 and the drain 3 are formed by injecting a high concentration impurity into a low concentration impurity region from the surface to the inside of the semiconductor substrate 1. The difference from the conventional EEPROM is that the auxiliary gate 9 is formed on the side surfaces of the floating gate 5 and the control gate 7 via the interlayer insulating film 8, and the source 2 has the same type as the semiconductor substrate 1 and the impurity type low concentration. The drain 3 is surrounded by the impurity region 2 ′, and the drain 3 is also surrounded by the impurity type low concentration region 3 ′ having a different form from the semiconductor substrate 1 under the gate. And this flash EE
In the PROM, the gate oxide film 4,
The floating gate 5, and the interlayer insulating film 6 and the control gate 7 are sequentially formed on the floating gate 5.

An interlayer insulating film 8 is formed in a direction perpendicular to the surface of the semiconductor substrate 1 so as to cover the side surfaces of the floating gate 5 and the control gate 7.
And the control gate 7 is insulated. The auxiliary gate 9 is in contact with the interlayer insulating film 8 and the source 2 through the gate oxide film 4.
And formed on a predetermined region of the drain 3. In such a structure, electrons are tunneled between the auxiliary gate 9 and the floating gate 5 at the time of erasing, and the surplus electrons stored in the floating gate 5 are removed.

In another flash EEPROM of the present invention shown in FIG. 2, the drain 3 is not surrounded by the low-concentration region under the gate 5, and the area in contact with the floating gate 5 is enlarged to float. Gate 5
The electrons are tunneled in the drain 3. The equivalent circuit of the EEPROM of the present invention is shown in FIG.
Shown in.

Next, the manufacturing process of the EEPROM of the present invention will be described in detail with reference to FIGS. First, FIG.
2 is a plan view of an embodiment realizing the device structure of the present invention shown in FIG. 1, in which 2 is a source, 5 is a floating gate, 7 is a control gate, 9 is an auxiliary gate, 12 is a drain, and 13 is The metal active region which is the contact of the drain 12 is shown.

5 to 9 are cross-sectional views during the manufacturing process, which correspond to the cross-sectional view taken along the cutting line AA 'in the plan view shown in FIG. The method of manufacturing the EEPROM of the present invention will be described in detail with reference to FIGS. First, as shown in FIG. 5, a gate oxide film 4, a floating electrode 5, an interlayer insulating film 6, and a control gate 7 are sequentially formed on a P-type semiconductor substrate 1 as in the conventional laminated gate electrode forming step.

Then, as shown in FIG. 6, a photoresist film 10 is applied and patterned to expose a part of the gate, and then a low concentration impurity region 3'for forming a drain region is formed. Next, as shown in FIG. 7, an interlayer insulating film 8 for sidewall insulation of the floating gate 5 and the control gate 7 is formed.
After forming and insulating, a polysilicon film is vapor-deposited on the entire surface, and a spacer-shaped auxiliary gate 9 made of a polysilicon film is formed on the sidewall of the interlayer insulating film 8 by anisotropic etching.

Then, as shown in FIG. 8, n-type high-concentration impurities are implanted by the same method as the low-concentration n-type impurity implantation performed for forming the drain of FIG. After the formation, the region where the drain is formed is masked by the pattern of the photosensitive film 10, and the p-type low-concentration impurity is injected to the gate side of the source 2 into which the n-type high-concentration impurity has been injected to form the low-concentration impurity region. To form 2 '.
At this time, as shown by the arrow in the figure, low-concentration p-type impurities are implanted from the oblique direction of the auxiliary gate 9. The reason for this is to control that the pn junction side of the source region becomes longer,
This is to prevent punch through from occurring.

Finally, as shown in FIG. 9, after the oxide film 11 is applied with the source 2 and the drain 3 formed, a predetermined region of the oxide film 11, that is, the oxide film on the drain 3 formed. 11 is etched to form contact holes for metal 12 (aluminum) connection, metal 1
Connect with 2. Next, the operation state of the EEPROM of the present invention shown in FIG. 2 will be described in detail.

Information "1", "1" based on the storage state of electrons in the floating gate 5 is formed by the four terminals of the source 2, the drain 3, the control gate 7 and the auxiliary gate 9 and the floating gate 5 connected to the outside. 0 "is determined. First, the programming process of inputting information "1" into the device means injecting surplus electrons into the floating gate electrode 5, but for programming, a high voltage of about 10V to 12V is applied to the control gate 7. In this state, 5 V to 7 V is applied to the drain 3 and the source 2 is grounded. At this time, when a voltage of about 1.2 V to 2 V is applied to the auxiliary gate 9, a strong electric field is formed at the boundary surface between the auxiliary gate 9, the floating gate 9 and the floating gate 9, and thermoelectrons are generated. The electrons are effectively injected into the floating gate 5 by the electric field created by the high voltage of the control gate 7.

On the contrary, in the erasing process for taking out the electrons injected into the floating gate 5, the source 2,
With the drain 3 and the control gate 7 all grounded, a high voltage of about 15V to 18V is applied to the auxiliary gate 9. In this way, F-N tunneling of electrons occurs through the thin interlayer oxide film 6 that insulates the auxiliary gate 9 and the floating gate 5, and the electrons stored in the floating gate 5 are transferred to the auxiliary gate 9. The stored information is erased.

On the other hand, the problem of so-called over-erasure is solved by the existence of the auxiliary gate 9. The over-erasure is a conduction phenomenon even when a channel existing under the floating gate 5 does not apply a voltage to the control gate 7 when a large amount of electrons escape, the line charge amount of the floating gate 5 becomes positive. In the present invention, since the auxiliary gate 9 is present, even if over-erasing occurs, if a voltage of a certain level or higher is not applied to the auxiliary gate 9, the auxiliary gate 9 is placed below the auxiliary gate 9. The non-conducting state is maintained in the existing channels. Therefore, even if over-erasing occurs in the unit element, there is no problem in operating characteristics.

The read process means that the information stored in the storage element is "0" or "1".
In order to read the information stored in the storage element, a voltage of about 3V to 5V is applied to the control gate 7 and the auxiliary gate 9 and the drain 3 is grounded. In this state, the source 2 has about 1.2
When a voltage of 2 V is applied from V, the programmed device, that is, the device in which the surplus electrons are stored in the floating gate 5, is kept in the non-conducting state and no current flows between the source 2 and the drain 3. Then, the erased element, that is, the element in which the surplus electrons are not present in the floating gate 5, becomes conductive and a current of several tens of μA flows. Therefore, information can be easily read by using a current sense amplifier that is capable of sensing such a current flow and connected to the storage element. Here, unlike the existing method, the voltage is applied to the source region instead of the drain region because the asymmetrical element structure causes the source 2 and the drain 3 to conduct.
This is because there is a difference in the conduction current flowing between them depending on the application method.

FIG. 3 is an equivalent circuit diagram of the storage element described above.
Shown in. In addition, the device operation for that operation is summarized in Table 1.

[0027]

[Table 1]

Next, another flash EEPROM of the present invention shown in FIG. 2 is a modification of the erasing method. In such a flash EEPROM, F-N tunneling occurs at the portion where the floating gate 5 and the drain 3 overlap. The system that operates to do so is adopted. For example, when a voltage of about 5V is applied to the drain 3 and a voltage of about -12V to -18V is applied to the control gate 7,
In the region where the floating gate 5 and the drain 3 overlap, tunneling of electrons occurs, and the surplus electrons stored in the floating gate 5 come out to the drain 3, thereby enabling erasing. The other reading and programming processes are the same as those of the flash EEPROM having the structure of FIG. 1, and the operation states thereof are shown in Table 2.

[0029]

[Table 2]

According to this structure, the auxiliary gate 9 is formed in contact with the interlayer insulating film 8 and above the predetermined region of the source 2 and the drain 3 with the gate oxide film 4 interposed therebetween. If the above voltage is not applied, the channel existing under the auxiliary gate 9 maintains the non-conducting state, so that even if over-erasing occurs, it does not affect the operating characteristics.

Further, by using the auxiliary gate 9 as a gate electrode having a spacer structure, the size of the device can be significantly reduced, and a low voltage power supply can be operated at the time of programming to realize a low power device. There is an effect that can be. Further, by forming the low concentration p-type impurity region in the source 2, the occurrence of punch through is suppressed.

[0032]

As described above, according to the present invention, the flash EE in which the second low concentration impurity region is not formed is provided.
In the PROM, an auxiliary gate is formed above the predetermined regions of the source and drain through the gate oxide film in contact with the interlayer insulating film, so that if a voltage higher than a certain level is applied to the auxiliary gate, the auxiliary gate is formed below the auxiliary gate. Since the non-conducting state is maintained in the channel existing in, there is no influence on the operation even if over-erasing occurs. In addition, by using the gate electrode having the spacer structure as the auxiliary gate, the size of the element can be significantly reduced, and it is possible to operate with a low voltage power source during programming, and it is possible to realize a low power element. is there.

In the flash EEPROM in which the second low-concentration impurity region is not formed, tunneling of electrons occurs in the region where the floating gate and the drain overlap, and the surplus electrons stored in the floating gate are drained to the drain. Because it comes out, it becomes possible to erase,
It can be operated in the same manner. Then, a polysilicon film is vapor-deposited on the entire surface, and the polysilicon film is anisotropically etched so that the polysilicon film has a spacer shape on the side surface of the second interlayer insulating film, whereby the auxiliary gate is formed into the first film. It can be formed on the side surface of the interlayer insulating film.

After forming the floating / control gate, a second low-concentration impurity region can be formed by implanting a low-concentration impurity into a predetermined region of the semiconductor substrate where the drain is to be formed.

[Brief description of drawings]

FIG. 1 is a structural diagram of an EEPROM according to an embodiment of the present invention.

FIG. 2 is an EEPROM structure diagram according to another embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of the EEPROM shown in FIGS. 2A and 2B.

FIG. 4 is a plan view of an EEPROM according to the present invention.

5 is a sectional view of the manufacturing process corresponding to the section line AA ′ in FIG. 3;

FIG. 6 is a sectional view of the manufacturing process of the same as above.

FIG. 7 is a sectional view of the manufacturing process of the same as above.

FIG. 8 is a sectional view of the manufacturing process of the same as above.

FIG. 9 is a sectional view of the manufacturing process of the same.

FIG. 10 is an equivalent circuit diagram of a conventional EEPROM.

11 is a structural diagram of the EEPROM of FIG.

[Explanation of symbols]

 1 semiconductor substrate 2 source 2 ', 3'low concentration impurity region 3 drain 4 gate oxide film 5 floating gate 6,8 interlayer insulating film 7 control gate 9 auxiliary gate 10 photosensitive film 11 oxide film 12 metal 13 active region

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] January 6, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

FIG. 3 is an equivalent circuit diagram of the EEPROM shown in FIGS. 1 and 2.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

FIG. 5 is a sectional view of a manufacturing process corresponding to the section line AA ′ in FIG. 4;

Claims (4)

[Claims]
1. In a flash EEPROM, a semiconductor substrate 1 is formed by performing high-concentration ion implantation of impurities of a form different from that of the semiconductor substrate 1 from the surface to the inside of the semiconductor substrate 1,
The source 2 surrounded by the first low-concentration impurity region 2'in which the impurity of the same form as that of the semiconductor substrate 1 is injected at a low concentration and the source are spaced apart from the surface of the semiconductor substrate 1 by a predetermined distance. A second low-concentration impurity region 3 ′ which is formed inside and in which an impurity of a different form from that of the semiconductor substrate 1 is ion-implanted at a high concentration and an impurity of a form different from that of the semiconductor substrate 1 is injected at a low concentration is surrounded. The surrounded drain 3, the gate oxide film 4 formed on the upper portion between the source 2 and the drain 3, the low concentration impurity region 2 ′, and the semiconductor substrate 1 between the source 2 and the drain 3. , And the second low concentration impurity region 3 ′
A floating gate 5 formed on the gate oxide film 4, a first interlayer insulating film 6 formed on an electrode of the floating gate 5, and a control formed on the first interlayer insulating film 6. A gate 7 and a second interlayer insulating film 8 which is formed in a direction perpendicular to the surface of the semiconductor substrate 1 so as to cover the sidewalls of the floating gate 5 and the control gate 7, and insulates the floating gate 5 and the control gate 7 from each other. A flash EEP, which is in contact with the interlayer insulating film 8 and includes an auxiliary gate 9 formed on a predetermined region of the source 2 and the drain 3 via a gate oxide film 4.
ROM.
2. In a flash EEPROM, a semiconductor substrate 1 is formed by performing high-concentration ion implantation of impurities of a form different from that of the semiconductor substrate 1 from the surface to the inside of the semiconductor substrate 1.
The source 2 surrounded by the first low-concentration impurity region 2'in which the impurity of the same form as that of the semiconductor substrate 1 is injected at a low concentration and the source are spaced apart from the surface of the semiconductor substrate 1 by a predetermined distance. A drain 3 which is formed inside and into which a different form of impurity from the semiconductor substrate 1 is ion-implanted with high concentration, a low concentration impurity region 2 ′, a semiconductor substrate 1 between the source 2 and the drain 3, and A gate oxide film 4 is formed on a part of the drain 3, a gate oxide film is formed on the low concentration impurity region 2 ′, on the semiconductor substrate 1 between the source 2 and the drain 3, and on the drain 3. A floating gate 5 formed via a film 4, a first interlayer insulating film 6 formed on the floating gate 5, a control gate 7 formed on the first interlayer insulating film 6, and the floating gate 5 and control A second interlayer insulating film 8 that is formed in a direction perpendicular to the surface of the semiconductor substrate 1 so as to cover the sidewall of the gate 7 and insulates the floating gate 5 from the control gate 7, and is in contact with the interlayer insulating film 8. A flash EEP including an auxiliary gate 9 formed on a predetermined region of the source 2 and the drain 3 via a gate oxide film 4.
ROM.
3. A method of manufacturing a flash EEPROM, comprising a floating / control gate forming step of sequentially forming a gate oxide film 4, a floating gate 5, a first interlayer insulating film 6, and a control gate 7 on a semiconductor substrate 1. A second interlayer insulating film 8 for insulating the sidewalls of the floating gate 5 and the control gate electrode 7 formed
An interlayer insulating film forming step, a polysilicon film is vapor-deposited on the entire surface, and the polysilicon film is anisotropically etched so that the polysilicon film has a spacer shape on the side surface of the second interlayer insulating film 8. Forming an auxiliary gate by using a polysilicon film of the form as an auxiliary gate 9 on the side surface of the second interlayer insulating film 8 and forming source / drain by forming a source 2 and a drain 3 by injecting a high concentration impurity into the semiconductor substrate 1. Steps and ions of an impurity form different from those of the semiconductor substrate 1 are selectively implanted into the electrode side of the gate 5 of the source 2 with an inclination with respect to the auxiliary gate 9 to form a first low concentration under the electrode of the gate 5. A first low-concentration impurity region forming step of forming an impurity region 2 ', and a flash EE.
Manufacturing method of PROM.
4. A second low-concentration impurity is implanted by implanting a low-concentration impurity into a predetermined region of the semiconductor substrate 1 in which the drain 3 is to be formed between the floating / control gate forming step and the second interlayer insulating film forming step. 4. The method of manufacturing a flash EEPROM according to claim 3, further comprising a second low-concentration impurity forming step of forming the region 3 '.
JP33770593A 1992-12-31 1993-12-28 Flash eeprom and manufacture thereof Pending JPH06232413A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR920027323 1992-12-31
KR1992-27323 1992-12-31

Publications (1)

Publication Number Publication Date
JPH06232413A true JPH06232413A (en) 1994-08-19

Family

ID=19348483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33770593A Pending JPH06232413A (en) 1992-12-31 1993-12-28 Flash eeprom and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH06232413A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01304784A (en) * 1988-06-02 1989-12-08 Seiko Instr Inc Semiconductor non-volatile memory
JPH0362574A (en) * 1989-07-31 1991-03-18 Toshiba Corp Nonvolatile semiconductor storage device and operating method therefor
JPH03174777A (en) * 1989-12-04 1991-07-29 Toshiba Corp Semiconductor device and manufacture thereof
JPH04274370A (en) * 1991-03-01 1992-09-30 Matsushita Electron Corp Semiconductor device and manufacture thereof and semiconductor integrated circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01304784A (en) * 1988-06-02 1989-12-08 Seiko Instr Inc Semiconductor non-volatile memory
JPH0362574A (en) * 1989-07-31 1991-03-18 Toshiba Corp Nonvolatile semiconductor storage device and operating method therefor
JPH03174777A (en) * 1989-12-04 1991-07-29 Toshiba Corp Semiconductor device and manufacture thereof
JPH04274370A (en) * 1991-03-01 1992-09-30 Matsushita Electron Corp Semiconductor device and manufacture thereof and semiconductor integrated circuit

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