JPH04274370A - Semiconductor device and manufacture thereof and semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To simplify the control of size on manufacture without increasing manufacturing processes, and to prevent erroneous write at the time of read. CONSTITUTION:The gate electrode structure of two layers is formed. The high- concentration ion implantation 10 of another conductivity type different from a semiconductor substrate 1 is conducted at an incident angle, where the sidewalls of gate electrodes 6, 7 on the source side are shaped on write. The low-concentration ion implatation 11 of another conductivity type different from the semiconductor substrance 1 is performed at an incident angle, where the sidewalls of the gate electrodes 6, 7 on the drain side are shaped on write. Impurities 12, 13 implanted are diffused through heat treatment, and high- concentration diffusion layers 2, 4 and low-concentration diffusion layers 3, 5 are formed. A wiring electrode 15 on the drain side at the time of write and a wiring electrode 16 on the source side at the time of write are formed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a nonvolatile memory transistor having a floating gate electrode, a method for manufacturing the same, and a semiconductor integrated circuit.

0002

2. Description of the Related Art In recent years, with the miniaturization of integrated circuit devices, the capacity and speed of nonvolatile memory devices have been increasing. As the writing speed of the nonvolatile memory transistors constituting the nonvolatile memory device increases, it becomes easier to write to the nonvolatile memory transistors, but on the other hand, writing errors during reading become more likely to occur. Furthermore, as the capacity increases, the probability of erroneous writing during reading also increases.

As a measure to prevent erroneous writing during reading, there is a method of reducing the generation of hot carriers during reading by making the drain structure during writing different from the drain structure during reading. FIG. 4 is a cross-sectional view of a conventional semiconductor device in which measures are taken to prevent erroneous writing during reading. This semiconductor device is an ultraviolet erasable electrically programmable nonvolatile memory (EPROM) having a floating gate electrode. In FIG. 4, 1 is a semiconductor substrate (or a well diffusion layer formed in the semiconductor substrate), 22 is a high concentration diffusion layer on the drain side during writing, 24 is a high concentration diffusion layer on the source side during writing, and 25 is a high concentration diffusion layer on the source side during writing. A low concentration diffusion layer on the source side during writing, 6 a floating gate electrode, 7 a control gate electrode, 8 a first gate insulating film, and 9 a second gate insulating film.

During writing, hot carriers are generated and electrons are injected into the floating gate electrode 6 by applying a high voltage to the heavily doped diffusion layer 22 on the drain side where the electric field strength is strong. During reading, the high concentration diffusion layer 24 on the source side during writing is used as a drain. At this time, the voltage at the time of reading is
5, the electric field strength is relaxed, the generation of hot carriers is suppressed, and erroneous writing during reading can be reduced.

Low concentration diffusion layer 25 on the source side during writing
The so-called LDD (Light
tly DopedDrain) area.

[0006]

However, it is difficult to form the low concentration diffusion layer 25 on the source side during writing, which is provided to prevent erroneous writing during reading. The general method for forming an LDD structure is to form a low concentration diffusion layer, then form a spacer such as an oxide film on the sidewall of the gate electrode, and use this as a mask to form the high concentration diffusion layer of the source and drain in a self-aligned manner. It is to be formed. However, as shown in FIG. 4, in order to form the low concentration diffusion layer 25 only on one side of the gate electrodes 6 and 7, one spacer provided on the side wall of the gate electrode must be removed, which requires a mask process. This adds an etching process and increases the number of manufacturing steps. There is also a method of forming the high concentration diffusion layer 24 on the source side during writing using a mask, but in this case it is disadvantageous for miniaturization because it cannot be formed in a self-aligned manner. That is,
It becomes difficult to control the length (offset length) from the gate edge of the low concentration diffusion layer 25 on the source side to the high concentration diffusion layer 24 on the source side.

An object of the present invention is to provide a semiconductor device, a method for manufacturing the same, and a semiconductor integrated circuit that can easily control dimensions during manufacturing without increasing the number of manufacturing steps and can prevent erroneous writing during reading. .

[0008]

Means for Solving the Problems A semiconductor device according to claim 1 includes: a semiconductor substrate of one conductivity type; a gate oxide film formed on the semiconductor substrate; and a gate electrode formed on the gate oxide film. a first low concentration diffusion layer formed in the semiconductor substrate away from the first end of the gate electrode; a first high concentration diffusion layer formed in the semiconductor substrate close to the first end;
A second low concentration diffusion layer formed in the semiconductor substrate close to the second end of the gate electrode, and a second high concentration diffusion layer formed in the semiconductor substrate away from the second end. ing.

A semiconductor device according to a second aspect of the present invention is a semiconductor device according to a first aspect, in which an end portion of the first high concentration diffusion layer or the second low concentration diffusion layer on the gate electrode side is located at the end portion of the first high concentration diffusion layer or the second low concentration diffusion layer. It is characterized by being located inside the first end or the second end. A method for manufacturing a semiconductor device according to claim 3 includes the steps of forming a first gate insulating film on a semiconductor substrate of one conductivity type, and forming a first gate electrode on the first gate insulating film. , a step of forming a second gate insulating film on the first gate electrode, a step of forming a second gate electrode on the second gate insulating film, and a step of forming a second gate electrode on the second gate insulating film, and a step of forming a second gate insulating film on the first gate electrode, and a step of forming a second gate electrode on the second gate insulating film, and a step of forming a second gate insulating film on the first gate electrode, and a step of forming a second gate electrode on the second gate insulating film. A step of performing diagonal high-concentration first ion implantation into the mold, and a step of performing diagonal second ion implantation of the same conductivity type as the first ion implantation from the source direction during writing in the opposite direction to the drain direction. the first and second ion implantations are performed on the first gate insulating film,
The method is characterized in that ion implantation is performed using the first gate electrode, the second gate insulating film, and the second gate electrode as masks.

A semiconductor integrated circuit according to a fourth aspect of the present invention provides a first word line extending in the X-axis direction and a plurality of first bit lines connected to a first bit line perpendicularly intersecting the first word line. a plurality of second nonvolatile memory elements connected to a second bit line extending in the X-axis direction and a second word line perpendicularly intersecting the second bit line; , a semiconductor substrate on which first and second non-volatile memory elements are simultaneously formed, and the diffusion layers of the first and second non-volatile memory elements are aligned with respect to a first surface perpendicular to the plane of the semiconductor substrate. It is characterized in that it is formed by first ion implantation tilted at a first predetermined angle, and second ion implantation tilted at a second predetermined angle into the first surface in symmetry with the first ion implantation.

[0011] The semiconductor integrated circuit according to claim 5 is the semiconductor integrated circuit according to claim 4, characterized in that the first surface is parallel to the first word line or the second bit line.

0012

[Operation] According to the structure of the present invention, the first low concentration diffusion layer is formed in the semiconductor substrate away from the first end of the gate electrode, and the first low concentration diffusion layer is formed in the semiconductor substrate close to the first end. a first high concentration diffusion layer formed in the semiconductor substrate close to the second end of the gate electrode; a second low concentration diffusion layer formed in the semiconductor substrate away from the second end; By providing a second high concentration diffusion layer, during writing, the gate edge has a high concentration diffusion layer near the gate edge on the drain side, and a low concentration diffusion layer at a location away from the gate edge. Near the edge, the impurity concentration gradient becomes steeper, the electric field strength becomes stronger, and hot carriers required during writing are more likely to be generated. In addition, there is a low concentration diffusion layer near the gate edge on the source side during writing (drain side during reading), and a high concentration diffusion layer at a location away from the gate edge, so the impurity concentration near the gate edge is The gradient becomes gentler, the electric field strength becomes weaker, and even if the necessary voltage is applied during reading, fewer hot carriers are generated, and erroneous writing can be prevented.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a step-by-step sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Although not shown, a first gate insulating film material, a floating gate electrode material, a second gate insulating film material, and a control gate electrode material are sequentially formed on the surface of a semiconductor substrate 1 of one conductivity type, and then a resist is used as a mask. The control gate electrode material, the second gate insulating film material, the floating gate electrode material, and the first gate insulating film material are etched in this order. A two-layer gate electrode structure of a nonvolatile memory transistor consisting of a gate electrode (gate electrode) 6, a second gate insulating film 9, and a control gate electrode (second gate electrode) 7 is formed.

Next, as shown in FIG. 1(a), at an incident angle at which the side walls (one side wall) of the gate electrodes 6 and 7 on the source side are in the shadow during writing, a conductivity type different from that of the semiconductor substrate 1 is detected. High concentration ion implantation 10 is performed. The incidence angle of this high concentration ion implantation 10 is from 7 degrees to 30 degrees with respect to the normal to the substrate.
However, the low concentration diffusion layers 3 and 5 to be formed later (Fig. 1(
c) If the diffusion depth in (c)) is shallow, the angle should be 20 to 30 degrees. 12 indicates the implanted impurity.

Next, as shown in FIG. 1(b), at an incident angle at which the sidewalls (the other sidewalls) of the gate electrodes 6 and 7 on the drain side are in the shadow during writing, a conductivity type different from that of the semiconductor substrate 1 is detected. Low concentration ion implantation 11 is performed. The incidence angle of this low concentration ion implantation 11 is 20 to 30 degrees with respect to the normal to the substrate. 13 indicates the implanted impurity. After that, an oxidation, annealing process, etc. are performed to form an interlayer insulating film 14, and a heat treatment is performed to diffuse the implanted impurities 12 and 13, forming high concentration diffusion layers 2 and 4 and low concentration diffusion layers 3 and 5. do. After this, a wiring electrode 15 on the drain side for writing and a wiring electrode 16 on the source side for writing are formed (
Figure 1(c)).

The operation of the semiconductor device formed as described above will be explained with reference to FIG. During writing, since there is a high concentration diffusion layer 2 at the gate edge which is on the drain side during writing, the electric field strength becomes stronger at the gate edge.
Hot carriers are generated and electrons are injected into the floating gate electrode 6. During reading, since the low concentration diffusion layer 5 is present at the gate edge on the drain side during reading, the electric field strength is relaxed at the gate edge, suppressing the generation of hot carriers, and preventing erroneous writing during reading.

It should be noted that the ion implantation 10,1 explained in FIG.
The lower limit of the incident angle of 1 is the offset distance between the high concentration diffusion layers 2, 4 and the low concentration diffusion layers 3, 5, the so-called offset length L1,
Determined by L2 (FIG. 2). The offset length L1 is
The offset length L2 is the offset distance between the high concentration diffusion layer 2 and the low concentration diffusion layer 3 on the drain side during writing, and the offset length L2 is the offset distance between the high concentration diffusion layer 4 and the low concentration diffusion layer 5 on the source side during writing. It is distance. This offset length L1
, L2 are determined in a self-aligned manner by the height of the control gate electrode 7 from the substrate surface and the incident angle of the ion implantations 10 and 11, and the height of the control gate electrode 7 from the substrate surface is approximately 0.5 to 0. .7 μm, the diffusion depth of the high concentration diffusion layers 2 and 4 is approximately 0.25 μm, and the diffusion depth of the low concentration diffusion layers 3 and 5 is approximately 0.
．． In the case of 5 μm, L1=0.05 to 0.27 μm,
L2=0.25 to 0.55 μm.

Further, the upper limit of the incident angle of the ion implantations 10 and 11 depends on the inclination angle at the end of the thick film for element isolation (not shown). If the incident angle is too large, a shadow will be created by a thick film for element isolation (not shown), and since no injection will be performed in the shadowed portion, a normal diffusion layer will not be formed. As described above, in this embodiment, the offset length L is determined by the height of the control gate electrode 7 from the substrate surface and the incident angle of the ion implantations 10 and 11 without increasing the number of manufacturing steps.
1 and L2 are determined in a self-aligning manner, improving dimensional controllability in manufacturing.

It should be noted that the order of the high concentration ion implantation 10 and the low concentration ion implantation 11 may be either performed first. Furthermore, a semiconductor integrated circuit to which the method of manufacturing a semiconductor device according to the present invention is applied will be described. Figure 3(a),(b)
shows two memory cell arrays arranged on the same integrated circuit device, FIG. 3(a) is a circuit diagram of the first group of memory cell arrays, and FIG. 3(b) is a circuit diagram of the second group of memory cell arrays. be.

The first group of memory cell arrays shown in FIG. 3(a) are formed by applying the semiconductor device manufacturing method according to the present invention and having word lines W1 arranged in the X direction.
In the second group of memory cell arrays in b), the method of manufacturing a semiconductor device according to the present invention is not applied, but the arrangement direction is rotated by 90 degrees with respect to the first group of memory cell arrays, and word lines W2 are arranged in the Y direction. It is. In addition, B1, B2
is the bit line (or source line).

According to this, it is possible to simultaneously form two types of memory cells for different purposes on the same integrated circuit device, and the first group of memory cell arrays is suitable for high speed, large capacity, and high readout applications. Therefore, the second group of memory cell arrays is suitable for low-speed, small-capacity, and low-number of read applications.

[0022]

According to the present invention, a low concentration diffusion layer is provided near the gate edge on the source side during writing (drain side during reading), and a high concentration diffusion layer is provided at a location away from the gate edge. Therefore, in the vicinity of the gate edge, the impurity concentration gradient becomes gentle and the electric field strength becomes weaker, and even if the necessary voltage is applied during reading, fewer hot carriers are generated, and erroneous writing can be prevented.

[0023] Furthermore, the distance between the high-concentration diffusion layer and the low-concentration diffusion layer, the so-called offset length, is determined in a self-aligned manner by the height of the multilayer gate electrode structure from the semiconductor substrate and the incident angle of ion implantation. Improves dimensional control. In this way, it is possible to realize a semiconductor device that can easily control dimensions during manufacturing and prevent erroneous writing during reading without increasing the number of manufacturing steps.

Furthermore, by preparing memory cells in which the arrangement direction of the memory cells is rotated by 90 degrees within the same integrated circuit device, it is possible to simultaneously form two types of memory cells for different purposes.

[Brief explanation of the drawing]

FIG. 1 is a step-by-step sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the semiconductor device in the same embodiment.

FIG. 3 is a diagram showing a semiconductor integrated circuit to which the method of manufacturing a semiconductor device according to the present invention is applied.

FIG. 4 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

1 Semiconductor substrate 2, 4 High concentration diffusion layer 3, 5 Low concentration diffusion layer 6 Floating gate electrode (first gate electrode) 7
Control gate electrode (second gate electrode) 8
First gate insulating film 9 Second gate insulating film 10 High concentration ion implantation 11 Low concentration ion implantation

Claims (5)

[Claims] 1. A semiconductor substrate of one conductivity type, a gate oxide film formed on the semiconductor substrate, a gate electrode formed on the gate oxide film, and a semiconductor substrate that is separated from a first end of the gate electrode. a first low concentration diffusion layer formed on the semiconductor substrate near the first end; a first high concentration diffusion layer formed on the semiconductor substrate close to the first end; and a second end of the gate electrode. a second portion formed on the semiconductor substrate near the portion;
A semiconductor device comprising: a low concentration diffusion layer; and a second high concentration diffusion layer formed in the semiconductor substrate apart from the second end. 2. An end of the first high concentration diffusion layer or the second low concentration diffusion layer on the gate electrode side is located inside the first end or the second end of the gate electrode, respectively. The semiconductor device according to claim 1, characterized in that: 3. A step of forming a first gate insulating film on a semiconductor substrate of one conductivity type, a step of forming a first gate electrode on the first gate insulating film, and a step of forming the first gate insulating film on the semiconductor substrate of one conductivity type. a step of forming a second gate insulating film on the electrode, a step of forming a second gate electrode on the second gate insulating film, and a step of forming a second gate electrode on the second gate insulating film; A step of performing a first ion implantation of a concentration obliquely, and a step of performing a second ion implantation of the same conductivity type as the first ion implantation obliquely from a source direction during writing in a direction opposite to the drain direction. The first and second ion implantations are performed using the first gate insulating film, the first gate electrode, the second gate insulating film, and the second gate electrode as masks. A method for manufacturing a semiconductor device. 4. A first word line extending in the X-axis direction;
a plurality of first nonvolatile memory elements connected to a first bit line perpendicularly intersecting the first word line; a second bit line extending in the X-axis direction; and the second bit line. a plurality of second word lines connected to a second word line perpendicularly intersecting the line;
and a semiconductor substrate on which the first and second nonvolatile memory elements are formed simultaneously,
, the diffusion layer of the second non-volatile memory element is implanted with a first ion implanted at a first predetermined angle with respect to the first surface perpendicular to the plane of the semiconductor substrate; 1. A semiconductor integrated circuit characterized in that the semiconductor integrated circuit is formed by a second ion implantation that is symmetrical to the ion implantation and tilted at a second predetermined angle. 5. The first surface is the first word line or the second word line.
5. The semiconductor integrated circuit according to claim 4, wherein the semiconductor integrated circuit is parallel to the bit line.