JPH06232353A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor wafer capable of preventing its warpage, a peeling of a metal silicide film and the like in the middle of a process of manufacturing a semiconductor device. CONSTITUTION:A metal silicide film 42 for wiring use and a polycrystalline silicon film 41 exist on a chip region within the surface of a semiconductor wafer in a laminated state and the film 42 does not exist on the peripheral region, on where the chip region is not formed, of the wafer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a C region in a chip region in a wafer central region.
MOS (complementary insulated gate) or BiCMOS (bipolar / CMOS) type LSI (large-scale integrated circuit)
And a method for manufacturing the same.

[0002]

2. Description of the Related Art FIGS. 4A to 4C are sectional views showing a conventional manufacturing process for forming a BiCMOS type LSI on a semiconductor wafer. First, as shown in FIG.
An N type buried layer 2 and a P type buried layer 3 are formed on a type semiconductor substrate (wafer) 1, respectively.

Thereafter, an N type epitaxial layer 4 is formed on the N type buried layer 2 and a P type well region 5 is formed on the P type buried layer 3. After that, the oxide film 6 in the element isolation region is formed by the selective oxidation method.

After that, for example, phosphorus is ion-implanted on the N-type epitaxial layer 4 and heat treatment is performed at 950 ° C. for about 60 minutes to make the collector electrode extraction portion 7 of the bipolar transistor into the N-type buried layer (of the bipolar transistor). It is formed so as to reach the collector region) 2.

After that, the N channel region 8 of the NMOS transistor and the P channel region 9 of the PMOS transistor are selectively formed by using the lithographic technique and the ion implantation method.

After that, a gate oxide film 10 is formed on the surface of the substrate, and a polycrystalline silicon film 11 is further deposited on the gate oxide film 10 by a CVD (vapor phase growth) method. Heat treatment is performed at 850 ° C. in the atmosphere. Then, a metal silicide film 12 is deposited on the polycrystalline silicon film 11.

Next, as shown in FIG. 4B, the gate electrode 13 of the MOS transistor is formed by using the ordinary lithography technique and RIE (reactive ion etching) technique.

At this time, as shown in the plan view of FIG. 5, the gate electrode 13 is formed in the chip region 51 in the central region of the wafer, and the gate electrode is formed in the wafer peripheral region where the chip region is not formed. The metal silicide film 12 which is the material of the above and the polycrystalline silicon film 11 thereunder remain in a laminated state. Then, in order to improve the reliability of the gate oxide film 10, oxidation is performed in a dry oxygen atmosphere at 900 ° C., for example.

Next, as shown in FIG. 4C, the emitter region 15 and the intrinsic base region 16, N of the bipolar transistor are formed by using the lithography technique and the ion implantation method.
N- regions 17 and N + regions 18 serving as the source / drain of the MOS transistor, a P + region 19 serving as the source / drain of the PMOS transistor, and a base electrode extraction portion 20 of the bipolar transistor are selectively formed.

After that, an insulating film 21 and a BPSG (boron phosphorus silicate glass) film 22 are sequentially deposited as an interlayer insulating film, and then heat treatment at 850 ° C. is performed. Then, contact holes are opened in the BPSG insulating film 22 and the insulating film 21, and the shape of the contact holes is rounded in order to improve the reliability of the metal wiring 23 formed later. Anneal. After that, a normal metal wiring process is performed, a surface protective film is further formed, and a pad opening is performed.

Until the final step, the metal silicide film 12 as the material of the gate electrode and the lower polycrystalline silicon film 11 remain in a laminated state in the wafer peripheral region where the chip region is not formed as described above. It is still done.

However, as described above, since the polycrystalline silicon film 11 and the metal silicide film 12 which are the material of the gate electrode remain in the peripheral region of the wafer where the chip is not formed until the final step, the rapid annealing step after the contact opening is performed. Then, the stress of the metal silicide film 12 becomes large, and the wafer warps.

As a result, when the mask misalignment becomes large in the subsequent lithography process and the wafer warp is large, when the wafer is loaded on the stepper, the wafer does not stick to the loader and the lithography process can be performed. The problem of disappearing arises.

In addition, in the area where the resist is removed around the wafer or the area where the resist is not applied,
Since there is a portion where the metal silicide film 12 is in direct contact with the oxide film having poor adhesion to the metal silicide film 12, there arises a problem that the metal silicide film 12 peels off in the process of oxidation or heat treatment after the formation of the metal silicide film. .

Further, when the resist mask for patterning the gate electrode 13 is formed by the RIE method, since the resist film remains in the wafer peripheral region where the chip region is not formed, the R in the chip region near the wafer peripheral region.
The IE etchant increases, and the etching rate increases. This causes a problem that the gate length dimension of the MOS transistor changes between the chip region in the central region of the wafer and the chip region near the peripheral region of the wafer.

[0016]

As described above, according to the conventional method of manufacturing a semiconductor device, the metal silicide film, which is the material of the gate electrode of the MOS transistor, remains in the peripheral region of the wafer where the chip region is not formed until the final step. Therefore, there is a problem that the wafer is warped during the manufacturing process, the metal silicide film is peeled off, and the etchant for RIE at the time of patterning the gate electrode is increased.

The present invention has been made to solve the above problems, and provides a semiconductor device and a manufacturing method thereof capable of preventing the warp of a wafer and the peeling of a metal silicide film during the manufacturing process. With the goal.

[0018]

The semiconductor device of the present invention comprises:
It is characterized in that a polycrystalline silicon film for wiring and a metal silicide film are present in a laminated state in a chip region in the plane of the semiconductor wafer, and the metal silicide film is not present in a wafer peripheral region where the chip region is not formed.

The semiconductor device manufacturing method of the present invention is
Depositing a polycrystalline silicon film on a substrate of a semiconductor wafer via a gate insulating film, diffusing impurities, and depositing a metal silicide film on the polycrystalline silicon film,
After applying the first resist film on the metal silicide film, the first resist film in the wafer peripheral region outside the chip region within the surface of the semiconductor wafer is removed, and the first resist film is formed on the chip region. A step of leaving the film, a step of etching the first resist film as a mask to remove the metal silicide film outside the chip region around the wafer, and a pattern of a second resist film on the chip region. And forming a gate electrode for a MOS transistor by using this resist film pattern as a mask, wherein a polycrystalline silicon film for wiring and a metal silicide film are present in a laminated state in a chip region on the surface of a semiconductor wafer. It is characterized in that a semiconductor wafer is manufactured in which the above-mentioned two films are not present in the wafer peripheral region where the chip region is not formed.

A method of manufacturing a semiconductor device according to the present invention is
Depositing a polycrystalline silicon film on a substrate of a semiconductor wafer via a gate insulating film, diffusing impurities, and depositing a metal silicide film on the polycrystalline silicon film,
After applying the first resist film on the metal silicide film, a step of exposing a gate electrode pattern to the chip area, and using a mask having no pattern in the wafer peripheral area outside the chip area, or using a mask The step of exposing the first resist film outside the chip region without using it and the etching using the first resist film as a mask form a gate electrode pattern in the chip region and at the same time outside the chip region. And the step of removing the metal silicide film and the polycrystalline silicon film, the polycrystalline silicon film for wiring and the metal silicide film are present in a stacked state in the chip region in the plane of the semiconductor wafer, and the chip region is not formed. It is characterized in that a semiconductor wafer in which the above-mentioned two films are not present in the wafer peripheral region is manufactured.

[0021]

After the metal silicide film is formed, all the metal silicide film, which is the material of the gate electrode, existing in the wafer peripheral region where the chip region is not formed is removed, so that the following effects can be obtained.

(1) The wafer is not warped in the rapid annealing process after the contact holes are opened to the interlayer insulating film formed in the subsequent process, and the subsequent lithography process becomes possible.

(2) In the peripheral area of the wafer, there is no place where the metal silicide film is in direct contact with the oxide film having poor adhesion to the wafer peripheral area, and in the peripheral area of the wafer in the process of oxidation or heat treatment after the formation of the metal silicide film. The problem that the metal silicide film peels off does not occur.

[0024]

Embodiments of the present invention will now be described in detail with reference to the drawings. (Example 1)

1A to 1F are cross-sectional views showing a manufacturing process for forming a BiCMOS type LSI according to a first embodiment of the present invention on a semiconductor wafer according to a design rule of 0.5 μm.

First, as shown in FIG. 1A, an N-type buried layer 32 and a P-type buried layer 33 are formed on a P-type semiconductor substrate 31, respectively. Then, an N-type epitaxial layer 34 is formed on the N-type buried layer 32, and a P-type well region 35 is formed on the P-type buried layer 33. After that, the oxide film 36 in the element isolation region is formed by the selective oxidation method.

After that, for example, phosphorus is ion-implanted on the N-type epitaxial layer 34, and heat treatment is performed at 950 ° C. for about 60 minutes to make the collector electrode extraction portion 37 of the bipolar transistor the N-type buried layer (of the bipolar transistor). It is formed so as to reach the collector region) 32.

After that, the N channel region 3 of the NMOS transistor is formed by using the lithographic technique and the ion implantation method.
8. P-channel regions 39 of PMOS transistors are selectively formed.

After that, a gate oxide film 40 is formed on the surface of the substrate, and the gate oxide film 4 is formed by the CVD method.
After depositing the polycrystalline silicon film 41 on the silicon oxide film, heat treatment is performed at 850 ° C. in an atmosphere of impurities such as phosphorus. Then, a metal silicide film 42 is deposited on the polycrystalline silicon film 41. The steps up to this point are the same as in the prior art.

Next, a sectional view and FIG. 2 shown in FIG.
As shown in the wafer top view shown in FIG.
After applying the resist film 43 on the surface of the semiconductor wafer 2, the resist film 43 in the wafer peripheral region where the chip region in the surface of the semiconductor wafer is not formed is removed, and the resist film 43 remains on the chip region.

In this case, the wafer peripheral region outside the chip region is exposed by the lithography technique with or without a mask having no pattern, and the resist 43 is left on the chip region.

Next, as shown in FIG. 1C, the metal silicide film 42 and the polycrystalline silicon film 41 in the peripheral region of the wafer are all removed by using the RIE or CDE (chemical dry etching) technique.

Next, as shown in FIG. 1D, a resist mask 44 for patterning the gate electrode of the MOS transistor is formed in the chip region by using a normal lithography technique. Next, as shown in FIG.
Gate electrode 4 of MOS transistor using RIE technology
Patterning 5 is performed.

Thereafter, as in the prior art, in order to improve the reliability of the gate oxide film 40, oxidation is performed in a dry oxygen atmosphere at 900 ° C., for example. Further, as shown in FIG. 1F, the emitter region 46 and the intrinsic base region 47 of the bipolar transistor, the N- region 48 and the N + region serving as the source / drain of the NMOS transistor are formed by using the lithography technique and the ion implantation method. 49, a P + region 50 serving as the source / drain of the PMOS transistor, and a base electrode extraction portion 51 of the bipolar transistor are selectively formed.

After that, an insulating film 52 and a BPSG film 53 are sequentially deposited as an interlayer insulating film, and then heat treatment at 850 ° C. is performed. In order to open contact holes in the BPSG insulating film 53 and the insulating film 52 and to round the shape of the contact holes for the purpose of improving the reliability of metal wiring, for example, Al (aluminum) wiring 54, which will be formed later. Then, rapid annealing at, for example, 1000 ° C. is performed. After that, a normal Al wiring process is performed, a surface protective film is further formed, and a pad opening is performed. (Example 2)

FIGS. 3A to 3D are sectional views showing a manufacturing process for forming a BiCMOS type LSI according to a second embodiment of the present invention on a semiconductor wafer according to a design rule of 0.5 μm.

First, as shown in FIG. 3A, an N type buried layer 62 and a P type buried layer 63 are formed on a P type semiconductor substrate 61, respectively. After that, an N-type epitaxial layer 64 is formed on the N-type buried layer 62, and a P-type well region 65 is formed on the P-type buried layer 63. After that, the oxide film 66 in the element isolation region is formed by the selective oxidation method.

After that, for example, phosphorus is ion-implanted on the N-type epitaxial layer 64, and heat treatment is performed at 950 ° C. for about 60 minutes so that the collector electrode extraction portion 67 of the bipolar transistor is formed on the N-type buried layer (of the bipolar transistor). It is formed so as to reach the collector region) 62.

After that, the N channel region 6 of the NMOS transistor is formed by using the lithographic technique and the ion implantation method.
8. P-channel regions 69 of PMOS transistors are selectively formed.

After that, a gate oxide film 70 is formed on the surface of the substrate, and the gate oxide film 7 is formed by the CVD method.
After depositing the polycrystalline silicon film 71 on 0, heat treatment is performed at 850 ° C. in an atmosphere of impurities such as phosphorus. Then, a metal silicide film 72 is deposited on the polycrystalline silicon film 71. The steps up to this point are the same as in the prior art.

Next, as shown in FIG. 3B, after a resist film is applied by a lithography technique, a gate electrode pattern is exposed in the central region of the wafer where the chip region is formed, and the chip region is not formed. The resist film is exposed in the peripheral region of the wafer using a mask having no pattern or without using a mask, and the resist 73 is left only in the gate pattern.

Next, as shown in FIG. 3C, the gate electrode 74 is patterned and formed in the chip region by using the RIE technique, and at the same time, the metal silicide film 72 and the polycrystalline silicon in the wafer peripheral region outside the chip region are formed. The film 71 is entirely removed.

Thereafter, as in the prior art, in order to improve the reliability of the gate oxide film 70, oxidation is performed in a dry oxygen atmosphere at 900 ° C., for example. Further, as shown in FIG. 3D, the emitter region 75 and the intrinsic base region 76 of the bipolar transistor, the N − region 77 and the N + region serving as the source / drain of the NMOS transistor are formed by using the lithography technique and the ion implantation method. 78, a P + region 79 serving as the source / drain of the PMOS transistor, and a base electrode extraction portion 80 of the bipolar transistor are selectively formed.

After that, an insulating film 81 and a BPSG film 82 are sequentially deposited as an interlayer insulating film, and then heat treatment at 850 ° C. is performed. Then, contact holes are formed in the BPSG insulating film 82 and the insulating film 81, and Al formed later is formed.
In order to make the shape of the contact hole round in order to improve the reliability of the wiring 83, rapid annealing at 1000 ° C., for example, is performed. After that, a normal Al wiring process is performed, a surface protective film is further formed, and a pad opening is performed.

According to each of the above-mentioned embodiments, after the metal silicide film is formed, the metal silicide film and the polycrystalline silicon film which are the material of the gate electrode existing in the peripheral region of the wafer where the chip region is not formed are all removed. The effect as described in is obtained.

(1) Since the in-wafer coverage of the metal silicide film is reduced, the stress exerted on the semiconductor substrate by the metal silicide film in the rapid annealing process after the contact holes are opened to the interlayer insulating film formed in the subsequent process. To reduce
It becomes possible to reduce the wafer warp. Therefore, the subsequent lithography process becomes possible.

(2) In the region where the resist is removed or the region where the resist is not applied around the wafer, there is no place where the metal silicide film is in direct contact with the oxide film having poor adhesion to it. Therefore, the problem of peeling of the metal silicide film in the peripheral region of the wafer does not occur in the process of oxidation or heat treatment after the formation of the metal silicide film.

(3) By forming a resist mask for patterning the gate electrode after forming the metal silicide film by using the invention of the second embodiment, at the same time, the resist in the chip area near the wafer peripheral area is also removed. The problem that RIE etchant increases in the chip region near the wafer peripheral region and the etching rate increases, and the etchant in the wafer surface becomes uniform. Therefore, the problem that the gate length dimension of the MOS transistor changes between the chip region in the central region of the wafer and the chip region near the peripheral region of the wafer does not occur.

[0049]

As described above, according to the present invention, it is possible to realize a semiconductor device capable of preventing the semiconductor wafer from warping, the metal silicide film from peeling off, and the like during the manufacturing process, and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the invention.

FIG. 2 is a plan view showing a pattern of a resist film on a wafer corresponding to FIG. 1 (b).

FIG. 3 is a sectional view showing a manufacturing process of a semiconductor device according to a second embodiment of the invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of a conventional semiconductor device.

FIG. 5 is a plan view showing a pattern of a resist film on a wafer corresponding to FIG. 4 (b).

[Explanation of symbols]

31 ... P-type semiconductor substrate, 32 ... N-type buried layer, 33 ... P-type buried layer, 34 ... N-type epitaxial layer, 35 ... P-type well region, 36 ... Element isolation oxide film, 37 ... Collector electrode extraction part , 38 ... N channel region, 39 ... P channel region, 40 ... Gate oxide film, 41 ... Polycrystalline silicon film, 4
2 ... Metal silicide film, 43 ... Resist film, 44 ... Resist mask, 45 ... Gate electrode, 52 ... Insulating film, 53 ...
BPSG film, 54 ... Metal wiring.

Claims (6)

[Claims] 1. A polycrystalline silicon film for wiring and a metal silicide film exist in a stacked state on a chip region in a semiconductor wafer surface, and the metal silicide film does not exist in a wafer peripheral region where the chip region is not formed. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, wherein the metal silicide film is any one of tungsten silicide, molybdenum silicide, and titanium silicide. 3. A step of depositing a polycrystalline silicon film on a substrate of a semiconductor wafer via a gate insulating film to diffuse impurities, a step of depositing a metal silicide film on the polycrystalline silicon film, and the metal described above. After applying the first resist film on the silicide film, the first resist film in the wafer peripheral region outside the chip region in the surface of the semiconductor wafer is removed, and the first resist film is formed on the chip region. A step of leaving it, a step of etching the first resist film as a mask to remove the metal silicide film outside the chip region around the wafer, and a pattern of a second resist film on the chip region, And a step of forming a gate electrode for a MOS transistor by using this resist film pattern as a mask. Method for producing polycrystalline silicon film and metal silicide film is present in a laminated state, the semiconductor device in the wafer peripheral region chip region is not formed, characterized in that the production of semiconductor wafers without the metal silicide layer is present. 4. A step of depositing a polycrystalline silicon film on a substrate of a semiconductor wafer via a gate insulating film to diffuse impurities, a step of depositing a metal silicide film on the polycrystalline silicon film, and the metal. After applying the first resist film on the silicide film, the step of exposing the gate electrode pattern for the MOS transistor to the chip area, and using the mask with no pattern in the wafer peripheral area outside the chip area, By exposing the first resist film outside, and performing etching using the first resist film as a mask, a gate electrode pattern is formed in the chip region, and at the same time, the metal silicide film and the polycrystal outside the chip region are formed. A step of removing the silicon film, and a polycrystalline silicon film for wiring and a chip area in the semiconductor wafer surface are provided. Metal silicide film is present in a stacked state, a method of manufacturing a semiconductor device in a wafer peripheral region chip region is not formed, characterized in that to produce a semiconductor wafer that does not present the above two membranes. 5. A step of depositing a polycrystalline silicon film on a substrate of a semiconductor wafer via a gate insulating film to diffuse impurities, a step of depositing a metal silicide film on the polycrystalline silicon film, and the metal described above. After the first resist film is applied on the silicide film, a step of exposing the gate electrode pattern for the MOS transistor to the chip area is performed, and the first resist film in the wafer peripheral area outside the chip area is used without using a mask. A step of exposing and a step of forming a gate electrode pattern in the chip region and simultaneously removing the metal silicide film and the polycrystalline silicon film outside the chip region by performing etching using the first resist film as a mask. However, a polycrystalline silicon film for wiring and a metal silicide film are stacked in the chip area on the surface of the semiconductor wafer. And, a method of manufacturing a semiconductor device in a wafer peripheral region chip region is not formed, characterized in that to produce a semiconductor wafer without the two films are present. 6. The semiconductor device according to claim 3, wherein the metal silicide film is any one of tungsten silicide, molybdenum silicide, and titanium silicide. Method.