JPH06231673A - Electron emitting element and its manufacture - Google Patents

Electron emitting element and its manufacture

Info

Publication number
JPH06231673A
JPH06231673A JP1735493A JP1735493A JPH06231673A JP H06231673 A JPH06231673 A JP H06231673A JP 1735493 A JP1735493 A JP 1735493A JP 1735493 A JP1735493 A JP 1735493A JP H06231673 A JPH06231673 A JP H06231673A
Authority
JP
Japan
Prior art keywords
emitter
electrode
substrate
electron
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1735493A
Other languages
Japanese (ja)
Inventor
Mamoru Ishizaki
守 石崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP1735493A priority Critical patent/JPH06231673A/en
Publication of JPH06231673A publication Critical patent/JPH06231673A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain electron sources and image indicating elements in a simple structure with no complex process entailed by forming emitter wiring on an emitter substrate, and concurrently forming a separation layer on the surface of a gate electrode in advance. CONSTITUTION:After a gate electrode 1 including a plurality of through holes has been made, a separation layer is formed over the surface of the electrode 1. Emitter wiring 21 is then formed, and an insulating spacer 2 is formed in an emitter substrate 20 on which an emitter electrode 21 is formed, and the electrode 1 is stuck together with the substrate 20 thereafter on which the electrode 21 and the spacer 2 are formed. Subsequently, each emitter electrode 22 in a minute projection shape is self-adjustably formed using emitter material by means of deposition. After that, the emitter material 12 adhered onto the electrode 1 by means of deposition, is peeled off via the separation layer. Thus as mentioned above, since the electrode 1 provided with the separation layer and the substrate 20 are separately manufactured, and they are stuck together so as to allow each electrode 22 in a minute projection shape to be formed thereafter, there is no need for complex processes such as one for the oblique deposition of the separation layer, so that electron emitting elements can thereby be manufactured in a comparatively simple way.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電界放出現象を利用した
電子源に関するものであり、画像表示素子、光プリン
タ、照明ランプ等に応用される電子放射素子及びその製
造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electron source utilizing the field emission phenomenon, and more particularly to an electron emitting element applied to an image display device, an optical printer, an illuminating lamp and the like and a manufacturing method thereof.

【0002】[0002]

【従来の技術】通常の状態において物体表面から電子を
取り出すためには、その物体の仕事関数に相当するエネ
ルギーを与える必要がある。これは、仕事関数分のエネ
ルギー障壁が存在するためである。そこで、上記エネル
ギー障壁を打破するために、物体表面に対して強電界を
かけると、その障壁の幅が狭くなり、トンネル現象によ
って電子が放出される。これが電界放出現象である。
2. Description of the Related Art In order to extract electrons from the surface of an object in a normal state, it is necessary to apply energy corresponding to the work function of the object. This is because there is an energy barrier for the work function. Therefore, when a strong electric field is applied to the surface of the object in order to break the energy barrier, the width of the barrier becomes narrow and electrons are emitted by the tunnel phenomenon. This is the field emission phenomenon.

【0003】電場はポアソンの方程式に支配されている
ため、突起があるとその先端部分に電子が集中する。即
ち、突起形状を用いれば、比較的低電圧で電子の電界放
出を起こすことができ、電子源として利用できる。
Since the electric field is governed by Poisson's equation, if there is a protrusion, electrons concentrate at the tip. That is, if the projection shape is used, it is possible to cause field emission of electrons at a relatively low voltage, and it can be used as an electron source.

【0004】従来、電界放出現象を利用した電子放射素
子の例としては、ジャーナル・オブ・アプライド・フィ
ズィックス第47巻12号(1976 年12月)5248 〜5263ペ
ージ(Journal of Applied Physics,Vol.47,Number12(D
ecember1976)5248〜5263に示されたものがある。
Conventionally, as an example of an electron-emitting device utilizing the field emission phenomenon, Journal of Applied Physics, Vol. 47, No. 12 (December 1976), pages 5248 to 5263 (Journal of Applied Physics, Vol. 47, Number12 (D
ecember1976) 5248-5263.

【0005】この方法では、図4(a)〜図4(c)の
ように、基板20上に形成した絶縁膜2’およびゲート
電極1に小孔1bを孔設し、図4(d)のように、斜め
蒸着方式によって剥離層11を設け、続いて図4(e)
のように、小孔1bの内部に向かって、エミッタ材料1
2として例えばMo(モリブデン)を蒸着し、小孔1b
内に円錐状のエミッタ電極22を形成する。剥離層11
上にMo蒸着によって付着したエミッタ材料12(M
o)は、剥離層11を介してゲート電極1より剥離し、
図4(f)に示すような電子放射素子を得ている。な
お、図4(g)は、電子放射素子の小孔1b内部の基板
20上に形成された円錐状のエミッタ電極22を示す斜
視図である。
In this method, as shown in FIGS. 4 (a) to 4 (c), a small hole 1b is formed in the insulating film 2'and the gate electrode 1 formed on the substrate 20, and then the small hole 1b is formed in FIG. 4 (d). As shown in Fig. 4 (e), the peeling layer 11 is provided by the oblique vapor deposition method.
The emitter material 1 toward the inside of the small hole 1b.
For example, Mo (molybdenum) is vapor-deposited as 2 and the small hole 1b is formed.
A conical emitter electrode 22 is formed inside. Release layer 11
Emitter material 12 (M
o) is peeled from the gate electrode 1 through the peeling layer 11,
An electron emitting element as shown in FIG. 4 (f) is obtained. 4 (g) is a perspective view showing the conical emitter electrode 22 formed on the substrate 20 inside the small hole 1b of the electron emitting element.

【0006】また、別の例としては特開平4−9401
2に開示されたものがある。この方法では、図5(a)
〜(c)のように、シリコン基板20上に、マスク4を
つけた状態でエッチングして、該マスク4の周囲にエッ
チング凹部1cを設け、熱酸化した後に図5(d)〜
(e)のように、エッチング凹部1cに絶縁体2’と金
属1(ゲート電極)を蒸着し、その後にマスク4を除去
し、金属1(ゲート電極)を残して絶縁体2’をエッチ
ング除去することによって、図5(f)に示すような、
マスク4によって残留する突起部分をエミッタ電極とす
る電子放射素子を得ている。
As another example, Japanese Patent Laid-Open No. 4-9401
2 are disclosed. In this method, as shown in FIG.
As shown in FIG. 5C, the silicon substrate 20 is etched with the mask 4 attached, etching recesses 1c are provided around the mask 4, and thermal oxidation is performed.
As shown in (e), the insulator 2'and the metal 1 (gate electrode) are vapor-deposited in the etching recess 1c, and then the mask 4 is removed, and the insulator 2'is removed by etching leaving the metal 1 (gate electrode). By doing so, as shown in FIG.
By the mask 4, the electron-emitting device having the protruding portion remaining as the emitter electrode is obtained.

【0007】なお前者の方法(図4(a)〜(f))で
作製した電子放射素子に関しては、これと、蛍光体を塗
布したアノード電極(陽極)とを対向させた画像表示素
子が開発されている。(Japan Display '86 512 〜515
ページ)
Regarding the electron-emitting device manufactured by the former method (FIGS. 4 (a) to 4 (f)), an image display device in which this and an anode electrode (anode) coated with a phosphor are opposed to each other has been developed. Has been done. (Japan Display '86 512 ~ 515
page)

【0008】[0008]

【発明が解決しようとする課題】しかしながら、前者の
方法では、剥離層11をゲート電極1上に蒸着により形
成する場合、該剥離層11が直接基板20上に蒸着され
ることを防ぐために、斜めに蒸着すること、後者(図5
(a)〜(f))ではマスク4を鋭角状にエッチングさ
れたシリコン上に残した状態でエッチングを停止するこ
とが必要であり、いずれも工程が複雑で難しいという欠
点があった。
However, in the former method, when the peeling layer 11 is formed on the gate electrode 1 by vapor deposition, in order to prevent the peeling layer 11 from being directly vapor deposited on the substrate 20, Vapor deposition on the latter (Fig. 5
In (a) to (f), it is necessary to stop the etching while leaving the mask 4 on the silicon etched in an acute angle, and all of them have the drawback that the process is complicated and difficult.

【0009】本発明は、このように複雑な工程を必要と
しない、単純な構造の電子源および画像表示素子を得る
ことにある。
The present invention is to obtain an electron source and an image display device having a simple structure, which does not require such complicated steps.

【0010】[0010]

【課題を解決するための手段】本発明は、貫通孔を有す
るゲート電極と、該貫通孔と対向する導電領域に電子放
出用微小突起状のエミッタ電極を有するエミッタ基板と
を、絶縁スペーサを介して貼り合わせた電子放射素子に
おいて、微小突起状のエミッタ電極を有する前記導電領
域が、エミッタ基板面に適宜なパターン状に形成されて
いることを特徴とする電子放射素子である。
According to the present invention, a gate electrode having a through hole and an emitter substrate having an electron-emitting microprojection-shaped emitter electrode in a conductive region facing the through hole are provided via an insulating spacer. In the electron-emitting device bonded by means of the above-mentioned method, the conductive region having the emitter electrodes in the form of minute protrusions is formed in an appropriate pattern on the emitter substrate surface.

【0011】また、本発明は、電子を通過させる貫通孔
を孔設し、且つ表面に剥離層を設けたゲート電極と、導
電領域を有するエミッタ基板とを、絶縁スペーサを介し
て貼り合わせた後、前記剥離層側よりエミッタ材料を貫
通孔を通して蒸着し、電子を射出させる微小突起状のエ
ミッタ電極を前記貫通孔と対向するエミッタ基板側に形
成することを特徴とする電子放射素子の製造方法であ
る。
Further, according to the present invention, a gate electrode having a through hole for allowing electrons to pass therethrough and having a release layer on the surface thereof and an emitter substrate having a conductive region are bonded together via an insulating spacer. A method of manufacturing an electron-emitting device characterized in that an emitter material is vapor-deposited from the release layer side through a through hole, and a microprojection-shaped emitter electrode for emitting electrons is formed on an emitter substrate side facing the through hole. is there.

【0012】[0012]

【実施例】本発明の電子放射素子は、図1に示されるよ
うに、複数の貫通孔1aを持つ電極1と、適宜数の絶縁
スペーサ2を介して貼り合わされているエミッタ基板2
0上に形成された適宜なパターン状のエミッタ配線21
と、該エミッタ配線21上に形成された前記貫通孔1a
と同数の微小突起状のエミッタ電極22を持つエミッタ
電極部3よりなっている。
BEST MODE FOR CARRYING OUT THE INVENTION As shown in FIG. 1, an electron-emitting device according to the present invention has an emitter substrate 2 which is bonded to an electrode 1 having a plurality of through holes 1a through an appropriate number of insulating spacers 2.
An appropriate patterned emitter wiring 21 formed on
And the through hole 1a formed on the emitter wiring 21.
The emitter electrode portion 3 has the same number of micro-projection-shaped emitter electrodes 22 as the above.

【0013】作製は、図2(a)〜(k)に示されるよ
うな工程によって行われる。まず、図2(a)〜(c)
に示すように、ゲート電極1から複数の貫通孔1aを持
つゲート電極1を作製し、続いて図2(d)ゲート電極
1表面に剥離層11を施し、図2(e)〜(g)エミッ
タ配線21を施し、図2(h)エミッタ電極21を形成
したエミッタ基板20に絶縁スペーサ2を施し、次に、
図2(i)に示すように、エミッタ電極21と絶縁スペ
ーサ2とを施したエミッタ基板20と、前記ゲート電極
1とを貼り合わせた後、図2(j)自己整合的に微小突
起状のエミッタ電極22をエミッタ材料を用いて蒸着
(真空蒸着が適当であるが、スパッタリングでも可)に
より形成し、その後、図2(k)に示すように、剥離層
11を介して蒸着によりゲート電極1上に付着したエミ
ッタ材料12を剥離して電子放射素子を形成する。
The fabrication is performed by the steps shown in FIGS. 2 (a) to 2 (k). First, FIGS. 2A to 2C
As shown in FIG. 2, a gate electrode 1 having a plurality of through holes 1a is produced from the gate electrode 1, and subsequently, a peeling layer 11 is applied to the surface of the gate electrode 1 in FIG. The emitter wiring 21 is applied, and the insulating substrate 2 is applied to the emitter substrate 20 on which the emitter electrode 21 is formed as shown in FIG.
As shown in FIG. 2I, after the emitter substrate 20 provided with the emitter electrode 21 and the insulating spacer 2 and the gate electrode 1 are bonded together, FIG. The emitter electrode 22 is formed by vapor deposition using an emitter material (vacuum vapor deposition is suitable, but sputtering is also possible), and then, as shown in FIG. 2 (k), the gate electrode 1 is vapor deposited through the peeling layer 11. The emitter material 12 deposited on the top is peeled off to form an electron-emitting device.

【0014】本発明の上記電子放射素子は、複数の貫通
孔1aを持つゲート電極1に予め剥離層11が形成され
ていることにより、斜め蒸着方式を採用しなくとも、エ
ミッタ基板20におけるエミッタ配線21の領域には、
剥離層11が付着することがなく斜め蒸着の工程が不要
となる。即ち、微小突起状のエミッタ電極22を形成し
た後に、剥離層11を除去することにより、簡単に素子
を作製することができる。
In the electron-emitting device of the present invention, since the peeling layer 11 is formed in advance on the gate electrode 1 having the plurality of through holes 1a, the emitter wiring in the emitter substrate 20 can be obtained without using the oblique vapor deposition method. In the area of 21,
Since the peeling layer 11 does not adhere, the step of oblique vapor deposition becomes unnecessary. That is, the element can be easily manufactured by removing the peeling layer 11 after forming the emitter electrode 22 in the form of minute protrusions.

【0015】こうして作製した素子において、ゲートを
基準としてエミッタに負の電圧を印加すると、エミッタ
先端から電子が射出される。その一部はゲートに直接到
達するが、大部分の電子はゲート電極1の貫通孔1aを
通過する。
In the element thus manufactured, when a negative voltage is applied to the emitter with the gate as a reference, electrons are emitted from the tip of the emitter. Some of them directly reach the gate, but most of the electrons pass through the through hole 1 a of the gate electrode 1.

【0016】[0016]

【作用】本発明の電子放射素子は、エミッタ基板20に
配線パターン状のエミッタ配線21が形成されており、
斜め蒸着方式を採用しなくとも微小突起状のエミッタ電
極22を蒸着によって比較的容易に形成できる。
In the electron emitting device of the present invention, the emitter substrate 20 is formed with the emitter wiring 21 in the form of a wiring pattern.
Even if the oblique vapor deposition method is not adopted, the minute projection-shaped emitter electrode 22 can be formed relatively easily by vapor deposition.

【0017】また、本発明の電子放射素子製造方法は、
ゲート電極1表面に事前に剥離層11を形成して製造す
るため、従来のような斜め蒸着という工程が不要とな
り、簡単に素子を形成できるという作用がある。
The method for manufacturing an electron-emitting device according to the present invention is
Since the peeling layer 11 is formed in advance on the surface of the gate electrode 1 for manufacturing, there is no need for a step of oblique vapor deposition as in the conventional case, and there is an effect that an element can be easily formed.

【0018】以下に本発明の電子放射素子及びその製造
方法の具体的実施例を説明する。 <実施例>
Specific examples of the electron-emitting device and the method for manufacturing the same according to the present invention will be described below. <Example>

【0019】まず、図2(a)〜(d)は、ゲート電極
1の作製工程である。材料としては426 合金を使用し
た。図2(a)、厚さ0.2mmのゲート電極1作製用
基板の一部を、フォトリソグラフィとウェットエッチン
グにより多段階に加工して、図2(b)に示すような厚
さ約10μm の薄肉部分を形成し、そこに図2(c)に
示すように直径約8μmの小孔状の貫通孔1aを複数個
形成した。こうして形成したゲート電極1の上面に、図
2(d)、剥離層11としてフォトレジスト(この例で
はポジ型ホトレジスト)をコートし、貫通孔1aの内部
に詰まった分や下面に回り込んだ分を下からの光照射と
現像で除去した。
First, FIGS. 2A to 2D show a manufacturing process of the gate electrode 1. As the material, 426 alloy was used. 2A, a part of the substrate for forming the gate electrode 1 having a thickness of 0.2 mm is processed in multiple steps by photolithography and wet etching to obtain a film having a thickness of about 10 μm as shown in FIG. 2B. A thin portion was formed, and a plurality of small through-holes 1a each having a diameter of about 8 μm were formed therein as shown in FIG. 2 (c). As shown in FIG. 2D, a photoresist (a positive photoresist in this example) is coated on the upper surface of the gate electrode 1 thus formed, and the amount of the photoresist clogged in the inside of the through hole 1a or wrapping around the lower surface. Was removed by light irradiation from below and development.

【0020】一方、図2(e)〜(h)は、エミッタ基
板20側の作製工程であり、まず、図2(e)に示すエ
ミッタ基板20を使用して、図2(f)のエミッタ配線
21を、図2(g)のように適宜パターン状にパターニ
ングしてエミッタ配線して、エミッタ配線21を設け、
図2(h)に示すように適宜厚さの絶縁スペーサ2の設
置を行なう。
On the other hand, FIGS. 2 (e) to 2 (h) are manufacturing steps on the side of the emitter substrate 20. First, using the emitter substrate 20 shown in FIG. 2 (e), the emitter of FIG. The wiring 21 is patterned into an appropriate pattern as shown in FIG. 2G to form an emitter wiring, and the emitter wiring 21 is provided.
As shown in FIG. 2H, the insulating spacer 2 having an appropriate thickness is installed.

【0021】まず、図2(e)ガラス製のエミッタ基板
20上に、図2(f)、図2(g)に示すように、蒸着
とフォトリソグラフィ、エッチングでエミッタ配線21
を形成した。エミッタ配線21にはタングステンを用
い、厚さ0.2μmとした。
First, as shown in FIGS. 2 (f) and 2 (g), the emitter wiring 21 is formed on the glass-made emitter substrate 20 shown in FIG. 2 (e) by vapor deposition, photolithography and etching.
Was formed. The emitter wiring 21 is made of tungsten and has a thickness of 0.2 μm.

【0022】次に、図2(h)絶縁スペーサ2を設け
た。絶縁スペーサ2にはポリイミド樹脂が用いられ、高
さ約20μmとした。具体的には、まず感光性のポリア
ミック酸溶液(加熱処理によってポリイミド樹脂による
絶縁スペーサ2を形成するためのポジ型感光性樹脂溶
液)をスピンコートし、90℃で20分のプリベイクを
行った。そして、フォトマスクを介して紫外線を露光
し、現像後、120℃で10分のポストベイク、さら
に、高真空中で380℃、1時間の硬化処理を行った。
このように、リソグラフィ技術を使用することにより、
微細なスペーサ2を形成できる。
Next, the insulating spacer 2 shown in FIG. 2 (h) was provided. The insulating spacer 2 is made of polyimide resin and has a height of about 20 μm. Specifically, first, a photosensitive polyamic acid solution (a positive photosensitive resin solution for forming the insulating spacer 2 made of a polyimide resin by heat treatment) was spin-coated, and prebaking was performed at 90 ° C. for 20 minutes. Then, it was exposed to ultraviolet rays through a photomask, developed, and post-baked at 120 ° C. for 10 minutes, and further cured at 380 ° C. for 1 hour in a high vacuum.
Thus, by using lithographic techniques,
The fine spacer 2 can be formed.

【0023】そして、図2(i)に示すように、作製し
たゲート電極1と基板20を対向させて重ね、周囲の一
部をエポキシ系接着剤(又はポリイミド系樹脂接着剤
等)で固定することにより、貼り合わせを行った。
Then, as shown in FIG. 2 (i), the gate electrode 1 and the substrate 20 thus produced are opposed to each other and overlapped, and a part of the periphery is fixed with an epoxy adhesive (or a polyimide resin adhesive or the like). By doing so, the bonding was performed.

【0024】貼り合わせ完了後、図2(j)エミッタ材
料12を真空蒸着した。なお本実施例においてはエミッ
タ材料12としてはタングステンを用いた。図2(j)
に示すように、ゲート電極1の貫通孔1aは蒸着が進む
につれてエミッタ材料12、即ちタングステンの付着に
よって狭くなり、やがて完全に塞がれる。こうして、貫
通孔1aの下には、円錐形で高さ約15μmの微小突起
状のエミッタ電極22が形成される。
After the completion of the bonding, the emitter material 12 shown in FIG. 2 (j) was vacuum-deposited. In this embodiment, tungsten is used as the emitter material 12. Figure 2 (j)
As shown in FIG. 5, the through hole 1a of the gate electrode 1 becomes narrower due to the deposition of the emitter material 12, that is, tungsten as the vapor deposition progresses, and is eventually completely blocked. In this way, the conical cone-shaped emitter electrode 22 having a height of about 15 μm is formed under the through hole 1a.

【0025】この状態で剥離層11であるレジストを有
機溶媒で除去することにより、ゲート電極1上のタング
ステンが除かれ、電子放射素子が完成した。
In this state, the resist as the peeling layer 11 was removed with an organic solvent to remove the tungsten on the gate electrode 1 to complete the electron-emitting device.

【0026】基板20には、ガラスに限らず、Si、G
aAs基板等を用いてもよい。その場合、エミッタ配線
21は基板上に設けてもよいし、基板中にイオン注入等
で導電領域を形成してもよい。また、ゲート電極1に
は、他の金属を用いることもできる。ただし、基板20
とゲート電極1との熱膨張係数差が小さいことが重要で
ある。絶縁スペーサ2には、ポリイミド以外の絶縁体、
例えばSiO2 なども使用できる。
The substrate 20 is not limited to glass, but Si, G
An aAs substrate or the like may be used. In that case, the emitter wiring 21 may be provided on the substrate, or a conductive region may be formed in the substrate by ion implantation or the like. Also, other metals can be used for the gate electrode 1. However, the substrate 20
It is important that the difference in thermal expansion coefficient between the gate electrode 1 and the gate electrode 1 is small. The insulating spacer 2 includes an insulator other than polyimide,
For example, SiO 2 or the like can be used.

【0027】また、エミッタ材料にはW(タングステ
ン)、Mo(モリブデン)、Ta(タンタル)等の金
属、LaB6 等のホウ化物、TiC等の炭化物、TiN
等の窒化物なども使用できる。剥離層11には、レジス
ト以外の材料も使用できるが、絶縁スペーサを傷めずに
除去できるようなエッチャントの選択が必要である。
The emitter material is a metal such as W (tungsten), Mo (molybdenum) or Ta (tantalum), a boride such as LaB 6 or the like, a carbide such as TiC or TiN.
It is also possible to use a nitride such as. A material other than a resist can be used for the peeling layer 11, but it is necessary to select an etchant that can remove the insulating spacer without damaging it.

【0028】また本発明は、請求項に記載した電子放射
素子の構造とその電子放射素子の製造方法であって、こ
れら請求項に記載する発明を逸脱しない範囲であれば上
記材料に限定されるものではない。
Further, the present invention is a structure of an electron-emitting device described in the claims and a method of manufacturing the electron-emitting device, and is limited to the above materials as long as it does not deviate from the invention described in these claims. Not a thing.

【0029】さらに、こうして作製した素子と、透明電
極(アノード電極)と電子線励起の蛍光体とを具備する
透明対向基板とを組み合わせることにより、発光素子や
画像表示素子を作製できることは言うまでもない。
Further, it goes without saying that a light emitting device or an image display device can be manufactured by combining the device thus manufactured with a transparent counter substrate provided with a transparent electrode (anode electrode) and an electron beam excited phosphor.

【0030】本発明の電子放射素子を使用する画像表示
のためのひとつの方法としては、エミッタ、ゲート、ア
ノードの少なくとも2つをX−Yマトリクス駆動にする
ことが挙げられる。
One method for displaying an image using the electron-emitting device of the present invention is to drive at least two of an emitter, a gate and an anode by XY matrix driving.

【0031】図3は、ゲート電極1とエミッタ配線21
とをストライプパターン状に形成して、それを互いに直
交方向に配置して貼り合わせた画像表示用パネルに使用
する電子放射素子の一例を示す模式図であり、2は絶縁
スペーサである。なお、同図3中、31は、ゲート電極
1を貼り合わせたエミッタ基板20上に重ね合わせるカ
ラー表示用のストライプパターン状に形成されたカラー
発色蛍光体(各発色パターンR,G,B)を備えた対向
電極基板30を示す。
FIG. 3 shows the gate electrode 1 and the emitter wiring 21.
FIG. 2 is a schematic view showing an example of an electron-emitting element used in an image display panel in which and are formed in a stripe pattern, and are arranged in a direction orthogonal to each other and bonded to each other, and 2 is an insulating spacer. In FIG. 3, reference numeral 31 denotes a color-emitting phosphor (each color-emitting pattern R, G, B) formed in a stripe pattern for color display, which is superposed on the emitter substrate 20 to which the gate electrode 1 is attached. The counter electrode substrate 30 provided is shown.

【0032】本発明においては、エミッタ配線21をス
トライプパターンにする場合、あるいはその他のパター
ンにする場合でも、ゲート電極1に施される貫通孔1a
の形成領域は、必ずしもエミッタ配線21領域真上に対
向するゲート電極1領域にのみ限定する必要はなく、例
えば配線パターン状のエミッタ配線21領域より広め
に、あるいはゲート電極1全面領域に亘って形成しても
よい。エミッタ配線21上にないエミッタ突起22は無
効になるだけであるので位置決めが容易になる。
In the present invention, the through hole 1a formed in the gate electrode 1 is formed even when the emitter wiring 21 has a stripe pattern or other patterns.
It is not always necessary to limit the formation region of the gate electrode 1 region right above the emitter wiring 21 region, for example, to be wider than the emitter pattern 21 region of the wiring pattern or over the entire surface of the gate electrode 1. You may. Since the emitter protrusion 22 not on the emitter wiring 21 is only invalidated, the positioning becomes easy.

【0033】ゲート電極1をストライプ構造にする場合
には、各々ストライプの互いの平行が維持できるよう
に、そのストライプの両端に繋ぎ部分を設けて互いのス
トライプを繋げた状態でゲート電極1を形成し、エミッ
タ基板20側に貼り合わせた後に、その繋ぎ部分をカッ
ティング等により除去すればよい。ただし、ストライプ
間にも剥離層を付けておくなどして、貼り合わせた後に
エミッタ材料12にてエミッタ電極22を蒸着する場合
の余計なエミッタ材料12の侵入を防ぐ必要がある。
When the gate electrode 1 has a stripe structure, the gate electrode 1 is formed in a state where the stripes are connected to each other by providing connecting portions at both ends of the stripes so that the stripes can be kept parallel to each other. Then, after bonding to the emitter substrate 20 side, the connecting portion may be removed by cutting or the like. However, it is necessary to prevent the extra intrusion of the emitter material 12 when the emitter electrode 22 is vapor-deposited with the emitter material 12 after the attachment by attaching a peeling layer also between the stripes.

【0034】[0034]

【発明の効果】本発明の電子放射素子は、剥離層を具備
するゲート電極と、エミッタ基板を別々に作製し、貼り
合わせた後に微小突起状のエミッタ電極を形成するた
め、剥離層の斜め蒸着という複雑な工程を必要とせず、
電子放射素子を比較的簡単に作製できるという効果があ
る。
According to the electron-emitting device of the present invention, the gate electrode having the peeling layer and the emitter substrate are separately manufactured, and the microprojection-shaped emitter electrodes are formed after bonding them together. Without the complicated process of
There is an effect that the electron-emitting device can be manufactured relatively easily.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の電子放射素子の構造を示す実施例の説
明図である。
FIG. 1 is an explanatory diagram of an example showing the structure of an electron-emitting device of the present invention.

【図2】本発明の電子放射素子の製造工程を示す説明図
である。
FIG. 2 is an explanatory view showing a manufacturing process of the electron-emitting device of the present invention.

【図3】本発明の電子放射素子を用いたカラー画像表示
パネルの概要斜視図である。
FIG. 3 is a schematic perspective view of a color image display panel using the electron emitting element of the present invention.

【図4】従来の電子放射素子の製造工程の一例を示す説
明図である。
FIG. 4 is an explanatory diagram showing an example of a manufacturing process of a conventional electron-emitting device.

【図5】従来の電子放射素子の製造工程の他の一例を示
す説明図である。
FIG. 5 is an explanatory diagram showing another example of a conventional manufacturing process of an electron-emitting device.

【符合の説明】[Explanation of sign]

1 …ゲート電極 1a…貫通孔 1b…小孔 1c…
エッチング凹部 2 …絶縁スペーサ 2’…絶縁層 3 …エミッタ電極部 4…マスク層 11 …剥離層 12…エミッタ材料 20 …エミッタ基板 21 …エミッタ配線 22
…エミッタ電極 30 …対向電極基板 31 …蛍光体
1 ... Gate electrode 1a ... Through hole 1b ... Small hole 1c ...
Etching concave portion 2 ... Insulating spacer 2 '... Insulating layer 3 ... Emitter electrode portion 4 ... Mask layer 11 ... Stripping layer 12 ... Emitter material 20 ... Emitter substrate 21 ... Emitter wiring 22
... Emitter electrode 30 ... Counter electrode substrate 31 ... Phosphor

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】貫通孔を有するゲート電極と該貫通孔と対
向する導電領域に電子放出用微小突起状のエミッタ電極
を有するエミッタ基板とを、絶縁スペーサを介して貼り
合わせた電子放射素子において、微小突起状のエミッタ
電極を有する前記導電領域がエミッタ基板面に適宜なパ
ターン状に形成されていることを特徴とする電子放射素
子。
1. An electron-emitting device in which a gate electrode having a through hole and an emitter substrate having an electron-emitting microprojection-shaped emitter electrode in a conductive region facing the through hole are bonded together via an insulating spacer, An electron-emitting device characterized in that the conductive region having minute projection-shaped emitter electrodes is formed in an appropriate pattern on the emitter substrate surface.
【請求項2】電子を通過させる貫通孔を孔設し、且つ表
面に剥離層を設けたゲート電極と、導電領域を有するエ
ミッタ基板とを、絶縁スペーサを介して貼り合わせた
後、前記剥離層側よりエミッタ材料を貫通孔を通して蒸
着し、電子を射出させる微小突起状のエミッタ電極を前
記貫通孔と対向するエミッタ基板側に形成することを特
徴とする電子放射素子の製造方法。
2. A peeling layer is provided after a gate electrode having a through hole for allowing electrons to pass therethrough and having a peeling layer provided on the surface thereof and an emitter substrate having a conductive region are bonded together via an insulating spacer. A method of manufacturing an electron-emitting device, characterized in that an emitter material is vapor-deposited from the side through a through hole, and a minute projection-shaped emitter electrode for emitting electrons is formed on the side of the emitter substrate facing the through hole.
JP1735493A 1993-02-04 1993-02-04 Electron emitting element and its manufacture Pending JPH06231673A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1735493A JPH06231673A (en) 1993-02-04 1993-02-04 Electron emitting element and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1735493A JPH06231673A (en) 1993-02-04 1993-02-04 Electron emitting element and its manufacture

Publications (1)

Publication Number Publication Date
JPH06231673A true JPH06231673A (en) 1994-08-19

Family

ID=11941718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1735493A Pending JPH06231673A (en) 1993-02-04 1993-02-04 Electron emitting element and its manufacture

Country Status (1)

Country Link
JP (1) JPH06231673A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100545917B1 (en) * 2001-05-09 2006-01-25 가부시키가이샤 히타치세이사쿠쇼 Display

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100545917B1 (en) * 2001-05-09 2006-01-25 가부시키가이샤 히타치세이사쿠쇼 Display

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