JP2940360B2 - Method of manufacturing field emission device array - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission cathode known as a cold cathode, and particularly to a manufacturing method useful for forming a large number of field emission element arrays on a substrate of a predetermined size. It is about.

[0002]

2. Description of the Related Art An electric field applied to a metal or semiconductor surface is 10
^At about ⁹ [V / m], electrons pass through the barrier due to the tunnel effect, and electrons are emitted in a vacuum even at room temperature. This is called field emission, and a cathode that emits electrons based on this principle is called a field emission cathode (hereinafter referred to as FEC).
It is called). In recent years, it has become possible to make use of semiconductor processing technology to produce a surface-emission type field emission cathode composed of micron-sized field emission cathodes. Irradiation of electrons emitted from the respective emitters onto a phosphor screen is expected as an element constituting a flat display device or various electronic devices.

One method of manufacturing such a field emission device is a rotary oblique deposition method developed by Spindt (US Pat. No. 37).
89471), and another method is based on a selective etching method for a silicon single crystal plate. The former has a feature that the cathode chip material can be almost freely selected, and the latter has a feature that the current semiconductor fine processing can be applied as it is.

[0004] Hereinafter, F corresponding to the SPINDT method will be described.
An EC manufacturing method (Japanese Patent Laid-Open No. 1-154426) will be described with reference to FIG. First, as shown in FIG. 2A, a thin film conductor layer 101 serving as a cathode electrode is formed on a substrate 100 made of glass or the like by vapor deposition, and further, Si doped with impurities is formed thereon. Resistance layer 102
Is formed, and the insulating layer 103 is formed of SiO ₂ . Then, Nb to be the gate electrode layer 104 is deposited thereon. After the photoresist layer 111 is applied on the gate electrode layer 104, which is the outermost surface of the laminated substrate, the resist is patterned by a photolithography method using a mask 112. As a result, as shown in FIG.
An opening pattern is formed on the substrate. The diameter of this opening is about 1μ
m.

Next, reactive ion etching (R) is performed using a gas such as SF ₆ from the direction in which the resist is applied.
An opening similar to the resist pattern is formed in the gate electrode layer 104 by performing anisotropic etching in IE). Next, this laminated substrate is buffered hydrofluoric acid (BHF).
The hole 114 is formed by immersing the insulating layer 103 in an etching solution such as the above and isotropically etching the portion of the insulating layer 103 (C). Then, as shown in FIG. 1F, the entire laminated substrate P is supported by an axis Q, and the rotation of the axis Q is performed to perform oblique deposition of Al as the release layer 105 from below.
When oblique deposition is performed in this manner, Al is not deposited in the holes 114, and the release layer 105 can be selectively formed only on the surface of the gate electrode layer 104.

Next, when Mo as an emitter material is deposited on the hole 114 side of such a substrate by forward evaporation, as shown in FIG.
At the same time as the vapor deposition on the four bottom sides, the emitter material layer 106 is deposited on the release layer 105. At the same time as the opening is closed by Mo deposited on the release layer 105, the cone-shaped emitter 11 is placed on the resistance layer 102.
5 are formed. After that, the substrate is immersed in phosphoric acid which is a solution of the release layer, whereby the release layer on the gate electrode layer 104 and the emitter material layer 106 are removed. As a result, an FEC having a shape as shown in FIG.

As shown in FIG. 1, the FEC manufactured by the Spindt method has a cone-shaped emitter 115 and a gate electrode layer 1.
Since the distance to 04 can be submicron,
By applying a voltage of only several tens of volts between the emitter 115 and the gate electrode layer 104, electrons can be emitted from the emitter 115. Therefore,
As shown in FIG. 3, an anode substrate 116 on which a fluorescent material is attached is disposed above a substrate on which a large number of the FECs are formed in an array, and when the voltages V _GE and _VA are applied, the emission is performed. The fluorescent material can be caused to emit light by the electrons, so that a display device can be obtained.

[0008]

By the way, in the structure of the field emission cathode device as described above, for example, it is necessary to form tens of millions of cone-shaped emitters at intervals of several microns on one display panel. Al but the multilayer substrate P as described above were placed in an oblique direction with respect to the heating chamber K for deposition as shown in FIG. 2 (f) to form a release layer, while rotating the laminate substrate P Alternatively, Ni is deposited to form a release layer. However, in this oblique deposition, since the distance between the substrate and the heating tank is different in each part of the substrate, it is extremely difficult to perform the deposition with a uniform thickness. The part and the end are different.
Therefore, when Mo or the like is subsequently vapor-deposited to form a cone-shaped emitter, the shape and structure of each emitter become non-uniform, and, for example, when applied to a display device, there is a problem that display unevenness occurs.

In addition, the oblique vapor deposition has a weaker adhesive force than the normal vapor deposition, and peels off from the peeling layer due to the stress inside the emitter layer during the vapor deposition for forming the emitter, which hinders the normal formation of the emitter. The problem arises. Also,
In the above-described method, a space where an emitter is formed in an insulating layer is formed by wet etching, but there is a problem that the overhang of the gate electrode layer is increased by this wet etching. In particular, when an FEC having a triode structure is manufactured by the above-described manufacturing method, another insulating layer 107 is provided on the conventional gate electrode layer 104 as shown in FIG. Two gate electrodes 108 are stacked to form a cone-shaped emitter 115 by the above-described manufacturing process. In this case, the insulating layer 10 is formed.
3, the time required for wet etching for forming the hole 114 by etching the insulating layer and the gate electrode becomes longer. Then, this etching also widens the etching of the hole 114 in the horizontal direction, and in particular, the overhang (t) of the second gate electrode 108 becomes longer.

By the way, the second gate electrode 108 has a function of converging electrons extracted from the emitter, and a voltage close to the emitter electrode is applied. The second gate electrode 108 hangs down to the emitter side due to an electrostatic attraction due to a potential difference between the second gate electrode 104 and the first gate electrode 104, which degrades the field emission characteristics and mechanically reduces the strength of the second gate electrode 108. And a slight shock (vibration)
As a result, the tip of the second gate electrode 108 may sag, causing various problems in terms of stability.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and comprises at least a cathode layer, a resistive layer, an insulating layer, and a gate electrode layer formed on at least a substrate. A resist layer is formed on the surface of the laminated substrate with respect to the formed laminated substrate, and the surface of the resist layer is subjected to a surface hardening treatment with monochrome benzene, and then a predetermined mask pattern is formed by photolithography. Step, and after forming a release layer and a mask layer by sequential vapor deposition from above the resist pattern obtained by this photolithography method, the substrate is immersed in a resist release liquid, and a part of the release layer and the mask layer A second step of removing the resist from the resist layer and performing anisotropic etching by reactive ion etching (RIE) on portions of the insulating layer not masked by the mask layer Includes a third step of holes formed, slightly widened by isotropic etching hole formed in the above step, a fourth step for making the overhang into the hole of the gate electrode. Thereafter, an emitter electrode material is positively deposited on the surface of the substrate to form a cone-shaped emitter electrode in the hole, and the release layer is removed to form a field emission element array. is there. When the insulating layer and the gate electrode layer have a two-layer structure, the above manufacturing method is particularly effective.

[0012]

According to the present invention, as described in the above-mentioned manufacturing method, after a resist layer is applied on the gate layer which is the outermost surface of the substrate, the resist surface is hardened with monochlorobenzene, and then the photolithography method is applied. Since the resist is patterned in this manner, the upper side surface of the remaining resist layer can be formed at an acute angle. Therefore, when the release layer and the mask layer are deposited in this state, the deposited film adhered to the upper portion of the resist at the time of removing the resist is finely removed, and the FEC
Defective formation can be prevented. In addition, as described above, the present invention eliminates oblique deposition of a release layer, which has been conventionally performed, and provides a RI layer made of Al or the like on the upper surface of the release layer.
An E mask is provided. When performing anisotropic etching with a gas such as SF ₆ or CHF ₃ , the Al mask has a higher RIE selectivity (etching rate of gate and insulating layer / etching rate of RIE mask) than using a resist mask. Big enough. In particular, in a three-electrode FEC, a hole for providing a cone-shaped emitter can be accurately etched, and as a result, the step of depositing the emitter can be performed accurately. Further, by adapting such a manufacturing method to the FEC having a three-pole structure, it is easy to control the protrusion of the second gate electrode to have a predetermined size.

[0013]

FIG. 1 is an explanatory view when the process of manufacturing an FEC of the present invention is applied to a cathode array having a three-electrode structure, and the laminated substrates are processed in the order of a, b, c, d. Is molded. That is, as in the case of forming a conventional FEC substrate, a thin film conductor layer 101 of a cathode is provided on a glass substrate 100 by sputtering a refractory metal material such as Nb, and P or B Layer 102 such as amorphous Si doped with
And the like. Further, a first insulating layer 103 is formed thereon by depositing SiO ₂ to a thickness of about 1 μm. On the first insulating layer 103, a first gate electrode layer 104 is formed. The first gate electrode layer 104 is made of Ti, C
It is formed of a high melting point metal such as r, Nb, and Mo. In the embodiment of the present invention, Nb is formed to a thickness of about 0.4 μm by sputtering. Then, a second insulating layer 107 is formed of SiO ₂ on the first gate electrode layer 104 in the same manner as the first insulating layer 103, and a second gate electrode layer 108 is formed of the first gate electrode. N same as layer 104
A film is formed of the material b.

The laminated substrate is provided with a positive photoresist layer 111 on its surface. Next, the surface of the resist is cured by dipping the resist layer in a monochlorobenzene solution. Then, a predetermined mask pattern is formed by photolithography. That is, a photomask 112 formed so that light is not irradiated to a region where the emitter electrode is provided is provided over the substrate. The resist layer 111 is exposed to ultraviolet light through the photomask 112 and developed, thereby leaving a part 120 (referred to as a resist island 120) of the resist layer as shown in FIG. 1B. Due to the effect of the surface hardening treatment with monochlorobenzene, this resist island is tapered such that the upper side surface of the island has an acute angle θ as shown in FIG. Therefore, a step can be formed when a release layer is deposited on the surface of the laminated substrate in the next step.

That is, as shown in FIG. 1C, first, a release layer 121 formed by depositing Ni by vapor deposition.
And a mask layer 1 for RIE made of Al thereon.
When the film 22 is formed, it can be a layer that is not continuous at the above-described resist island 120 portion and the flat surface portion. Therefore, in the subsequent steps, the resist island 120
Is removed by a dedicated stripper, the resist island 120 is removed.
And the release layer 121 and the RIE mask layer 122 adhered to the upper surface thereof are clearly separated from the release layer 121 and the RIE mask layer 122 formed on the substrate surface. As shown, a hole 123 is formed at the position where the emitter electrode is formed on the surface of the substrate.

After that, anisotropic etching is performed from the hole 123 by RIE using a combination of SF ₆ gas and CHF ₃ gas to form the second gate electrode layer 108 and the second insulating layer 1.
07, the first gate electrode layer 104, the first insulating layer 1
03 is anisotropically etched to form a hole 124. The formation of the hole 124 is based on the RIE selectivity of Al which is the RIE mask layer 122 (etching rate of gate and insulating layer / etching rate of RIE mask).
Is sufficiently large, Al acts as a mask, and the hole 124 can be formed. In the formation of the hole 124, the anisotropic etching is positive just before the resistance layer 102
Since it is difficult to reliably stop the operation, the process ends when the first insulating layer 103 remains on the resistance layer 102 by about 0.1 μm, and the state shown in FIG.

Next, using buffered hydrofluoric acid (BHF), the first insulating layer 103 and the second
Is wet-etched. Then, etching is performed so that the resistive layer 102 is exposed and the first gate electrode layer 104 and the second gate electrode layer 108 are slightly protruded as shown in FIG. Further, since Al has a property of dissolving in BHF, the mask layer (Al) 1 for RIE is simultaneously formed in the above steps.
22 also dissolves, and the release layer (Ni) 121 is exposed to the upper surface. From this state, the conventional emitter electrode forming method is applied .

That is, as described with reference to FIG. 2, the emitter material layer 106 such as Mo is deposited on the release layer 121. Then, this emitter material is deposited on the bottom surface of the hole 124, and a cone-shaped emitter 115 is formed on the resistance layer 102.
Is formed. (G) After that, the second gate electrode layer 10
When the peeling layer 121 and the emitter material layer 106 on the substrate 8 are both removed using a technique such as anodic oxidation, an FEC having a two-layer structure is obtained as shown in FIG.

In the above embodiment, the field emission cathode having a two-layer structure has been described. However, in the laminated substrate shown in FIG. 1A, a second insulating layer 107 and a second gate electrode layer 108 are formed. When a similar process is performed in a state where no operation is performed, FIG.
It will be easily understood that a field emission cathode having a single layer structure can be formed as shown in FIG.

[0020]

As described above, the method of manufacturing a field emission device array according to the present invention comprises forming a peeling layer for removing an emitter material layer without using oblique vapor deposition which has been conventionally used. The release layer is formed by forward evaporation in which evaporation is performed from a direction. As a result, a highly uniform release layer can be formed in the substrate, the adhesion of the release layer to the substrate side also increases, and a defect such as separation due to internal stress of the deposited film during the deposition of the emitter material layer is caused. Occurrence can be prevented. Therefore, the cone-shaped electrode forming the emitter can be spread over a large area with better reproducibility and uniformity.
There is an advantage that it can be formed accurately.

In the present invention, Al is used as a mask for RIE. RIE selectivity of Al (etching rate of gate and insulating layer / etching rate of RIE mask)
Is sufficiently larger than the resist. In particular, a two-layer FE
In C, when forming a hole for accommodating a cone-shaped emitter, it is possible to perform anisotropic etching to such an extent that the first insulating layer is slightly left by utilizing the high selectivity. This prevents the gate electrode from drooping into the hole or bending since the overhang of the gate electrode can be minimized as compared with the case where only the wet process using BHF is used to form the hole. And the yield at the time of manufacturing the field emission element array can be improved.

[Brief description of the drawings]

FIG. 1 is a process chart showing a method for manufacturing an FEC array of the present invention.

FIG. 2 is an explanatory view of manufacturing a conventional Spindt-type FEC.

FIG. 3 is an explanatory diagram of a display device using an FEC array.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Substrate 101 Thin film conductor layer 102 Resistive layer 103 First insulating layer 104 First gate electrode layer 107 Second insulating layer 108 Second gate electrode layer 121 Release layer (Ni) 122 RIE mask layer (Al)

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Waka Otsu 629 Oshiba, Mobara-shi, Chiba Futaba Electronics Co., Ltd. (72) Inventor Masateru Taniguchi 629 Oshiba, Mobara-shi, Chiba Futaba Electronics Co., Ltd. (56) References JP-A-4-196026 (JP, A) JP-A-4-506280 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01J 9/02

Claims (3)

(57) [Claims] 1. A resist layer is formed on a surface of a laminated substrate on which at least a cathode layer, a resistance layer, an insulating layer, and a gate electrode layer are sequentially formed on the substrate, and a surface of the resist layer is formed. A first step of patterning the resist into a predetermined shape by photolithography after the surface is hardened with monochlorobenzene, and a separation layer and a mask layer are sequentially deposited from above the resist pattern obtained by this photolithography A second step in which the substrate is immersed in a resist stripping solution, and the stripping layer on the resist layer and the mask layer are removed from the resist layer; A third step of forming a hole by performing anisotropic etching by ion etching, and the same direction in the hole formed in the above step. A fourth step in which the gate electrode is slightly expanded by reactive etching to form a protrusion of the gate electrode into the hole, and then, a positive electrode material is deposited on the surface of the substrate to form a cone-shaped emitter electrode in the hole. And a method of manufacturing a field emission device array, comprising: removing the release layer. 2. The method according to claim 1, wherein the insulating layer and the gate electrode layer have a two-layer structure. 3. The method according to claim 2, wherein the third step is completed while leaving a lower insulating layer slightly.