JPH06231102A - High speed control device based upon learning - Google Patents

Abstract

PURPOSE:To provide a high speed control device based upon learning which can attain high speed control. CONSTITUTION:In each change in a phenomenon, the contents of a status decoder 21 are stored, and when the same status as the decoder 21 is generated again, a memory address 26 is set up to a selected state '1'. When the same status did not exist in the past (a signal 11 is not generated), an output memory 24 also stores the contents of an output register 24 in an address corresponding to a memory address stored in a status memory 22. When the status stored in the memory 22 is generated again, a corresponding address in memory addresses 26 is turned to a selected state '1' and its corresponding data stored in an output memory 23 is loaded to an output register 24 and outputted to a controlled system 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed control device based on learning using a microcomputer.

[0002]

2. Description of the Related Art Conventionally, in a device using a microcomputer as a controller, the change is judged in accordance with the change of the external input state and the internal register state (timer etc.), and the required output is calculated. , The output is changed to control the entire system.

[0003]

Therefore, the CPU is always used.
It requires calculation for external state determination and output by
The control speed is the product of the number of program steps executing this series of programs and the speed of the CPU. In this method, when trying to increase the control speed, there is only a method of changing the program to reduce the number of steps or increasing the processing speed of the CPU. Even if the former method (reduction of the number of steps) is small, the minimum number of items that must be processed is limited, and it depends on the ability of the programmer. The latter method (enhancement of CPU speed) depends on microcomputer circuit design technology and LSI process technology, and is advancing day and night. I can't expect that. That is, even if both methods are taken into consideration, a significant improvement in control speed cannot be expected for the time being.

However, in recent years, it has been desired to improve the control speed by controlling the communication signal between systems, the audio signal, and further the video signal from the mechanism. In addition, it is also desired to improve the control speed due to the large scale and complexity of the controlled system.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a learning-based high-speed control device which enables high-speed control.

[0006]

A high-speed control apparatus according to the learning of the present invention is a CPU, a memory for accumulating past input states and output states, and a current input state and the past input state, It is characterized in that the CPU is provided with means for making the output state in the memory a control output without calculating the output state by the CPU.

[0007]

Operation: The CPU calculates in the past for a specific input state,
The output state after the output processing is stored in the memory together with the input state. When the same input state exists in the memory with respect to the new input state, the CPU does not perform the calculation and the output state in the memory is used as the control output. If the same input state does not exist in the memory, the CPU calculates the output state and uses it as the control output, and stores the input state and the output state in the memory.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described in detail with reference to the drawings. 2 shows a system configuration diagram of the present invention, FIG. 1 shows an example of the hardware configuration of a dedicated IC with a built-in memory, and FIG. 3 shows a flowchart executed by the microcomputer side.

FIG. 2 is a system configuration diagram of the high speed control device. The high-speed control device of this embodiment comprises a microcomputer 1, which has conventionally controlled a controlled system, a dedicated IC 2 with a built-in memory, and a control system changeover switch 3. Data is exchanged between the microcomputer 1 and the dedicated IC 2 with a built-in memory by the communication means 5 and 6. Further, the dedicated IC 2 with built-in memory informs through the signal 11 whether or not the data designated by the microcomputer is stored in the dedicated IC with built-in memory. Reference numeral 4 is a controlled system, which is a system to be controlled by the system of the present invention. The controlled system 4 is controlled by a control output 8 by a microcomputer or a control output 9 of a dedicated IC with a built-in memory, and its switching is performed by a switch 3 by a switching signal 7 from the microcomputer. Here, the input signal 10 from the controlled system 4 is given to the microcomputer.

FIG. 1 shows the hardware configuration of a dedicated IC with a built-in memory.

In the figure, reference numeral 20 denotes a communication unit, which performs data communication with the microcomputer and reception 5 and 6 of commands from the microcomputer. Reference numeral 21 denotes a state decoder, which decodes and holds the register of the microcomputer having a factor such as an input state, an output state, and a register state that requires a change in output. For example, an input register, an output register, a timer register, an S10 register and the like of the microcomputer can be cited. Reference numeral 22 denotes a state memory, which is composed of an array of memory cells 25 and is an integral multiple of the bit length of the state decoder 21. If the same state does not exist in the past (when the signal 11 does not occur), a command from the microcomputer is given. Due to this, every time the phenomenon changes, the state decoder 21
If the same state as the state decoder 21 occurs again, the memory address 26 is set to the select state "1". The output memory 23 has the same configuration as the state memory 22, but the configuration is an integral multiple of the bit length of the output register 24. Also, this output memory 24
Also, when the same state does not exist in the past (when the signal 11 does not occur), the contents of the output register 24 are stored in the corresponding address of the memory address stored in the state memory 22 according to the instruction of the microcomputer each time the phenomenon changes. Remember. Next, when the state stored in the state memory 22 occurs again, the corresponding one of the memory addresses 26 becomes the select state "1", the corresponding data of the output memory 23 is loaded into the output register 24, and Is output to. Further, reference numeral 24 is an output register, and the data written here is output through 9 and this data is transmitted to the communication unit 2
Sent from 0 to 6 to the microcomputer.
In the case of a phenomenon that is not stored in the state memory 22 (a phenomenon that has not been experienced in the past), none of the memory addresses 26 is selected, the signal 11 becomes “0”, and the system has never experienced this phenomenon in the past. Acknowledge things to the microcomputer. Here, 32 is a controller that controls all of these operations, and the communication unit 20
34, 3 in response to the command 33 from the microcomputer received in
Each component is controlled by 0 and 31. Reference numeral 35 denotes an internal data bus for exchanging data in the memory built-in dedicated IC.

FIG. 3 shows an operation flowchart of the microcomputer that executes the above-described series of steps. In step S30, the initial state is set. Step S
At 31, test if the condition has changed. If it does not change, the process proceeds to step S32 and waits. That is, until the state changes, the WAIT routine is cycled and in the standby state. If the state has changed (change of input terminal state, change of timer and registers such as SIO), the process proceeds to step S33. In step S33, the changed contents are transmitted to the memory built-in dedicated IC. In step 34, the dedicated IC with a built-in memory receives this data and determines whether the same phenomenon has existed in the past (whether the same data exists in the state memory 22). That is, when the signal 11 in FIG. 1 is "0", it is not in the past and is "1".
The time is in the past. The microcomputer receives this signal 11, and if it is present in the past, step S35.
In the above, the control system is immediately switched from the microcomputer output to the output of the dedicated IC with built-in memory without performing the judgment and calculation by the CPU. After this, step S36
In step 3, the dedicated IC with built-in memory is instructed to transmit the output data and the register contents to the microcomputer side.
Further, in step S37, this data is received,
In step S38, the output of the microcomputer and the register are rewritten according to this data. In step S39, the control system is returned from the dedicated IC with a built-in memory to the microcomputer side, and then in step S3 again.
At 2, the WAIT state is returned to.

On the other hand, if the user has no experience in the past, a normal control routine is executed (the state is judged in step S40, the output is calculated in step S41, and the output is changed in step S42). If necessary (when the memory is full, that is, when there is no write capacity), in step S43, the dedicated I
Instruct C to delete the oldest data that appears the least,
In step S44, the output result of the microcomputer and the register state are transmitted to the dedicated IC with built-in memory, and in step S45, after instructing to store data, the state returns to the WAIT state again in step S32. The dedicated IC with a built-in memory receives these instructions, erases the oldest data with the lowest appearance frequency, outputs the contents of the previously received status decoder, the output result and register status received here, to the status memory and output, respectively. Store in memory.

The second embodiment of the present invention will be described below.

FIG. 4 shows an example of a hardware configuration for realizing the present invention, and FIG. 5 shows an operation execution flowchart thereof.

FIG. 4 shows blocks added to a conventional microcomputer to implement the present invention.

In the figure, reference numeral 41 denotes a status register, which is a register having a factor such as an input status, an output status, a register status, etc., which requires a change in output. For example, input register, output register, timer register, S10
Such as a register. Reference numeral 42 denotes a state memory, which is configured by an array of memory cells 45 with an integer multiple of the bit length of the state register 41. If the same state does not exist in the past (when the signal W is generated), the phenomenon changes. The contents of the status register 41 are stored each time, and if the same status as the status register 41 occurs again, the memory address 46
To select state "1". The output memory 43 has the same configuration as the state memory 42, but the configuration is similar to that of the output register 4
It has a configuration that is an integral multiple of the bit length of 4. Also, when the same state does not exist in the past (when the signal of W is generated), this output memory 43 also stores the output register 44 at the corresponding address of the memory address stored in the state memory 42 every time the phenomenon changes. Memorize the contents. Next, if the state stored in the state memory 42 occurs again, one corresponding memory address 46 becomes the select state "1",
The corresponding data in the output memory 43 is loaded into the output register 44 and output. 44 is an output register,
The data written here is the output. Reference numeral 47 is a transfer gate. When any one of the memory addresses 46 (only one is selected at any one time) is selected, the transfer gate becomes active, and the selected data in the output memory 43 is loaded into the output register 44. It On the other hand, in the case of a phenomenon that is not stored in the state memory 42 (a phenomenon that has not been experienced in the past), none of the memory addresses 46 is selected, the transfer gate 47 is turned off, and the output data is given from the data bus 49. Further, at this time, the signal W becomes "1", which instructs the system that this phenomenon has not been experienced in the past.

FIG. 5 is a flowchart showing the above-mentioned series of steps.

In step S50, the initial state is set. In step S51, it is tested whether the state has changed. If the state does not change, in step S52, the WAIT routine is repeated until the state changes, and the process is in a standby state. If the state has changed (change of input terminal state, change of internal register such as timer and SIO), the presence or absence of the same phenomenon in the past (presence or absence of the same data in the state memory 42) is determined by the signal W in step S53. . That is, when the signal W is "1", it is not present in the past, and when it is "0", it is present in the past. If it is present in the past, the contents of the output memory 43 are immediately loaded into the output register without performing judgment and calculation by the CPU in step S54, and the state returns to the WAIT state again in step S52. At this time, in the case of storing only those whose occurrence frequency is higher than the capacity limit of the memory, a memory for storing the count is further required.
The count is incremented after the output at 55. On the other hand, if it is not in the past, a normal routine is executed (the state is determined in step S56, the output is calculated in step S57, and the output register is rewritten in step S58), and then the phenomenon state (change) in step S60. (Including the previous output state) and output are written in the state memory and the output memory, respectively, and the state returns to the WAIT state again in step S52. Further, similarly to the above, if only the ones with a high phenomenon occurrence frequency are stored due to the memory capacity limitation, after changing the output, in step S59,
When there is no free data area in the memory, it is necessary to delete the data with the smallest count value from the oldest one.
However, the age of data can be easily determined by writing in the order of addresses.

[0020]

As described above, the high-speed control device according to the learning of the present invention is C
When the PU, the memory that stores the past input state and the output state, and the current input state and the past input state are the same, the CPU does not calculate the output state, and the output state in the memory is controlled and output. With respect to a phenomenon that has been experienced in the past, complicated judgment and calculation in the CPU are not required, and the controlled system can be instantly controlled by switching the control system. Therefore, a high speed control system is realized.

[Brief description of drawings]

FIG. 1 is a hardware configuration example of a dedicated IC with a built-in memory according to a first embodiment.

FIG. 2 is a system configuration diagram of the first embodiment.

FIG. 3 is an operation execution flowchart of the first embodiment.

FIG. 4 is a hardware configuration example of a second embodiment.

FIG. 5 is an operation execution flowchart of the second embodiment.

[Explanation of symbols]

 1 Microcomputer 2 Dedicated IC with built-in memory 3 Switch for switching between two control systems 4 Controlled system 5, 6 Communication 8, 9 Control output 11 Acknowledge signal 20 Communication unit 21 State decoder 22, 42 State memory 23, 43 Output memory 24, 44 output register 32 controller 25, 45 memory cell 26, 46 memory address 30, 31, 34 control signal 35, 49 bus 41 status register 47 transfer gate 48 output terminal

Claims (1)

[Claims] 1. A CPU, a memory for accumulating past input states and output states, and when the present input state and the past input states are the same, the CPU does not calculate the output state and A high-speed control apparatus by learning, comprising means for setting an output state as a control output.