JPH06231071A - Format conversion circuit - Google Patents

Abstract

PURPOSE:To provide a conversion circuit in which the scale of a circuit and a power consumption can be reduced by operating format conversion with serial data as they are. CONSTITUTION:This circuit is equipped with a shift register 10 in which N pieces of flop flops 1 and 2:1 selectors 2 equipped with first input terminals 2A and second input terminals 2B are alternately and serially connected, and the second input terminal 2B of each 2:1 selector 2 is connected with the output terminal 1B of each flip flop 1 corresponding to format conversion, and an N frequency-division counter 20 which N frequency-divides a clock signal Cs, and generates a switching signal Ts in each frame. Then, input data inputted to the first input terminal 2A of each 2:1 selector 2 and the input data for format conversion inputted to the second input terminal 2B are simultaneously switched synchronously with the switching signal Ts, and inputted prescribed format data Di are converted into specific format data Do while the serial data are shifted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data format conversion circuit for data transmission, and more particularly to a format conversion circuit incorporated as one circuit portion of an LSI composed of a gate array.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing an example of a conventional format conversion circuit. For example, input format data Di (1
Output format data Do (1 frame: 12b) in which a specific format is output as a frame: 12bit
When converting to (it), conventionally, format data conversion processing is performed by the circuit configuration as shown in FIG.
10a is 12 flip-flops FF1-1 to FF1
It is a 12-bit shift register composed of −12 and converts serial data into parallel data. Two
Reference numeral 0a denotes a divide-by-12 counter composed of a counter and a decoder, which generates a latch signal Ls for converting serial data into parallel data and select signals Ss1 to Ss12 for converting parallel data into serial data.

Reference numeral 30 designates flip-flops FF2-1 to FF.
It is a 12-bit latch circuit composed of 2-12,
Holds parallel data temporarily. 40 is 12 A
An AND-OR circuit composed of an ND gate and a 12-bit input OR gate, and select signals Ss1 to Ss1
In parallel with 2, the parallel data is converted into serial data.

FIG. 6 is a time chart showing a format data conversion process by a conventional format conversion circuit. Input format data Di shown in FIG. 3 is input, and it is shifted by FF1-1 to FF1-12 (F
F1-1Q to FF1-12Q indicate output data of the flip-flop). Then, the outputs of FF1-1 to FF1-12 are latched by FF2-1 to FF2-12 by the latch signal Ls generated by the divide-by-12 counter 20a, and 12 bits are output.
Parallel data (FF2-1Q to FF2-
12Q indicates the data latched in the flip-flop).

Further, select signals Ss1 to Ss12 generated by the 12-frequency division counter 20a for this parallel data.
Therefore, the parallel data is selected in the order desired to be output by the AND-OR circuit 40 and converted into serial data to obtain the output format data Do.

[0006]

Therefore, in the conventional format conversion circuit configured as described above, when the format conversion of serial data is performed, the serial data is once converted into parallel data and latched and latched. A method of converting parallel data into serial data format data has been used. Therefore, when a format conversion circuit is built in an LSI configured by a gate array, for example, when the LSI has a limited number of gates, there is a problem that the circuit configuration becomes large. A format conversion circuit that can be downsized has been desired.

The present invention has been made in consideration of the above problems. When the format conversion of serial data is performed, the predetermined format data (Di) is converted into a specific format (Do) while maintaining the serial data state. ), It is possible to significantly reduce the circuit scale, and to provide a format conversion circuit that also leads to a reduction in power consumption and a reduction in the number of nets (gates). .

[0008]

FIG. 1 is a block diagram showing the configuration of a format conversion circuit of the present invention. In FIG. 1, the format conversion circuit of the present invention is a format conversion circuit for converting a predetermined format data (Di), in which one frame consists of N-bit serial data, into specific format data (Do). It is composed of a 2: 1 selector 2 having one input terminal 2A and a second input terminal 2B, and the first input terminal 2B and the flip-flop 1 are alternately connected in series and N: 2: 1 each.
Second input terminal 2B of selector 2 and each flip-flop 1
Shift register 10 having output terminals 1B connected to each other for format conversion, and a clock signal Cs input to each flip-flop 1 for shifting serial data.
Is divided by N to generate a switching signal Ts for each frame N
The frequency division counter 20 and the first of each 2: 1 selector 2
The input data input to the input terminal 2 and the input data for format conversion input to the second input terminal 2B,
It is characterized in that it is switched all at once in synchronization with the switching signal Ts of the N frequency dividing counter 20 and that the serial data of the input predetermined format data (Di) is shifted and converted into a specific format data (Do).

The shift register 10 maintains the state of serial data by switching the input data of the first input terminal 2A and the second input terminal 2B of the 2: 1 selector 2 by a switching signal TS synchronized for each frame. Predetermined format data DI is converted to specific format data D
It is preferably configured to convert to O.

The flip-flop 1 of the shift register 10 is preferably a D-flip-flop.

A shift register 10 consisting of the flip-flop 1 and a 2: 1 selector 2 and an N dividing counter 2
0 may be built in an LSI configured by a gate array.

In the present invention, the shift register 10 including the flip-flop 1 and the 2: 1 selector 2 is used.
And the N frequency division counter 20 is TTL or CM.
It can be used as a format conversion circuit incorporated in a gate array LSI including an OS or the like.

[0013]

According to the present invention, in FIG. 1, when the predetermined format data Di in which one frame consists of N bits is input to the input section 1A of the flip-flop 1, it is normally synchronized with the clock signal Cs. The output section 1B of the flip-flop 1 is sequentially shifted to the input section 1A of the next flip-flop 1 through the first input section 2A of the 2: 1 selector 2 and its output section 2C. Here, when the switching signal Ts obtained by dividing the clock signal Cs by N from the N frequency division counter 20 is input to the 2: 1 selector 2 in synchronization with each frame, it is input to the first input unit 1B of the 2: 1 selector. The input data to be converted can be simultaneously switched to the input data for format conversion to be input to the second input unit 2B. At this time, since the second input terminal 2B of each 2: 1 selector 2 and the output terminal 1A of each flip-flop 1 are connected corresponding to the format conversion, the data for the format conversion is switched and the final output of the flip-flop 1 is output. The converted specific format data Do is output from the terminal 1B.

The shift register 10 maintains the state of serial data by switching the input data of the first input terminal 2A and the second input terminal 2B of the 2: 1 selector 2 by a switching signal Ts synchronized for each frame. Predetermined format data Di is converted to specific format data D
Since it can be configured to convert to o, the circuit scale can be reduced, power consumption can be reduced, and the number of nets can be reduced.

Since the flip-flop 1 of the shift register 10 is composed of a D-flip-flop, the circuit structure is further simplified.

A shift register 10 comprising the flip-flop 1 and a 2: 1 selector 2 and an N frequency dividing counter 2
0 is suitable for an LSI having a limited number of gates because it can reduce the number of gates when incorporated in an LSI configured by a gate array.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the embodiments shown in the drawings. This does not limit the invention.

FIG. 2 is a circuit diagram showing an embodiment of the format conversion circuit of the present invention. 2, the same components as those in FIG. 1 have the same numbers. Also, FIG.
Is a predetermined format data Do (input format data) which is composed of serial data of 12 bits per frame as shown in FIG.
The circuit which converts into (output format data) is shown. 1
0 is 12 flip-flops FF1-1 to FF1-1
2 and 10 2: 1 selectors SR1-1 to SR1-10 composed of an inverter, an AND gate, and an OR gate, and normally shifts serial data in synchronization with the clock signal Cs. To do. 20
Is a 12-divider counter composed of a counter and a decoder, and generates a switching signal Ts for switching the serial data of the flip-flops FF1-1 to FF1-12 into data for format conversion.

FIG. 3 is an explanatory diagram showing an example of input format data and output format data. FIG. 3 shows a correspondence relationship between input format data Di (predetermined format data) in which one frame is composed of 12-bit serial data and output format data Do (specific format data) to be converted.

FIG. 4 is a time chart showing a format data conversion process by the format conversion circuit of the present invention. The data processing for format conversion will be described below with reference to FIG. Input the input format data Di shown in FIG. 3 and input it to FF1-1 to FF1-12.
bit shift (FF1-1Q to FF1-12Q indicate output data of the flip-flop). And 12bi
When the shift signal Ts generated by the 12 frequency division counter 2 is input to the 2: 1 selectors SR1-1 to SR1-10 when t-shifted, the serial data is rearranged in the order of the format data to be output, and the serial data is further shifted. As a result, the converted output format data Do is obtained.

[0021]

According to the present invention, it is possible to significantly reduce the circuit scale for performing format conversion, and further reduce power consumption and the number of nets.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a format conversion circuit of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of a format conversion circuit of the present invention.

FIG. 3 is an explanatory diagram showing an example of input format data and output format data.

FIG. 4 is a time chart showing format data conversion processing by the format conversion circuit of the present invention.

FIG. 5 is a circuit diagram showing an example of a conventional format conversion circuit.

FIG. 6 is a time chart showing conversion processing of format data by a conventional format conversion circuit.

[Explanation of symbols]

 10 shift register 20 12 frequency divider FF1-1 to FF1-12 flip-flop SR1-1 to SR1-10 2: 1 selector Cs clock signal Ts switching signal Di input format data Do output format data

Claims (4)

[Claims] 1. A format conversion circuit for converting a predetermined format data (Di) consisting of N-bit serial data in one frame into a specific format data (Do), wherein a flip-flop (1) and a first input terminal (2A) are provided. ) And a 2: 1 selector (2) having a second input terminal (2B), the first input terminal (2B) and the flip-flop (1) are alternately connected in series by N pieces, and 2: 1 each.
A shift register (10) in which a second input terminal (2B) of the selector (2) and an output terminal (1B) of each flip-flop (1) are connected for format conversion, and a clock signal for shifting serial data (Cs) is divided by N to generate a switching signal (Ts) for each frame by an N divider counter (20), and each 2: 1 selector (2)
The input data input to the first input terminal (2A) and the input data for format conversion input to the second input terminal (2B) are used as a switching signal (Ts) from the N frequency dividing counter (20). A format conversion circuit characterized in that it switches synchronously all at once, and converts serial data of input predetermined format data (Di) into specific format data (Do) while shifting. 2. The shift register (10) is 2: 1.
By switching the input data of the first input terminal (2A) and the second input terminal (2B) of the selector (2) by a switching signal (Ts) synchronized for each frame, a predetermined format is maintained while maintaining the serial data state. The format conversion circuit according to claim 1, wherein the data (Di) is converted into a specific format (Do). 3. The format conversion circuit according to claim 1, wherein the flip-flop (1) of the shift register (10) is a D-flip-flop. 4. A shift register (10) and N comprising the flip-flop (1) and a 2: 1 selector (2).
The frequency division counter (20) is an L-shaped gate array.
The format conversion circuit according to claim 1, wherein the format conversion circuit is incorporated in SI.