JPS63262933A - Multiplex transmission circuit - Google Patents

Abstract

PURPOSE:To make the manufacture of a dedicated IC unnecessary and to reduce cost, by providing both parity check and CRC check functions, and selecting either of them. CONSTITUTION:A transmission part attaches a parity bit generated by a parity bit generating means 1 or a CRC bit generated by a CRC bit generating means 2 selectively on data, and a reception part performs the the parity check or the CRC check synchronizing with the switching of the check bit of the transmission part. Therefore, it is possible to select either the parity check or the CRC check at need. In such a way, it is possible to eliminate the need of the manufacture of the dedicated IC.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multiplex transmission circuit, and particularly relates to a multiplex transmission circuit that performs a parity check or CRC check on data when transmitting data from a transmitter to a receiver. Regarding circuits.

[Prior Art] In a multiplex transmission circuit, when data is transmitted from a transmitting section to a receiving section, an error check is performed at the receiving section in order to check for errors in the data during transmission.

One typical error checking method is a parity check and a CRC check. In the validity check, the transmitter adds a redundant bit called a parity bit to the data, and the receiver performs, for example, a horizontal parity check. In the CRC check, a CRC bit consisting of a plurality of bits is added to data in a transmitter, and a CRC check is performed in a receiver.

[Problems to be Solved by the Invention] The validity check described above only requires adding one valid bit to the data, so it has the advantage of minimizing serial data cycle time. On the other hand, it has the disadvantage that the probability of error checking is small. On the other hand, in the case of a CRC check, although the probability of error checking increases, the number of bits of the CRC pit increases, so the disadvantage is that the cycle time becomes long. Which method to use is selected in consideration of the importance of the data to be transmitted and the cost of the product. Conventionally, circuits were configured only for one of them, or dedicated ICs were manufactured, so separate circuits had to be configured or dedicated ICs had to be manufactured depending on the device.

Therefore, the main purpose of the present invention is to provide a multiplex transmission circuit that has both parity check and CRC check functions, allows selection of either one, and can reduce costs by implementing it into an IC. That's true.

[Means for Solving the Problems] The present invention is a multiplex transmission circuit that performs a data error check by a validity check or a CRC check when transmitting data from a transmitter to a receiver, wherein the transmitter parallel-to-serial conversion means for converting bit-parallel data into bit-serial data; parity bit generation means for generating variable bits based on the bit-parallel data; and CRC pit generation means for generating CRC bits. a first selection means for selecting one of the generated parity bits and CRC bits; and a first selection means for selecting either the generated parity bit or CRC bit; and check bit adding means.

On the other hand, the receiving section includes a check pit *\ stage for separating check bits from the transmitted bit serial data, and a serial/parallel conversion means for converting the bit serial data from which the check pits have been separated into bit parallel data. , a parity check means for performing a parity check on data converted into bit parallel by the serial/parallel conversion means based on the separated parity pits, and a CRC check on the data converted into bit parallel based on the separated CRC bits. and a second selection means that selects either the check result by the parity check means or the check result by the CRC check means in synchronization with the transmitter.

[Operation] In the multiplex transmission circuit according to the present invention, in the transmitting section, the parity bit generated by the parity bit generation means and C
The CRC bits generated by the RC pit generation means are selectively added to the data, and the receiving section performs a parity check or CRC check in synchronization with the switching of the check bits in the transmitting section. Either parity L nick or CRC check can be selected accordingly.

[Embodiment] FIG. 1 is a schematic block diagram of a transmitter according to an embodiment of the present invention, and FIG. 2 is a schematic block diagram of a receiver as well.

First, the configuration of an embodiment of the present invention will be described with reference to FIGS. 1 and 2. In this embodiment, it is assumed that 8-bit data is transmitted from the transmitter 30 to the receiver 70. The 8-bit data input to the transmission 130 is given to the parity bit generation circuit 1 and the ORC pit generation circuit 2.

Parity bit generation circuit 1 generates a 1-bit parity bit based on 8-bit data, and ORC pit generation circuit 2 generates 5-bit ORC pits based on 8-bit data.

Generated 1-bit parity bit and 5-bit CR
The first bit at the bottom of CL' is given to the selection circuit 3. The selection circuit 3 selects the parity bit or the first bit of the ORC pit based on the selection signal. Furthermore, the 8-bit data is transferred to the shift register 10.
given to.

Shift register 10 is constructed by cascading fifteen 7-lip flops 11 to 20 and converts parallel data and parity bits or ORC pits into serial data. For this purpose, a start bit is given to the flip-flop 11 in the first stage of the shift register 10, 8-bit data is given to the flip-flops 12 to 19 in the second to ninth stages, and 7-bit data is given to the flip-flops 12 to 19 in the second to ninth stages. The output of the selection circuit 3 is given to the 70 tube 2o.

Furthermore, 11 flip-flops 21 to 25 included in the shift register 10 are connected in series, and the second to fifth bits of the five ORC bits are given to the flip-flops 21 to 24. is given a stop bit. Then, the output of the 11th stage flip-flop 21 and the final stage 7
The output of the flip-flop 25 is applied to the selection circuit 4.

This selection circuit 4 is switched according to a selection signal, and
The output of the first stage flip-flop 21 or the final stage 7
The output of the lip flop 25 is selected and applied to the 7 lip flop 20 in the 10th stage.

Next, the configuration of the receiving section 70 will be explained with reference to FIG. The serial data transmitted by the transmitting section 30 is given to the shift register 50 of the receiving section 70. This shift register 50 includes 15 flip-flops 51 to 65, and converts serial data to which parity bits or ORC pits are added into parallel data.

To explain more specifically, the first stage flip-flop 51
The 7-lip-flops 60 in the 11th to 10th stages are connected in cascade, and the 7-lip-flops 61 in the 11th stage to the 7-lip flops 65 in the most IIM stage are also cascaded. And 1
The output of the first stage flip-flop 61 and the output of the final stage flip-flop 65 are applied to the selection circuit 5. The selection circuit 5 selects one of them based on the select signal and supplies it to the 7 lip-flop 60 in the 10th stage.

The first stage 7-lip flop 7a block 51 outputs a start bit from serial data, and the second-stage flip-flop 52 to the ninth stage 7-lip flop 59 convert the serial data into 8-bit parallel data and output it to the latch 9. give to The latch 9 is based on the strobe signal.
Latch 8-bit parallel data. Furthermore, the 7-lip 70-tube 60 in the 10th stage outputs the first bit of the 1-bit parity bit or the 5-bit ORC pit to be sent to the parity check circuit 6 and the CRC check circuit 7.
give to. Further, the flip-flops 61 to 64 output the remaining bits of the ORC pit and provide them to the CRC check circuit 7. The final stage flip 70 tube 65 outputs a stop bit.

Parity check circuit 6 performs a validity check on 8-bit parallel data based on 1-bit parity bit. Further, the CRC error circuit 7 performs a CRC check on the 8-bit parallel data based on the 5-bit CRC bit. A check signal from parity check circuit 6 and a check signal from CRC check circuit 7 are applied to selection circuit 8 . The selection circuit 8 performs parity check or CRC based on the selection signal.
Select and output one of the check signals from the check results. Note that the select signal is synchronized with the select signal of the transmitter 30, so that when the transmitter 30 selects a parity bit, the receiver 70 also outputs a parity check result signal.

FIG. 3 is a diagram for explaining the operation of parity check according to an embodiment of the present invention, and FIG.
FIG. 3 is a diagram for explaining a check operation.

Next, with reference to FIGS. 1 to 4, a specific operation of an embodiment of the present invention will be described.

First, when adding parity pits to 8-bit parallel data and transmitting it from the transmitter 30 to the receiver 70,
The input of the selection circuit 3 is switched to the parity bit generation circuit 1 side by the selection signal, and the selection circuit 4 selects the output of the flip-flop 25 at the final stage of the shift register 10 and supplies it to the flip-flop 20 at the 10th stage. . The 8-bit parallel data is applied to a parity bit generation circuit 1, and a 1-bit parity pit is generated. This parity pit is loaded via the selection circuit 3 into the 7-lip flop 20 at the 10th stage. In addition, a start bit is loaded into the first stage 7-lip flop O-tube 11, 8-bit parallel data is loaded into one or more 7-lip flop O-tubes 12 from the 2nd to 9th stages, and 10
A parity pit is loaded into the 7th lip flop 20 at the 7th stage, and a stop bit is loaded into the 7th lip flop 25 at the final stage.

At this time, since the output of the final stage 7 flip-flop 25 is selected by the selection circuit 4, the flip 7 flip-flops 21 to 24 are invalidated.

When an O clock pulse (not shown) is applied to the shift register 10, the start bit (S), 8-bit serial data, and parity pit (
P) and a stop bit (E) are output serially.

On the other hand, in the receiving section 70, the input of the selection circuit 5 is switched to the final stage flip-flop 65 side, and the input of the selection circuit 8 is switched to the output side of the parity check circuit 6. The serial data transmitted from the transmitter 30 is serially input to the shift register 50, and the flip-flop 6
59 selection circuit 5, flip-flop 60.59...5
2.51 based on a clock pulse (not shown). Then, a start bit is output from the flip-flop 51 at the first stage, and 8-bit parallel data is output from the 7-lip 70 tubes 52 to 59 at the second to ninth stages and is applied to the latch 9. It is also given to

Latch 9 latches and outputs 8-bit parallel data based on the strobe signal. Further, the parity check circuit 6 performs a parity check on the 8-bit parallel data based on the parity pit provided from the flip-flop 60 in the tenth stage. The check result signal is outputted via the selection circuit 8. Further, a stop bit is output from the 7-lipflip 65 at the final stage.

Next, when performing a CRC″f nick, the transmitter 30
Then, based on the select signal, the selection circuit 3 selects the first bit of the CRC bit generation circuit 2, and the selection circuit 4 selects the first bit of the CRC bit generation circuit 2.
The output of the flip-flop 21 in the second stage is selected. In this case, the CRC bit generation circuit 2 generates 5-bit CRC bits based on 8-bit parallel data. Of these 5 CRC bits, the first bit is loaded into the 10th stage 7-lip 70 block 20 via the selection circuit 3, and the remaining 4 bits are loaded into the flip-flops 21 to 24.
loaded into.

Then, in the same way as described above, the start bit is set to 7.
The 8-bit parallel data is loaded into the 7 flip-flops 12 to 19, and the stop bit is loaded into the final flip-flop 25. When a clock pulse is applied to the shift register 10, the start bit (S), 8-bit parallel data, and 5-bit C
The RC bit and stop bit (E) are output serially and sequentially.

In the receiving section 70, the selection circuit 5 selects the output of the flip-flop 61 at the 11th stage and serially applies it to the 7-lip flop 60 at the 10th stage, and the selection circuit 8 selects the output of the CRC boonick circuit 7.

In this state, serial data to which a CRC check bit has been added as shown in FIG. 4 is serially input to the shift register 50. That is, the shift register 50
is based on the clock pulse, the start bit (S),
8-bit serial data 25-bit CRC bits and stop bits are sequentially shifted.

Then, a start bit is output from the flip 70 knob 51 in the first stage, and 8-bit parallel data is output from the flip 70 knobs 52 to 59 in the second to ninth stages, and this data is sent to the latch 9 based on the strobe signal. Latched. Further, flip-flop 60 outputs the first bit of 5 CRC bits, and flip-flops 61 to 64 output the remaining CRC bits in parallel. The 5 CRC bits are provided to a CRC check circuit 7. The CRC check circuit 7 performs a CRC check on 8-bit parallel data based on 5-bit CRC bits. Then, the check result signal is outputted via the selection circuit 8.

[Effect of the Invention 1] As described above, according to the present invention, the transmitter C can switch between parity bit generation and CRC bit generation, and the receiver C can perform parity check and CRC boonicking in synchronization with the transmitter. Since it is configured to be switchable, if you want to perform high-speed transmission even if the probability of error checking is low, select parity 1, and if you want to increase the probability of error checking even if the transmission speed is slow, select CRC check. It is possible to select the check mode as needed.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a transmitter according to an embodiment of the present invention. FIG. 2 is also a schematic block diagram of the receiving section. FIG. 3 is a diagram showing 8-bit serial data with parity pits added. FIG. 4 is a diagram showing 8-bit serial data with CRC bits added. In the figure, 1 is a parity bit generation circuit, 2 is a CRC
Bit generation circuit, 3.4.5.8 is selection circuit, 6 is parity check circuit, 7 is CRC check circuit, 9 is latch, 10.50 is shift register, 11 to 25.5
1 to 65 indicate flip-flops.

Claims (2)

[Claims] (1) A multiplex transmission circuit that performs an error check by parity check or CRC check of the transmitted data when transmitting data from a transmitting section to a receiving section, the transmitting section transmitting bit-parallel input data. parallel-to-serial conversion means for converting into bit-serial data; parity bit generation means for generating parity bits based on the input bit-parallel data; and parity bit generation means for generating parity bits based on the input bit-parallel data. , CRC
CRC bit generation means for generating bits; and first selection means for selecting and outputting either the parity bit generated by the parity bit generation means or the CRC bit generated by the CRC bit generation means. and check bit addition means for applying the parity bit or CRC bit selected by the first selection means to the parallel-to-serial conversion means and adding it to the bit-serial converted data, the receiving unit a check bit separating means for separating check bits from the bit serial data to which the check bits have been added transmitted from the transmitter; and bit parallel processing for the bit serial data from which the check bits have been separated by the check bit separating means. serial-parallel conversion means for converting the data into bit-parallel data; and parity check means for performing a parity check on the data converted into bit parallel by the serial-parallel conversion means based on the parity bits separated by the check bit separation means. and a CRC check means for performing a CRC check on the data converted into bit parallel by the serial-to-parallel conversion means based on the CRC bits separated by the check bit separation means, and a first selection included in the transmission section. 2. A multiplex transmission circuit comprising second selection means that is switched in synchronization with the parity check means and selects and outputs either the check result by the parity check means or the check result by the CRC check means. (2) The multiplex transmission circuit according to claim 1, wherein the receiving section includes storage means for storing data converted into bit-parallel data by the serial-parallel conversion means.