JP3953650B2 - Information encoding apparatus and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information encoding apparatus in a digital mobile radio, and more particularly to an information encoding apparatus having a convolutional encoding function and a bit interleaving function.
[0002]
[Prior art]
In digital mobile communication devices, in order to avoid the effects of fading due to high-speed movement, information is encoded by error correction codes such as convolutional codes and bit interleaving processing that converts burst errors into random errors. Yes.
[0003]
The convolutional code is a method of encoding data to be transmitted with the data used when encoding so far. In a convolutional code, an item indicating how many bits are used to generate a certain code data is called a constraint length and is expressed as “K”, and a ratio of how many bits of encoded data are generated from 1 bit of data to be transmitted. It is called a coding rate and is represented by “R”. In general, convolutional codes are added with “0” data having a constraint length of −1 bit at the end of information bits for the purpose of improving error correction capability when decoding. This data is called a termination code.
[0004]
On the other hand, bit interleaving performs bit rearrangement processing. Due to bit interleaving, burst errors where the received electric field such as fading is weak are scattered and apparently converted to random errors. In the bit rearrangement process, a parameter indicating how far the data arranged before the process is separated after the process is referred to as a depth.
[0005]
FIG. 2 is a circuit block diagram of a conventional information encoding apparatus including a convolutional encoding circuit and a bit interleave circuit. In the information encoding apparatus shown in the figure, 12-bit input data to which a 2-bit termination code is added is serially input to the convolutional encoding circuit 20, and the constraint length K = 3, the information rate R = 1 / 2 is subjected to convolutional coding to 24 bits, and then bit interleaved to a depth of 6 by a bit interleave circuit 25.
[0006]
Here, the generator polynomial of the convolutional code is
G1 (D) = 1 + D2
G2 (D) = 1 + D1 + D2
The bit interleave circuit 25 has a depth of 6 × 4.
[0007]
The convolutional encoding circuit 20 includes a three-stage shift register 21, an arithmetic circuit 22 that performs an exclusive OR (EXOR) operation on the first and third stages of the shift register 21, and the first stage of the shift register 1. An arithmetic circuit 23 that performs an exclusive OR operation on the outputs of the second and third stages and an output G1 or G2 from each of the arithmetic circuits 22 and 23 are input, and either one is selected according to a selection signal of a control circuit (not shown). It consists of a 2-input 1-output multiplexer 24 for output. In the initial state, all 0s are set in the shift register 21, and when 1 bit of data to be encoded is input in this state, the data in the first and second stages of the shift register 21 are in the second and third stages, respectively. In addition to being shifted, input data is latched in the first stage.
[0008]
Next, G1 data obtained by exclusive ORing the first and third stage data of the shift register 21 and G2 data obtained by exclusive ORing the first, second and third stage data are generated. Is input. In response to the control signal, the multiplexer 24 first outputs G1 data and then outputs G2 data. As a result, convolutional encoding can be performed for 1 bit of data, and 2 bits are obtained as convolutionally encoded data. Accordingly, by repeating the above process 12 times, a total of 24 bits of encoded data is generated.
[0009]
The convolutionally encoded data is input to the bit interleave circuit 25 which is the next process. The bit interleave circuit 25 includes a 1-input 6-output demultiplexer 26, 6-stage 4-bit shift registers 27 to 32, and a 6-input 1-output multiplexer 33. The generated convolutional code data is input to the demultiplexer 26, and the first 4 bits are latched in the first-stage shift register 27. The next 4-bit data input to the demultiplexer 26 is latched in the second-stage shift register 28. By repeating this process until all 24 bits of the convolutional code are input, the data after the 24-bit convolutional encoding is latched in all the shift registers 27-32.
[0010]
When all the data is latched, the multiplexer 33 that receives the outputs of the six-stage shift registers 27 to 32 selects and outputs the first one bit from the first-stage shift register 27. At this time, the remaining data in the shift register 27 is shifted by 1 bit. Next, the multiplexer 33 selects the second-stage shift register 28 and outputs 1 bit therefrom. The remaining data in the shift register 28 is also shifted to the right by 1 bit. By repeating the same process for the shift registers 29 to 32 in the third to sixth stages, 6-bit data is sequentially output from the demultiplexer 33. Furthermore, by repeating this process three times, the bit interleaving process for a total of 24 bits of data is completed.
[0011]
The processing in the bit interleave circuit 25 is actually performed after the processing in the convolutional coding circuit 20 is performed. That is, the process of inputting 1-bit data to the convolutional encoding circuit 20 and inputting 2-bit convolutionally-encoded data to the bit interleaving circuit 25 is performed for information bits (12 bits in the above example). Repetitively, when all the shift registers 27 to 32 of the bit interleave circuit 25, that is, 6 × 4 bit buffers are filled, a process of outputting 1 bit from each shift register is started.
[0012]
[Problems to be solved by the invention]
As described above, in the conventional information encoding apparatus, the convolutional encoding process is completed, and the output cannot be performed unless all the quantitative encoding process data is input to the buffer of the bit interleave circuit. However, there was a problem that continuous data processing could not be performed.
[0013]
Accordingly, an object of the present invention is to provide an information encoding apparatus that performs high-speed information encoding processing by continuously performing convolutional encoding processing and bit interleaving processing.
[0014]
Another object of the present invention is to reduce the size of the apparatus by reducing the number of circuits required for the information encoding apparatus.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, an information encoding apparatus of the present invention includes an n-bit (0 to n-1) ring buffer capable of inputting n-bit data including a termination code in parallel, and an even number of the ring buffer. N / 2 convolutional encoding circuits that perform convolutional encoding on the bits of the data input to, and the bits generated by the respective convolutional encoding circuits are input in parallel and sequentially output serially. And a multiplexer.
[0016]
The present invention also provides an n-bit (0 to n-1) buffer capable of inputting n-bit data including a termination code in parallel, and a convolutional code for data bits input to the even number of the buffer. N / 2 first convolutional encoding circuits for performing the conversion, and n / 2 second convolutional encodings for performing the convolutional encoding on the odd bits of the buffer A circuit and a multiplexer that inputs the bits generated by the first and second convolutional coding circuits in parallel and sequentially outputs the bits may be provided.
[0017]
In these information encoding apparatuses, it is preferable that each of the convolutional encoding circuits has a constraint length of 3 and an encoding rate of 1/2.
[0018]
In addition, the multiplexer includes a first multiplexer that receives one output of each of the convolutional encoding circuits, a second multiplexer that receives the other output of each of the convolutional encoding circuits, and the first And a third multiplexer having the outputs of the first and second multiplexers as inputs.
[0019]
The present invention also includes a step of inputting n-bit data including a termination code in parallel to an n-bit (0 to n-1) ring buffer, and a bit of data input to an even number of the ring buffer. The process of performing convolutional encoding in parallel, the step of inputting the bits generated by the above convolutional encoding in parallel to the multiplexer and sequentially outputting them serially, and the data input to the ring buffer being shifted by 1 bit A step of performing convolutional encoding on the bits of data input to the even number of the buffer in parallel, and a bit generated by the convolutional encoding is input in parallel to the multiplexer and sequentially serialized. And an information encoding method including a step of outputting to the information.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail based on the illustrated embodiment. FIG. 1 is a circuit block diagram in an embodiment of an information encoding apparatus according to the present invention, which has a convolutional encoding function and a bit interleaving function. The information encoding apparatus according to the present invention includes a 12-bit ring buffer 10, two sets of convolutional encoding circuits 11 to 16 each including two types of arithmetic circuits, two multiplexers 17 and 18 having six inputs and one output, And a 2-input 1-output multiplexer 19.
[0021]
The ring buffer 10 is a 12-bit buffer that can input 12-bit data including a termination code in parallel. In the following description, the codes 0 to 11 are associated with the address of the ring buffer 10 in order from the address where the first bit of the input data is arranged. The 12-bit data arranged in the ring buffer 10 is configured to be shiftable by at least one bit. In this case, the first bit of the input data is shifted from 0th to 11th in the ring buffer 10.
[0022]
Each of the convolutional encoding circuits 11 to 16 includes arithmetic circuits 11a to 16a that perform an exclusive OR operation according to the generator polynomial G1 and arithmetic circuits 11b to 16b that perform an exclusive OR operation according to the generator polynomial G2. Then, the convolutional encoding circuit 11 is connected to the ring buffer 10 so that the data of the 10th, 11th, and 0th addresses is input data. Similarly, the convolutional encoding circuit 12 is connected to No. 0, 1 and 2, and is connected to the convolutional encoding circuit 13, No. 2, No. 3 and No. 4, and the convolutional encoding circuit 14 is Connected to Nos. 4, 5, and 6, the convolutional encoding circuit 15 is connected to Nos. 6, 7, and 8, and the convolutional encoding circuit 16 is connected to Nos. 8, 9, and 10. Has been. Therefore, for example, in the convolutional encoding circuit 11, the arithmetic circuit 11a outputs G1 based on the 10th and 0th data of the ring buffer 10, and the arithmetic circuit 11b is the 10th and 11th of the ring buffer 10. And G2 is output based on the 0th data. As a result, all the convolutional encoding circuits 11 to 16 can simultaneously obtain six G1 outputs and six G2 outputs.
[0023]
The multiplexer 17 receives six pieces of G1 data output from one of the arithmetic circuits 11a to 16a of the convolutional encoding circuit in parallel, and sequentially outputs them serially in accordance with a control signal. The convolutionally encoded data for the first bit of the data input to the ring buffer 10, that is, the data from the arithmetic circuit 11a is first output from the multiplexer 17 and sequentially from the arithmetic circuits 12a, 13a, 14a, 15a and 16a. Followed by output.
[0024]
The multiplexer 18 receives six pieces of G2 data output from the other arithmetic circuits 11b to 16b of the convolutional encoding circuit in parallel, and sequentially outputs them serially in accordance with a control signal. Similar to the case of the multiplexer 17, the convolutionally encoded data for the first bit of the data input to the ring buffer 10, that is, the data from the arithmetic circuit 11b is first output from the multiplexer 18, and the arithmetic circuits 12b, 13b, Data from 14b, 15b and 16b are subsequently output.
[0025]
The multiplexer 19 receives outputs from the multiplexers 17 and 18 and outputs one of them based on a control signal. The control signal causes the multiplexer 19 to first output the 6-bit data from the multiplexer 17 continuously and then output the 6-bit data from the multiplexer 18. As a result, the data from the arithmetic circuits 11a, 12a, 13a, 14a, 15a, 16a, 11b, 12b, 13b, 14b, 15b and 16b are serially output from the multiplexer 19.
[0026]
Next, the operation of the information encoding apparatus will be described. First, 12-bit data is input to the 12-bit ring buffer 10 in parallel. At this time, the first bit of the data is arranged at the 0th position of the ring buffer 10. In the convolutional code, when the first 1 bit is input, all the data in the shift register must be “0”, but the first bit of the input data is the end of the 2 bits “0” at the end. This condition can be satisfied by performing convolutional encoding together with the code.
[0027]
When data is input to the ring buffer 10, the multiplexers 17 and 18 are selected to output the data from the convolutional encoding circuit 11, and the multiplexer 19 outputs the data from the multiplexer 17, ie, G1. Selected as As a result, the G1 data from the arithmetic circuit 11a is first output from the multiplexer 19.
[0028]
Next, the selection of the multiplexer 19 is left as it is, and the multiplexer 17 is selected to output the data from the convolutional encoding circuit 12. As a result, the G1 data from the arithmetic circuit 12a is next output from the multiplexer 19. Similarly, the multiplexer 17 sequentially selects the convolutional encoding circuits 13 to 16, thereby sequentially outputting the G1 data from the arithmetic circuits 13 a to 16 a to the multiplexer 19. Thus, the multiplexer 19 sequentially outputs the first 6 bits of data.
[0029]
Next, the input of the multiplexer 19 is switched to the multiplexer 18 side, that is, the G2 data output side. The multiplexer 18 receives G2 data from the arithmetic circuits 11b to 16b, and these data are sequentially output serially. Thus, the multiplexer 19 sequentially outputs the G2 data from the arithmetic circuits 11b to 16b as the next 6-bit data, that is, the 7th to 12th bit data, following the first 6 bits.
[0030]
Subsequently, the data input to the ring buffer 21 is shifted to the right by 1 bit by a control unit (not shown). As a result, the first bit of the data arranged at the address 0 is shifted to the last 11th, and the second bit from the beginning arranged at the 1st is arranged at the 0th. That is, by shifting 1 bit to the right, odd bits of input data are shifted from even addresses to odd addresses, and even bits of input data are shifted from odd addresses to even addresses. The Rukoto.
[0031]
In a state where the input data is shifted to the right in the ring buffer 21, the convolutional encoding by the respective convolutional encoding circuits 11 to 16 is executed as described above. The resulting G1 and G2 data are sequentially output as 13th to 24th bit data from the multiplexer 19 as described above by controlling the multiplexers 17, 18 and 19. That is, the multiplexer 17 is selected as the first 6 bits, and G1 data from the arithmetic circuits 11a to 16a are sequentially output. As the next 6 bits, the multiplexer 18 is selected, and the G2 data from the arithmetic circuits 11b to 16b are sequentially output.
[0032]
As described above, convolutional coding and bit interleaving can be performed simultaneously. Here, input data is input in parallel, and serially bit-interleaved data can be acquired in the next one step, thereby shortening the encoding processing time. In addition, the number of registers used in the entire apparatus is approximately half, and the circuit can be reduced in size.
[0033]
The embodiment of the present invention has been described with reference to the drawings. However, the present invention is not limited to the matters shown in the above-described embodiments, and it is obvious that changes, improvements, etc. can be made based on the description of the scope of claims. In the above embodiment, a buffer for inputting data in parallel is configured by a ring buffer, and by performing bit shift, convolutional encoding is realized by a convolutional encoding circuit that is ½ the number of data bits. Yes. However, the present invention can be configured so that convolutional coding for all the bits of the input data can be realized without performing a bit shift by providing the same number of convolutional coding circuits as the bit length of the input data. good.
[0034]
In the above embodiment, the case where the convolutional coding circuit has a constraint length of 3 and a coding rate of 1/2 and the bit interleave circuit has a depth of 6 × 4 has been described. It is not limited.
[0035]
【The invention's effect】
As described above, according to the present invention, the convolutional encoding and the bit interleaving process are continuously performed without delay, so that there is an effect that high-speed encoding of information can be realized.
[0036]
In addition, the number of necessary registers can be halved as compared with the conventional information encoding apparatus, and a remarkable effect can be exhibited in reducing the circuit scale.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram in an embodiment of an information encoding apparatus according to the present invention.
FIG. 2 is a circuit block diagram of a conventional information encoding apparatus.
[Explanation of symbols]
10 Ring Buffers 11-16 Convolutional Coding Circuits 11a-16a Arithmetic Circuits 11b-16b Arithmetic Circuits 17, 18, 19 Multiplexer

Claims (5)

An n-bit (0 to n-1) ring buffer capable of inputting n-bit data including a termination code in parallel;
N / 2 convolutional encoding circuits for performing convolutional encoding on the bits of data input to the even number of the ring buffer;
A multiplexer that inputs the bits generated by each of the convolutional encoding circuits in parallel and sequentially outputs the bits;
An information encoding apparatus comprising: An n-bit (0 to n-1) buffer capable of inputting n-bit data including a termination code in parallel;
N / 2 first convolutional encoding circuits for performing convolutional encoding on the bits of data input to the even number of the buffer;
N / 2 second convolutional encoding circuits for performing convolutional encoding on bits of data input to odd numbers of the buffer;
A multiplexer that inputs the bits generated by the first and second convolutional encoding circuits in parallel and sequentially outputs the bits;
An information encoding apparatus comprising: 3. The information encoding apparatus according to claim 1, wherein each of the convolutional encoding circuits has a constraint length of 3 and an encoding rate of 1/2. The multiplexer is
A first multiplexer having one output of each of the convolutional coding circuits as an input;
A second multiplexer having the other output of each of the convolutional coding circuits as an input;
A third multiplexer receiving the outputs of the first and second multiplexers;
The information encoding apparatus according to claim 3, further comprising: Inputting n-bit data including a termination code in parallel to an n-bit (0 to n-1) ring buffer;
A step of performing convolutional encoding in parallel on the bits of data input to the even number of the ring buffer;
Inputting the bits generated by the convolutional encoding in parallel to a multiplexer and sequentially outputting the serially;
Shifting the data input to the ring buffer by 1 bit;
A step of performing convolutional encoding in parallel on the bits of data input to the even number of the buffer;
Inputting the bits generated by the convolutional encoding in parallel to a multiplexer and sequentially outputting the serially;
An information encoding method comprising:

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