JP2011248591A - Bit rearrangement circuit and test device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize a data bit rearrangement circuit and/or reduce power consumption of the same.SOLUTION: An input flip-flop 10 sequentially holds word data Dincluding consecutive m bits in input data Dwith (m×n) bits as a unit. A plurality of decoder circuits DECare provided in each bit of word data D, and each of decoder circuits DECreceives a bit corresponding to the word data and storage destination data indicating a position after rearrangement, and generates decode data Dwith the (m×n) bits. The decode data Dhas all bits as 0 when the corresponding bit is 0, and has the bit corresponding to the position after the rearrangement as 1 and the remaining bits as 0. A memory circuit 20 includes a storage area of the (m×n) bits, receives m number of pieces of decode data D, and writes 1 in the bit of the storage area which corresponds to the bit where each 1 of the decode data is stored in.

Description

  The present invention provides a circuit capable of rearranging each bit of a serial data signal in an arbitrary order.

  A device such as a CMOS image sensor outputs data indicating the luminance of each captured pixel (referred to as pixel data) as serial data. Here, each pixel data is variously 8, 10, 12, 14, 16 bits.

  Here, the pixel data from the CMOS image sensor is not necessarily arranged continuously. FIG. 1 is a diagram illustrating an example of a bit arrangement when pixel data is 12 bits. In this example, the output data of the CMOS image sensor is composed of 3 bytes (24 bits) as one group.

  The interface circuit that receives the output data of the CMOS image sensor needs to rearrange serial data including a plurality of continuous pixel data and to separate the data for each pixel. In the example of FIG. 1, 3 bytes are one repeating unit, but there are devices having 8 or 16 repeating bytes.

Japanese Patent Laid-Open No. 10-164596 JP 2010-28241 A

  For example, in order to arbitrarily rearrange serial data having a repetition bit number of 16 bytes (128 bits), 128 multiplexers (selectors) having 128 inputs and 1 output (128 to 1) may be provided. Alternatively, 128 demultiplexers having 1 input and 128 outputs (1 to 128) may be provided.

  However, if 128 multiplexers are arranged, the circuit area becomes enormous and the power consumption of the circuit also increases. In particular, when an interface circuit is configured using an FPGA (Field Programmable Gate Array), the problem becomes remarkable.

  An embodiment of the present invention has been made in view of the above problems, and one of exemplary purposes thereof is to reduce the size and / or power consumption of a data bit rearrangement circuit.

One embodiment of the present invention relates to a bit rearrangement circuit that rearranges input data in units of (m × n) bits (m and n are natural numbers) in an arbitrary order. The bit rearrangement circuit includes an input flip-flop that sequentially holds word data including consecutive m bits in the input data, and a storage that indicates a position after the rearrangement of each of (m × n) bits included in the input data. A storage destination data memory for holding the destination data, m decoder circuits, and a memory circuit are provided.
The m decoder circuits are provided for each bit of the word data, and receive storage destination data indicating the corresponding bit of the word data and the rearranged position. Each decoder circuit generates decode data having (m × n) bits. When the corresponding bit input to a certain decoder circuit is 0, all bits of the decoded data are 0. When the corresponding bit to be input is 1, the decoded data is 1 for the bit corresponding to the rearranged position and 0 for the remaining bits.
The memory circuit includes an (m × n) -bit storage area, receives decode data from each of the m decoder circuits, and sets 1 to the bit of the storage area corresponding to the bit in which 1 of each decode data is stored. Write.

  According to this aspect, each bit of input data can be rearranged in an arbitrary order. Even if the number of bits of input data is large, it is not necessary to use an enormous multiplexer or demultiplexer, so that the circuit area can be reduced and / or the power consumption can be reduced.

The memory circuit includes a (m × n) -bit flip-flop that is a storage area, a first logic gate that generates a logical sum of (m × n) -bit decoded data from m decoder circuits, and a flip-flop A second logic gate that generates a logical sum of the output data and the output data of the logic gate. The output data of the second logic gate may be written into the flip-flop.
The decoded data is updated each time new word data is input. According to this configuration, the data of the flip-flop can overwrite the value of new decoded data while maintaining the state of the bit once asserted.

  The input data may be image data including a plurality of pixels. The bit rearrangement circuit may further include a pixel cutout circuit that cuts and outputs the data stored in the flip-flop by the number of bits of one pixel for each cycle of the input data.

Another aspect of the present invention is a test apparatus. This apparatus includes the bit rearrangement circuit described above.
According to this aspect, it is possible to test devices under test having various output formats.

  It should be noted that any combination of the above-described constituent elements, and those in which constituent elements and expressions of the present invention are mutually replaced between methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, a small and / or low power consumption bit rearrangement circuit can be provided.

It is a figure which shows an example of a bit arrangement | sequence in case pixel data is 12 bits. It is a circuit diagram which shows the structure of the bit rearrangement circuit which concerns on embodiment. It is a figure which shows the structure of the test apparatus using the bit rearrangement circuit of FIG.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected in addition to the case where the member A and the member B are physically directly connected. It includes the case of being indirectly connected through another member that does not affect the connection state. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

FIG. 2 is a circuit diagram showing a configuration of the bit rearrangement circuit 100 according to the embodiment.
The bit rearrangement circuit 100 receives input data D _IN [1: m × n] in units of (m × n) bits (m and n are natural numbers), and rearranges them in an arbitrary order designated. Output. In this embodiment, m = 8 bits. n is variable and can take any value from 1 to 16, for example.

Input data _{D IN} is divided into n words of data _D WD1 _{to D WDn.} Word data _{D WD} includes m successive bits of the input data _{D IN.} Word data _{D WD1, D WD2, ... D} WDn is sequentially input in parallel form to the input terminal _{P IN} of the bit rearrangement circuit 100. The data valid terminal of the bit rearrangement circuit 100, a data valid signal Data_valid that is asserted whenever a new word data _{D WD} is inputted is inputted.

Bit rearrangement circuit 100, in order to sort the one of the input data D _IN, repeats the same signal processing for n word data D _WD. Here, for easy understanding, a value j (1 ≦ j ≦ n) indicating what number of word data _DWD the bit rearrangement circuit 100 is currently processing is introduced.

The bit rearrangement circuit 100 includes an input flip-flop 10, flip-flops 11 a to ₁₁ c, a storage destination data memory (Destination Memory) 12, a memory address counter 14, decoder circuits DEC _{1 to} DEC _m , a memory circuit 20, a flip-flop 23, and a pixel A clipping circuit 30 is provided.

  A clock signal CLK to be synchronized is supplied to each logic gate and circuit block of the bit rearrangement circuit 100. The flip-flops 11a to 11c and the flip-flop 23 are provided to synchronize the timing of each signal.

The input flip-flop 10 holds m-bit word data D _WDj [1: m] sequentially input every cycle j. The i-th bit D _WDj [i] of the word data D _WDj corresponds to the (j−1) × m + i-th bit of the input data D _IN .
D _WDj [i] = D _IN [(j−1) × m + i]

Storage destination data memory 12 holds the storage destination data DEST indicating the position after input data D _IN (m × n) bits of each sort. Each of the storage destination data DEST has L bits (L = log ₂ (m × n)). In the present embodiment, the storage destination data DEST is 7 bits (= log ₂ (128)). The storage destination data corresponding to the k-th bit D _IN [k] of the m × n-bit input data D _IN is denoted as DEST _k .

  The storage destination data memory 12 can be freely rewritten by the user of the bit rearrangement circuit 100 according to the rearrangement rule. When switching a plurality of sorting rules is possible, storage destination data may be prepared for each rule, and the storage destination data to be used may be selected from the storage destination data.

The storage destination data memory 12 simultaneously outputs m pieces of storage destination data DEST corresponding to each of m bits constituting the word data _DWD currently input to the bit rearrangement circuit 100 by one reading. That is, the output bus width of the storage destination data memory 12 is m × L bits.

The storage destination data memory 12 includes a terminal A for controlling the storage destination data DEST to be output. The memory address counter 14 _supplies a control signal (address count) S 1 corresponding to the word data _DWD currently input to the bit rearrangement circuit 100 to the terminal A of the storage destination data memory 12. The address count S1 indicates a number (j−1) that is 1 smaller than the cycle number j described above. The memory address counter 14 receives a data valid signal Data_valid, an address reset signal ADD_RST, and a word number signal NUM_WORD. Word number signal NUM_WORD is data indicating a smaller value (n-1) by the number n of the word data _{D WD} included in the input data _{D IN,} when the maximum value of n is 16, is represented by 4 bits . NUM_WORD = [1111] indicates n = 16, and NUM_WORD = [0000] indicates n = 1.

  The memory address counter 14 repeatedly counts up the address count S1 in the range of 0 to (n−1). That is, the memory address counter 14 counts the number of cycles j (= 1 to n).

Address reset signal ADD_RST is a signal for synchronization with the count value of the input data D _IN and the memory address counter 14, first one, is asserted. When the address reset signal ADD_RST is asserted, the memory address counter 14 initializes the address count S1 to its maximum value (n−1). Subsequently, when the first data valid signal Data_valid is asserted, the address count S1 returns to zero, and then the address count S1 is incremented by 1 each time the data valid signal Data_valid is asserted. When the address count S1 reaches the value (n-1), it returns to zero again.

Storage destination data memory 12 outputs an address count S1, the head of m storage destination data _{DEST (j-1) × m} + 1 ~DEST (j-1) × m + m.

Decoder circuits DEC _{1 to} DEC _m are provided for each bit of word data _DWDj . The i-th decoder circuit DEC _i receives the bit D _WDj [i] corresponding to the word data D _WDj and the storage destination data DEST _{(j−1) × m + i} indicating the rearranged position. The i-th decoder circuit DEC _i generates (m × n) -bit decoded data D _DECi . When the input bit D _WDj [i] is 0 (value indicating false), the decoder circuit DEC _{i sets} all bits of the decoded data D _DECi to 0. When the input bit D _WDj [i] is 1 (value indicating true), the decoder circuit DEC _i sets the bit corresponding to the rearranged position in the decoded data D _DECi to 1 and the remaining bits. 0.

For example, it is assumed that the position after the rearrangement of the third bit of the word data _DWDj is the 64th from the beginning. In this case, the value of the storage destination data DEST _{(j−1) × m + 3} is 64. When the value of the third bit of the word data _DWDj is 1, the decoder circuit DEC ₃ outputs decoded data D _{DEC3 in} which 1 is stored in the 64th bit out of 128 bits and 0 is stored in the rest.

The memory circuit 20 includes a storage area of (m × n) bits. In FIG. 2, this storage area is a flip-flop 22. The memory circuit 20 receives the decoded data D _{DEC1 to} D _DECm from each of the _m decoder circuits DEC _{1 to} DEC _m . The memory circuit 20 writes 1 to the bit of the storage area corresponding to the bit in which 1 of each of the decode data D _{DEC1 to} D _DECm is stored.

For example, it is _assumed that 1 is stored in the third bit of D _DEC1 , 1 is stored in the 62nd bit of D _DEC2 , and all bits of D _{DEC3 to} D _DECm are 0. At this time, 1 is written in the third and 62nd bits of the flip-flop 22.

Specifically, the memory circuit 20 includes a first OR gate 24, a second OR gate 26, and an AND gate 28 in addition to the flip-flop 22.
The first OR gate 24 generates a logical sum of (m × n) -bit decoded data D _{DEC1 to} D _DECm from the _m decoder circuits DEC _{1 to} DEC _m .
The second OR gate 26 generates a logical sum of the output data of the flip-flop 22 and the output data of the first OR gate 24. The output data of the second OR gate 26 is written into the flip-flop 22.
With this configuration, the bit in which the value 1 is once stored is held thereafter in the flip-flop 22, and when 1 is newly generated in another bit, 1 is added to the bit.

The flip-flop 22 is cleared at the beginning of the cycle of the input data _DIN . For this purpose, the memory circuit 20 includes an AND gate 28.
The memory address counter 14 generates a control signal S2 that instructs the flip-flop 22 to be cleared. The memory address counter 14 asserts (= 0) the control signal S2 every time the address count S1 = 0. When the control signal S2 = 0 is input, data stored in the flip-flop 22 is masked by the AND gate 28, the flip-flop 22 is newly input decoded data _D DEC1 _{to D DECm} is written. In this way, the flip-flop 22 is reset every cycle.

When the input data _DIN is image data including a plurality of pixels, a pixel cutout circuit 30 is provided. Pixel extracting circuit 30, for each period of the input data D _IN, the data stored in the flip-flop 22, and outputs the cut in the number of bits of one pixel. A control signal S3 indicating the timing of carving is generated by the memory address counter 14. Specifically, the control signal S3 is asserted every time the address count S1 reaches (n−1).

Also in the pixel extraction circuit 30, a pixel length of (number of bits) and data PIX_LEN showing a p, data PIX_NUM indicating the number q of pixels included in one of the input data _{D IN} is input. For example, when the number of bits p of one pixel is variable as 8, 10, 12,..., 24 bits, the data PIX_LEN is 5 bits. When the number of bits of one pixel is variable in units of one byte, for example, when it is variable by 8, 16, 24 bits, the data PIX_LEN may be data indicating the length (number of bytes) of one pixel. PIX_LEN can be 2 bits.
Also, for example, when the number q of pixels included in the input data _{D IN} is variable in the range of 1 to 16, the data PIX_NUM is 4 bits. The pixel cutout circuit 30 outputs q pixel data from the output data of the flip-flop 22 in units of p bits.

The above is the configuration of the bit rearrangement circuit 100. Next, the operation will be described.
Now, the bit rearrangement circuit 100, and the input data _{D IN} to m = 8, n = 16,128 bits units are input. At this time, the word number signal NUM_WORD is set to a value indicating n = 16. Further, at the timing before the input data _{D IN} is input, the address reset signal ADD_RST is asserted, the count value S1 of the memory address counter 14 is initialized to (n-1).

The bit rearrangement circuit 100, the first word data _{D WD1} is input, it along with the data valid signal Data_valid is asserted. In response to this, the memory address counter 14 sets the count value S1 to zero. The bit rearrangement circuit 100 writes each bit of the word data _DWD1 to a corresponding position (bit) of the flip-flop 22.

Subsequently, word data D _WD2 , D _WD3 ,... _Are input, and each time the data valid signal Data_valid is asserted, the address count S1 of the memory address counter 14 is incremented. Then, bits included in each word data D _WD2 , D _WD3 ,... _Are written in appropriate positions of the flip-flop 22.

When the writing processing for all the word data D _WD1 to D _WDn is completed, it is possible to flip-flop 22, to obtain a bit sequence rearranged according collation rules stored input data D _IN in the memory address counter 14. At this time, the address count S1 of the memory address counter 14 becomes (n-1), and the control signal S3 is asserted. In response to this, the rearranged bit string stored in the flip-flop 22 is extracted by the pixel cutout circuit 30 as data for each pixel and output to the subsequent stage.

Thus, according to the bit rearrangement circuit 100 of FIG. 2, it is possible to sort the input data D _IN in any order. The circuit area of the bit rearrangement circuit 100 is much smaller than when using m × n multiplexers, and the power consumption of the circuit can be reduced.

  Next, a preferred application of the bit rearrangement circuit 100 will be described. FIG. 3 is a diagram showing a configuration of a test apparatus using the bit rearrangement circuit 100 of FIG. The DUT 1 is an imaging device such as a CMOS sensor, and outputs image data including pixel data indicating the luminance of each pixel in a serial format. As already described, the arrangement of the pixel data in the image data varies depending on the type of DUT 1 and the number of bits of each pixel.

  The test apparatus 2 receives the image data from the DUT 1, rearranges it appropriately, and after dividing it into data for each pixel, frame data corresponding to one screen is formed. Then, using image processing, it is determined whether or not the frame data matches the expected value, whether the DUT 1 is good or bad, or the defective portion is specified. Or you may determine whether the brightness | luminance of each pixel corresponds with an expected value.

The test apparatus 2 includes a level comparator CP, a latch (timing latch) TL, a buffer memory BUF, a bit rearrangement circuit 100, and a logical comparator DC.
The level comparator CP compares the image data (bit string) from the DUT 1 with a predetermined threshold voltage to determine a high level or a low level. The timing latch TL latches data indicating the determination result of the level comparator CP in synchronization with the clock signal CLK. The buffer memory BUF is a FIFO, for example, and holds serial image data.

The image data stored in the buffer memory BUF, for each input data D _IN is a unit including a plurality of pixels is input to the subsequent bit rearrangement circuit 100. Bit rearrangement circuit 100, the input data _{D IN} pixel data _{D PIX1, D PIX2,} carving ... to. Logic comparator DC, by applying operation to the constituted frame data of a plurality of pixel data _{D PIX,} outputs a pass-fail data PASS / FAIL indicating whether DUT1 is functioning properly. The pass / fail data is written in a fail memory (not shown).

  By using the bit rearrangement circuit 100 of FIG. 2, the test apparatus 2 can test the DUT 1 that outputs image data of various arrangements for a general purpose.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications may exist in each of those constituent elements, each processing process, and a combination thereof. Hereinafter, such modifications will be described.

  In the embodiment, the case where “true value” is assigned to 1 and “false value” is assigned to 0 in the digital signal processing has been described. It is included in the scope of the present invention.

  In the embodiment, the case where m = 8 has been described, but the value of m is not limited, and m can be any value such as 1, 2, 4 or the like.

  In the embodiment, rearrangement of image data has been described as an example. However, the use of the bit rearrangement circuit 100 is not limited thereto, and can be used for rearrangement of various bit strings. Although the test apparatus has been described as an example of the use of the bit rearrangement circuit 100, the bit rearrangement circuit 100 can be used for a DSP that is mounted on an electronic device including the image sensor that is the DUT 1 and processes a signal from the image sensor.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and changes in the arrangement are allowed within the range not to be performed.

DESCRIPTION OF SYMBOLS 10 ... Input flip-flop, 11 ... Flip-flop, 12 ... Storage destination data memory, 14 ... Memory address counter, DEC ... Decoder circuit, 20 ... Memory circuit, 22, 23 ... Flip-flop, 24 ... First OR gate, 26 ... First 2OR gate, 28 ... AND gate, 30 ... pixel extraction circuit, 100 ... bit rearrangement circuit, 1 ... DUT, 2 ... test device, 4 ... timing comparator.

Claims (4)

An input flip-flop that sequentially holds word data including consecutive m bits among input data in units of (m × n) bits (m and n are natural numbers);
A storage destination data memory that holds storage destination data indicating positions after rearrangement of each (m × n) bits included in the input data;
M decoder circuits provided for each bit of the word data, each receiving the corresponding bit of the word data and the storage destination data indicating the rearranged position, and (m × n) bits When the corresponding bit is 0, all bits are 0, and when the corresponding bit is 1, the bit corresponding to the rearranged position is 1, and the remaining bits are 0 M decoder circuits for generating decode data;
A memory that includes a (m × n) -bit storage area, receives decoded data from each of the m decoder circuits, and writes 1 to the bit in the storage area corresponding to the bit in which 1 of each decoded data is stored Circuit,
A bit rearrangement circuit comprising: The memory circuit includes:
(M × n) -bit flip-flop as the storage area;
A first logic gate for generating a logical sum of the (m × n) -bit decoded data from the m decoder circuits;
A second logic gate for generating a logical sum of the output data of the flip-flop and the output data of the first logic gate;
The bit rearrangement circuit according to claim 1, wherein output data of the second logic gate is written to the flip-flop. The input data is image data including a plurality of pixels,
The bit rearrangement circuit further comprises a pixel cutout circuit that cuts out and outputs the data stored in the flip-flop by the number of bits of one pixel for each cycle of the input data. The bit rearrangement circuit according to 2.   A test apparatus comprising the bit rearrangement circuit according to claim 1.

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