JPH06225185A - Picture processing unit - Google Patents

Abstract

PURPOSE:To prevent with less number of components by using selectively a clock signal obtained by frequency-dividing an original clock at a clock generator for a clock signal of an analog system circuit and a digital system circuit. CONSTITUTION:An original clock fHz generated by a clock oscillating circuit 1 is inputted to a clock generator 2, from which clocks fclk1-fclk2n whose phases differ from each other and they are inputted to a phase selection section 3. Then the phase selection section 3 selects a clock signal so as to reduce the interference between an analog system circuit 4 and a digital system circuit 5 and the selected signal is fed to them respectively. Practically an original clock from the clock generator 2 is inputted to the analog system circuit 4 or the digital system circuit 5 through fixed connection. The phase selection section 3 selects a clock signal to the analog system circuit 4 or a clock signal to the digital system circuit 5.

Description

Detailed Description of the Invention

[0001]

The present invention is used in image processing.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing device in which an analog circuit integrated with a CCD camera and a digital circuit are mixed to perform clock synchronization.

[0002]

2. Description of the Related Art Analogues such as conventional image processing devices
In the digital mixed circuit, separate clock signals are used for the analog system circuit and the digital system circuit, and the following four methods have been mainly used to prevent the crosstalk itself.

1) Strengthening of GND (grounding).

2) Dealing with decoupling.

3) The frequency component of the digital system circuit is trapped by the analog system circuit.

4) Board division of analog circuits and digital circuits.

[0007]

In such a conventional analog / digital mixed circuit, the above-mentioned four measures have been taken, but decoupling requires a component such as a capacitor or a coil, The method of splitting required an extra connector. Even when not specifically divided, the circuit pattern is restricted by dividing the area on the board, which increases the board size and requires an analog circuit and a digital circuit as clock signal oscillators. I was there.

As described above, in order to eliminate the crosstalk itself, extra circuit parts and a board size are required, which makes it difficult to downsize the circuit.

The present invention solves such a problem, and an object thereof is to provide a device capable of preventing crosstalk with a small number of components.

[0010]

The present invention provides an image processing apparatus having an analog circuit and a digital circuit,
One clock oscillating circuit, a clock generator for generating and outputting a plurality of clock signals having different phases at frequencies corresponding to the analog system circuit and the digital system circuit according to the clock oscillation circuit output original clock, and the clock generator And a phase selector for selectively outputting the plurality of clock signals output from the analog circuit and the digital circuit.

The phase selection unit includes means for selecting, fixing and outputting the clock signals output to the analog system circuit and the digital system circuit so as to form a combination having a small mutual influence, and the digital system circuit includes A central processing unit that fixes the clock signal from the clock generator as a reference and outputs a selector control signal to the phase selection unit to supply the clock signal to the analog circuit can be included.

[0012]

[Function] Both analog and digital circuits
A common clock signal from the same oscillator is supplied via the clock generator and the phase selector. In this way, the same clock oscillator that oscillates from the same clock oscillator is used for the analog circuit and the digital circuit, and the clock signal of the cycle and phase that is not affected by the clock noise generated from the digital circuit is generated by the clock generator. Then, by operating the analog circuit, it is possible to select the clock signals of the analog circuit and the digital circuit that do not cause a problem even when there is crosstalk.

[0013]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing the basic configuration of the embodiment of the present invention.

The embodiment of the present invention includes an analog system circuit 4 and a digital system circuit 5. Further, as a feature of the present invention,
A clock oscillating circuit 1 for generating a source clock commonly applied to the analog circuit 4 and the digital circuit 5,
A clock generator 2 for generating and outputting a plurality of clock signals having different phases at frequencies corresponding to the analog system circuit 4 and the digital system circuit 5 according to the original clock from the clock oscillation circuit 1, and the clock generator 2 And a phase selector 3 for selectively outputting a plurality of clock signals to the analog system circuit 4 and the digital system circuit 5.

Next, the operation of the embodiment of the present invention thus constructed will be described with reference to the drawings.

The original oscillation clock fHz generated by the clock oscillation circuit 1 is input to the clock generator 2 to generate clocks fclk1 to fclk2n having different phases and input to the phase selector 3. Analog circuit 4 in phase selector 3
A clock signal is selected and output to each so that the mutual influence of the digital circuit 5 and the digital circuit 5 is reduced.

In practice, the base clock from the clock generator 2 is fixedly connected to the digital circuit 5 or the analog circuit 4 and input. The phase selector 3 selects a clock signal for the analog circuit 4 or
Alternatively, the clock signal to the digital circuit 5 is selected.

FIG. 2 is a basic block diagram showing an example of application of the embodiment of the present invention to a mass production machine.

In this case, the phase selection unit 3 includes means for selecting and fixing the clock signals output to the analog system circuit 4 and the digital system circuit 5 so that they have a small influence on each other and fixing and outputting them.

The phase selector 3 is fixedly connected to the analog circuit 4
And clock signals fclkA, f to the digital circuit 5
Supply clkD. However, the spare clock signals fclk3 to fclk2n are also output from the clock generator 2 in consideration of the machine difference.

FIG. 3 is a diagram for explaining the configuration and operation when the digital circuit according to the embodiment of the present invention controls the phase selector.

In this case, the central processing unit that fixes the clock signal from the clock generator 2 to the digital system circuit 5 as a reference, outputs the selector control signal to the phase selection unit 3 and supplies the clock signal to the analog system circuit 4. 6 and the image processing unit 7 are included.

In operation, the clock signal fclkD from the clock generator 2 to the digital system circuit 5 is fixedly connected, and the clock signal supplied to the analog system circuit 4 is connected to the analog system circuit 4 via the phase selection unit 3. A selector control signal is applied from the central processing unit 6 to the phase selection unit 3, and a clock signal which is less affected by crosstalk is selected by the signal and connected to the analog circuit 4.

FIG. 4 is a diagram for explaining the configuration and the operation in the case of applying a combination of clock signals having a small mutual influence to the respective constituent means of the analog system circuit and the digital system circuit in the embodiment of the present invention.

As shown in FIG. 4, the digital system circuit 5 receives a digital video signal from the phase selection unit 3 and controls the image processing, and the central processing unit 6 controls the image processing. An image processing unit 7 is included, and a CCD camera unit 8 that outputs a captured image as an analog video signal to the analog system circuit 4 and an analog video signal from the digital system circuit 5 are input and a video output signal is output. The output analog section is included, and the analog system circuit 4 and the digital system circuit 5 convert the analog video signal from the CCD camera section 8 into a digital video signal to convert the image processing section 7 into a digital video signal.
Is connected to the A / D conversion unit 9 for outputting to the A / D conversion unit and the D / A conversion unit for converting the digital video signal from the image processing unit 7 into an analog video signal and outputting the analog video signal to the output analog unit 11.

The clock generator 2 receives the original clock generated by the clock oscillation circuit 1 and inputs fclk1 to fclk.
Eight kinds of phase-shifted clocks of lk8 are output. In this embodiment, the analog clock signal for the CCD camera unit 8 is fixed and the clock signal for each unit is selected. That is, fclk1 is used as a reference clock signal and a drive clock signal for the CCD camera unit 8 is used, and fclk
Connect k1. After that, this connection is fixed.

The CCD camera unit 8 has a clock signal fc.
Clock noise and bus noise synchronized with lkA may occur. In order to avoid this, the A / D converter 9,
A clock signal to the image processing unit 7 and the D / A conversion unit 10 is selected from fclk1 to fclk8, and a clock signal less susceptible to noise is searched for and connected.

FIG. 5 is a diagram showing a clock signal in the phase selection section of the image processing apparatus with a built-in micro camera shown in FIG. Further, FIG. 6 is a diagram showing a waveform when noise due to crosstalk is not present when the microminiature camera integrated image processing apparatus shown in FIG. 4 is operated, and FIG. 7 is a waveform when noise due to crosstalk is present. FIG.

The CCD camera unit 8 has fclkA = fcl
It operates at k1, and the waveform of the output analog video signal is as shown in FIG. 6A due to the influence of analog drive noise. At this time, the A / D conversion unit 9 should select a stable portion of the analog signal as a sample & hold point, so that it can be selected within a range of fclkAD = fclk5 to fclk7 if a certain time is required after the clock starts. Further, in the digital clock fclkD, when crosstalk noise appears in the analog video at 1/4 cycle after rising and 1/8 cycle after falling, from these, when fclkA = fclk1, fclkAD = fcl
When k7 and fclkD = fclk6 are selected, noise is not added to the digital video signal.

On the other hand, as shown in FIG. 6B, fclkD
When = fclk4 is selected, the noise jump of the analog video signal from fclkD coincides with the sample & hold timing, and the influence increases.

[0031]

As described above, according to the present invention, a clock signal obtained by dividing the original clock by the clock generator is selected and used as a clock signal for each circuit, which causes a problem even when crosstalk occurs. Since it is possible to reduce the number of components used for preventing crosstalk, it is possible to configure the image processing apparatus with a small size and low cost.

Further, arbitration between image capturing and digital image processing in parallel, serial access of video data in the image memory, and random access for image processing is facilitated, and these control circuits are greatly simplified. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of an embodiment of the present invention.

FIG. 2 is a basic block diagram showing an application example to a mass production machine in the embodiment of the present invention.

FIG. 3 is a diagram for explaining a configuration and an operation when a digital circuit according to an embodiment of the present invention controls a phase selection unit.

FIG. 4 is a diagram for explaining a configuration and an operation when a combination of clock signals having a small mutual influence is given to each component of the analog system circuit and the digital system circuit in the embodiment of the present invention.

5 is a diagram showing a clock signal in a phase selection unit of the image processing apparatus with the microminiature camera shown in FIG.

FIG. 6 is a diagram showing a waveform when noise due to crosstalk does not occur when the microminiature camera integrated image processing apparatus shown in FIG. 4 is operated.

7 is a diagram showing a waveform when noise due to crosstalk occurs when the microminiature camera integrated image processing device shown in FIG. 4 is operated.

[Explanation of symbols]

 1 clock oscillation circuit 2 clock generator 3 phase selection unit 4 analog system circuit 5 digital system circuit 6 central processing unit 7 image processing unit 8 CCD camera unit 9 A / D conversion unit 10 D / A conversion unit 11 output analog unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroki Yamaguchi 1-1-1, Shinurashima-cho, Kanagawa-ku, Yokohama, Kanagawa Prefecture NEC Robot Engineering Co., Ltd.

Claims (3)

[Claims] 1. An image processing apparatus including an analog circuit and a digital circuit, wherein one clock oscillation circuit and each of the analog circuit and the digital system circuit according to an output original clock of the clock oscillation circuit. A clock generator that generates and outputs a plurality of clock signals having different phases at corresponding frequencies, and a phase selector that selectively outputs the plurality of clock signals output from the clock generator to the analog system circuit and the digital system circuit. An image processing apparatus comprising: 2. The phase selection unit includes means for selecting, fixing, and outputting clock signals output to the analog circuit and the digital circuit so that the clock signals output from the analog circuit and the digital circuit have a small influence on each other. Image processing device. 3. The digital system circuit includes a central processing unit that fixes the clock signal from the clock generator as a reference, outputs a selector control signal to the phase selection unit, and supplies the analog system circuit with the clock signal. The image processing apparatus according to claim 1.