KR0142261B1 - Digital sine wave generation method and circuit - Google Patents

Abstract

The present invention relates to an apparatus for generating a clock required in a digital signal processing system, and more particularly, to a method and a circuit for generating a digital sine wave. According to an embodiment of the present invention, a phase accumulator which receives phase information and generates a accumulated phase value, a phase calculator which receives phase conversion data and generates first phase data in addition to a phase value applied from the phase accumulator, and the phase A control unit generating first phase data from the information and phase calculating unit and generating a plurality of phase data, a plurality of memories receiving the phase data, respectively, and outputting a sine value, and a signal applied from the memories It is provided with a multiplexer for switching to and outputting. In the prior art, at least four times the reference clock is required to generate a high frequency sine wave, while the present invention can obtain the same output frequency as that of the reference clock. In addition, since four times the number of samples can be obtained even when generating the same output frequency, it is possible to obtain a relatively high reliability sinusoidal wave during digital / analog conversion. Therefore, the digital sinusoidal wave generation circuit according to the present invention has the effect of realizing a product at low cost while improving reliability.

Description

Digital sine wave generation method and circuit

1 is a block diagram showing a general digital sinusoidal wave generation circuit,

2 is a block diagram showing a digital sinusoidal wave generating circuit according to an embodiment of the present invention;

3 shows a multiplexer input / output signal waveform when an output sine wave with the same frequency as the reference clock is obtained.

4 is a signal waveform diagram for comparing the output sine wave according to an embodiment of the present invention with the prior art.

* Explanation of symbols for main parts of the drawings

10: phase accumulation part 20: phase calculation part

32, 34, 36, 38: first to fourth memory 40: control unit

50: multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit, and more particularly, to a digital sine wave generation method and a circuit capable of generating a clock having the same frequency as a reference clock and increasing the number of sampling to increase the reliability of an output waveform.

1 shows a general digital sinusoidal wave generation circuit. First, the phase accumulator 10 receives phase information DELTA P in order to make a clock of a constant frequency. Then, the phase accumulation unit 10 accumulates and outputs phase information DELTA P at each rising edge of the reference clock fref. That is, when the phase information ΔP is 90 ° ( ΔP = 90 °), the phase accumulator 10-this output is 0 °, 90 °, 180 °, 270 °, 0 °, 90 °,... Will increase as The phase operation unit (Phase ALU) 20 receives the phase conversion data P _D and adds it to the phase value output from the phase accumulation unit 10. The phase calculator 20 thus acts as a phase converter for shifting the output phase of the phase accumulator 10 by P _D. Then, the memory (Sine Look-Up Table) 30 outputs a sine value corresponding to the phase output from the phase calculator 20. In this way, by converting the sinusoidal wave output as a digital value into an analog signal and amplifying it to an appropriate size, it can be used as a digital system clock.

The above-mentioned general digital sine wave generator circuit is disclosed in a Numerically Controlled Oscillator (NCO) product of Stanford Telecom.

As described above, at least four sample values are required to convert the digital sine wave into an analog to implement a complete sine wave. However, in the above-described general digital sine wave generation circuit, the output frequency fout is ΔP cannot exceed 90 ° in order to obtain more than 4 sample values per cycle. Therefore, the maximum frequency of the sinusoidal wave that can be generated from the above-described conventional circuit is Becomes However, clocks required in digital high-definition television (Digital-HDTV) or digital communication systems are mostly 20 MHz or more. As described above, in order to obtain a clock of 20 MHz or more, the reference clock f _ref is required to be a high frequency signal of 80 MHz or more. However, in most NCO products, the reference frequency (f _ref ) is within 40 MHz, and some products operating at 40 MHz or more have a very expensive problem.

An object of the present invention for solving the above problems is to provide a digital sine wave generation method that can obtain a sine wave of the same frequency as the reference frequency at the maximum.

Another object of the present invention is to provide a digital sine wave generation method which can improve reliability by increasing the number of samplings per cycle even with a clock having the same frequency.

Another object of the present invention is to provide an apparatus implementing the above-described method.

According to an aspect of the present invention, a method for generating a digital sine wave includes: accumulating phases according to phase information, converting a phase to the accumulated phase values, and generating first phase data; And a step of outputting the respective sine values, and sequentially outputting the sine values.

Another object of the present invention is a device for generating a digital sine wave, comprising: a phase accumulator for inputting phase information and generating a accumulated phase value; A phase calculator for generating phase data, a controller for generating first phase data from the phase information and the phase calculator, and a plurality of memories for receiving the phase data and outputting corresponding sine values respectively; And a multiplexer for sequentially converting and outputting signals applied from the memories.

Hereinafter, the present invention will be described in detail with reference to FIGS. 2 to 4.

2 is a block diagram showing a digital sine wave generating circuit according to a preferred embodiment of the present invention. As shown in FIG. 2, the phase accumulator 10 receives phase information ΔP . The phase accumulator 10 outputs the accumulated phase values by the phase information ΔP . The phase operation unit 20 that moves the phase according to the phase conversion data P _D received from the outside is connected to the output terminal of the phase accumulation unit 10. A first memory 32 that outputs a sine value for the first phase data P1 supplied from the phase calculator 20 is connected to an output terminal of the phase calculator 20.

On the other hand, the phase information ΔP is also input to the controller 40. The control unit 40 also receives the output signal of the phase calculating unit 20 and from this ¼ times the phase information ΔP ( Each of the phase data P2 to P4 separated by) is generated. The second to fourth memories 32 to 38 are respectively connected to the output terminal of the controller 40. In addition, a 4: 1 multiplexer 50 that sequentially selects and outputs these signals is connected to an output terminal of the first to fourth memories 32 to 38.

A reference clock f _ref is input to each component except the multiplexer 50. The multiplexer 50 is input with a reference clock 4f _ref having a frequency value four times the reference clock f _ref input to each component.

The operation of the above-described second apparatus is described in more detail as follows.

In FIG. 2, first, the phase cumulative beam 10 outputs the phase information DELTA P at the rising edge of the reference clock f _ref in addition to the phase of the previous output fed back. The phase calculator 20 adds and outputs phase conversion data P _D to the accumulated phase values supplied from the phase accumulator 10. The first phase data P1 output through the phase accumulator 10 and the phase calculator 20 is expressed as follows.

P1 = P _D mod (∑ ΔP)

Where mod () is modulo for 360 °

The control unit 40 receives the first phase data P1 and the phase information ΔP to generate three phase data P2 to P4. Here, three phase data P2 to P4 are expressed as follows.

For example, ΔP = 90 ° and P _D = 0 ° (P1, P2, P3, P4) = (0 °, 22.5 °, 45 °, 67.6 °), (90 °, 112.5 °, 135 °, 157.5 °), (180 °, 202.5 °, 247.5 °), (270 °, 292.5 °, 315 °, 337.5 °), (0 °, 22.5 °, 45 °, 67.5 °),... … Becomes The phase data P1 to P4 are respectively input to the first to fourth memories 34 to 38 as address signals, and sine values corresponding to the respective phases are output. That is, the outputs of the first to fourth memories 32 to 38 are as follows.

S1 = Sin (P1)

S2 = Sin (P2)

S3 = Sin (P3)

S4 = Sin (P4)

The multiplexer 50 sequentially switches the output values S1 to S4 of the first to fourth memories 32 to 38 and outputs them in synchronization with the reference clock 4f _ref .

3 is a multiplexer input / output signal waveform diagram when generating a sinusoidal wave having the same frequency as the reference clock. In FIG. 2, when the phase information ΔP is 360 ° (ΔP = 360 °), the phase data P1, P2, P3, and P4 output from the controller 40 are (0 °, 90 °, 180 °, 270). °), (0 °, 90 °, 180 °, 270 °),... … Becomes Output signals S1 to S4 of the first to fourth memories for the phase data P1 to P4 are as shown in FIG. The waveform shown in (b) of FIG. 3 receives the waveform from the multiplexer 50 and sequentially outputs the waveform in synchronization with the reference clock 4f _ref . In this case, the number of samples of the sine wave output from the multiplexer 50 is four. And the output frequency is Since ΔP = 360 °, f _out = f _out . Therefore, when the frequency f _out of the reference clock is 20 MHz, the maximum possible output frequency f _out is 20 MHz. However, the multiplexer 50 should be operated at 4 times the reference frequency (4f _ref ), that is, 80 MHz, but since the 74 series multiplexer operates well at frequencies above 100 MHz, there is no difficulty in implementing the multiplexer.

4 compares the output waveforms of the device according to the prior art with the prior art for output signals of the same frequency. A case where the reference frequency f _ref is 20 MHz and the desired output frequency f _out is 5 MHz will be described as an example. At this time, ΔP = 90 °, and in the conventional NCO as shown in FIG. 1, four sample values per cycle can be obtained as shown in FIG. However, in the present invention, the phase data is (P1, P2, P3, P4) = (0 °, 22.5 °, 45 °, 67.5 °), (90 °, 112.5 °, 135 °, 157.5 °), (180 °, 202.5 °, 225 °, 247.5 °), (270 °, 292.5 °, 315 °, 337.5 °), and 16 sample values can be obtained per cycle. Therefore, the waveform of (b) according to the present invention becomes a waveform closer to the sine wave than the waveform of (a) according to the prior art.

As described above, in the related art, at least four times the reference clock is required to generate a high frequency sine wave, while the present invention can obtain the same output frequency as that of the reference clock. In addition, since four times the number of samples can be obtained even when generating the same output frequency, it is possible to obtain a relatively high reliability sinusoidal wave during digital / analog conversion. Therefore, the digital sinusoidal wave generation circuit according to the present invention has an effect of realizing a product at a low cost while improving reliability.

Claims (6)

CLAIMS What is claimed is: 1. A method of generating a digital sinusoid, comprising: accumulating phases according to phase information; Generating a first phase data by converting a phase to the accumulated phase value; generating a plurality of phase data using the first phase data and the phase information; Outputting respective sine values corresponding to the phase data; And sequentially outputting the sine values. The digital sinusoidal wave generating method according to claim 1, wherein the first phase data can be represented by the following equation. P1 = P _D + mod (∑ △ P) Where P1 is the first phase data and P _D is the phase shift data. DELTA P denotes phase information and mod () denotes modulo for 360 °. The method of claim 2, wherein the plurality of phase data are each The phase difference of the digital data generation method characterized in that the phase data can be represented by the following equation. Here, N is an integer of 2 or more. An apparatus for generating a digital sinusoidal wave, the apparatus comprising: a phase accumulator configured to receive phase information and generate an accumulated phase value; A phase calculation unit receiving phase conversion data and generating first phase data in addition to the phase value applied from the phase accumulation block; A controller configured to receive a plurality of phase data by receiving first phase data from the phase information and the phase calculator; A plurality of memories that receive the phase data and output corresponding sine values; And a multiplexer for sequentially converting and outputting signals applied from the plurality of memories. The digital sinusoidal wave generating circuit according to claim 4, wherein the first phase data generated by the phase calculating unit can be expressed by the following equation. P1 = P _D + mod (∑ΔP) Where P1 is the first phase data and P _D is the phase shift data. ΔP denotes phase information and mod () denotes modulo for 360 °. The method of claim 5, wherein the plurality of phase data generated by the control unit The phase difference of the digital sine wave generation circuit, characterized in that can be represented by the following equation. Where N is an integer of 2 or more.