JPH06224921A - Polling signal synchronization protection circuit - Google Patents

Abstract

PURPOSE:To realize a synchronization protection circuit for a polling signal with a small scale of circuit configuration. CONSTITUTION:A periodic frame signal is in existence in an outgoing signal and plural polling signal areas are in existence at an equal interval between the frame signals. A polling signal detection circuit 2 detects a polling signal addressed to a concerned equipment in the polling signal area. A frame signal detection circuit 4 detects the frame signal. A count circuit 6 is initialized for each detection of the frame signal and outputs a polling signal position count 7 synchronously with each polling signal area. A first-in first-out memory circuit 8 stores a position count P and a protection count S with respect to each polling signal position addressed to the concerned equipment. A condition discrimination circuit 11 receives a polling signal detection signal 3 and the position count 7 and outputs a polling signal 12 whose synchronization is protected by using the counts P, S read from the memory circuit 8 as criteria.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polling signal synchronization protection circuit in digital communication by a polling system between a main device and a plurality of slave devices.

[0002]

2. Description of the Related Art When communication is performed between a master device and a slave device by a polling method, the master device sends a polling signal to a downlink transmission line, and the slave device goes up in synchronization with a polling signal addressed to itself. Uplink signals such as messages are sent to the transmission path. The polling signal is repeatedly transmitted to the downlink transmission line, and generally when the slave device detects the polling signal addressed to itself in N consecutive times, it starts outputting the polling signal to the device body. Here, if the polling signal on the downlink transmission line temporarily changes due to the influence of noise or the like, the slave device cannot detect the polling signal addressed to itself, and cannot output the polling signal to the device body. In such cases,
In the slave device, it is necessary to continuously output the polling signal under a certain condition to protect the missing of the polling signal due to noise or the like.

FIG. 4 shows a block diagram of a conventional sync protection circuit in the case where a downlink signal has a sync signal such as a frame signal or a polling signal at a cycle Ts. In the figure, the sync signal detection circuit 18 inputs a down signal from the signal line 17, and outputs a sync signal detection signal to the signal line 19 when the sync signal is detected. The memory circuit 20 stores the count value of the synchronization signal detection, outputs the count value to the signal line 21 by the read signal, and writes the count value from the signal line 22 when the write signal comes. The synchronization timing signal generation circuit 23 is initialized to zero by the clear signal from the signal line 25, and outputs the synchronization timing signal to the signal line 24 at the same time as the period Ts of the downlink signal. The condition determination circuit 26 reads the count value from the memory circuit 20, and determines the synchronization signal based on these values and the presence or absence of the synchronization signal detection signal on the signal line 19 and the synchronization timing signal on the signal line 24.
In addition to the above, the count value for detecting the synchronization signal is calculated, and writing to the memory circuit 20 and generation of a clear signal to the signal line 25 are performed.

Condition determination circuit 2 in this synchronization protection circuit
6 operates as follows.

Step 1: The sync signal detection signal on the signal line 19 is monitored. When the sync signal detection signal is detected on the signal line 19, a clear signal is generated on the signal line 25 to initialize the sync timing signal generation circuit 23, set the count value to 1, and write it in the memory circuit 20, and then proceed to step 2. .

Step 2: The synchronization timing signal on the signal line 24 is monitored, and when the synchronization timing signal is detected, it is determined whether or not there is a synchronization signal detection signal on the signal line 19. If there is no sync signal detection signal, the process returns to step 1. If there is a sync signal detection signal, the count value is read from the memory circuit 20 and the value is incremented by 1. If the count value is smaller than the predetermined integer value N, the counter value is written in the memory circuit 20, and this step is repeated. If the count value is N, a predetermined integer value M is added to the count value to obtain N + M, this N + M is written to the memory circuit 20 as a count value, and a synchronization signal is output to the signal line 27.
Go to step 3.

Step 3: The synchronization timing signal on the signal line 24 is monitored, and when the synchronization timing signal is detected, it is determined whether or not there is a synchronization signal detection signal on the signal line 19.
If there is no synchronizing signal detection signal, the count value is read from the memory circuit 20, the count value is decremented by 1, and the process proceeds to step 4. If there is a sync signal detection signal, the count value is read from the memory circuit 20, the count value is written as N + M in the memory circuit 20, a sync signal is output to the signal line 7, and this step is repeated.

Step 4: If the count value is larger than N, this count value is written in the memory circuit 20, a synchronizing signal is output to the signal line 27, and step 3 is executed. If the count value is N or less, the process returns to step 1.

From the above operation, the synchronization protection circuit of FIG.
When a downlink signal has a synchronization signal of a cycle Ts, if a synchronization signal is detected in the downlink signal N times consecutively, the synchronization signal starts to be output to the signal line 27 at the synchronization Ts, and even if the synchronization signal is not detected, the number of times is It can be seen that when the number of times is less than M times, the synchronization signal is continuously output, and when the synchronization signal is not detected in the downlink signal continuously M times, the synchronization signal output of the signal line 27 is stopped. As a result, even if the synchronization signal of the downlink signal temporarily changes due to the influence of noise, etc.
It is possible to continuously output the synchronization signal of No. 7 and protect the loss of the synchronization signal due to noise or the like.

[0010]

FIG. 3 is a conceptual diagram of an example of a downlink signal and a communication system when there is a frame signal and a synchronization signal in a polling signal area. In the figure, a master device 13 and a slave device 14 are designated as a downlink transmission line 15 and an uplink transmission line 1.
6 are connected, and a downlink signal is transmitted to the downlink transmission path. The downlink signal includes a frame signal having a period Tf, and the polling signal regions (1) to (4) are sandwiched between the frame signals and have an interval Tp. A certain polling signal area (i) is composed of the same polling signal for each frame signal, and thus the signal in the polling signal area (i) is a repeating signal of the cycle Tf. The slave device 14 uses the downlink signal frame signal and polling signal areas (1) to (4).
The upstream signal is transmitted to the upstream transmission line in synchronization with the polling signal addressed to the self-slave device. At this time, it is optional where the polling signal addressed to the self-serving apparatus is in the polling signal areas (1) to (4) and in one or a plurality of polling signal areas. The polling signal addressed to the own device in the plurality of polling areas is not periodic.

Consider the case where the conventional synchronization protection circuit of FIG. 4 is applied as the synchronization protection circuit of the frame signal of the down signal and the polling signal addressed to the own device of FIG.

Since the frame signal has a period Tf, by setting the period of the synchronization timing signal of the synchronization timing signal generation circuit 23 to Tf, the synchronization protection circuit of FIG. 4 can be used as it is. On the other hand, it is possible to know where the polling signal addressed to the own device is in the polling signal areas (1) to (4), whether one polling signal area is used, or whether a plurality of polling areas are used. As shown in FIG.
The synchronization protection circuit of can not be applied. However, the signal in the arbitrary polling signal area is the period T of the frame signal.
Since it is repeated at f, the synchronization protection circuit of the period Tf is configured for each polling signal area by the circuit of FIG. 4, and if the number of polling signal areas is prepared, the polling for its own device is performed like the frame signal. It is possible to protect the signal from being lost due to noise or the like. That is, for example, if there is a polling signal addressed to its own device in the polling signal area (1), this signal is always present at the cycle Tf, so the circuit of the configuration of FIG. 4 detects the polling signal addressed to its own device and outputs a synchronization signal. You can Further, if there is no polling signal addressed to the self device in the polling signal area (2), the circuit having the configuration of FIG. 4 cannot detect the polling signal addressed to the self device, and as a result, does not output the synchronization signal. Therefore, by configuring a synchronization protection circuit having a period Tf corresponding to each polling signal area and using the logical sum of the synchronization signal outputs of each circuit as the synchronization signal, the synchronization protection circuits for all polling signals addressed to the own device are provided. Can be configured.

As described above, the synchronization protection circuit for the frame signal found in the downlink signal of FIG. 3 and the polling signal addressed to itself can be configured by the conventional synchronization protection circuit of FIG. 4. In this circuit configuration, the polling signal is used. With respect to the above, the same circuit as in FIG. 4 is required for the number of polling signal areas in the downlink signal, and there is a drawback that the circuit scale becomes large.

The present invention provides a synchronization protection circuit for a polling signal addressed to itself in the polling signal area as shown in the downlink signal of FIG. 3 with a scale smaller than that of the conventional synchronization protection circuit. The purpose is to provide.

[0015]

A polling signal synchronization protection circuit of the present invention for achieving the above object includes a frame signal detection circuit that detects a frame signal that is periodically repeated and outputs a frame signal detection signal. , A polling signal detection circuit that detects a polling signal addressed to its own device in a polling signal area arranged at equal intervals sandwiched by the frame signal, and outputs a polling signal detection signal; And a polling signal position counting circuit that updates the count value in synchronization with each polling signal area and outputs the count value as a polling signal position count value, and the polling signal position corresponding to the polling signal detection signal. The count value (position count value) and the number of times the polling signal detection signal is output (protection A first-in first-out memory circuit for reading out the stored contents, and a unit for reading and rewriting the position count value and the protection count value from the first-in first-out memory circuit one by one. A condition determination circuit that receives a detection signal and a polling signal position count value and outputs a synchronously protected polling signal addressed to itself by using the position count value and the protection count value read from the first-in first-out memory circuit as a determination reference. .

[0016]

The frame signal detection circuit detects the frame signal, and the polling signal detection circuit detects the polling signal addressed to itself. The position of the detected polling signal addressed to the own device can be known by the polling signal position counting circuit that measures the polling signal area based on the detected frame signal. In addition, by using this first-in first-out memory circuit that stores this position count value and the protection count value of the polling signal addressed to the own device at this position and is read out in the order in which they are written, these positions are cyclically synchronized with the frame signal. Values can be written and read. The condition judging circuit outputs a polling signal addressed to its own device, which is synchronously protected, according to the detection signals from the frame signal detecting circuit and the polling signal detecting circuit and the position count value and the protection count value read from the first-in first-out memory circuit. As described above, only one set of the frame signal detection circuit, the polling signal detection circuit, the polling signal position counting circuit, the first-in first-out memory circuit, and the condition determination circuit can be used in the own device in the polling signal region as seen in the down signal of FIG. A synchronization protection circuit for the addressed polling signal can be realized, and a polling signal synchronization protection circuit with a small circuit scale can be realized.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a polling signal synchronization protection circuit of the present invention. 1 is an input down signal, 2 is a polling signal detection circuit, 3 is an output signal of the polling signal detection circuit 2, and a polling signal detection signal,
4 is a frame signal detection circuit, 5 is an output signal of the frame signal detection circuit 4, a frame signal detection signal, 6 is a polling signal position count circuit, 7 is an output signal of the polling signal position count circuit 6, and a polling signal position count value,
Reference numeral 8 is a first-in first-out memory circuit, 9 is a read signal from the first-in first-out memory circuit 8, 10 is a signal to be written in the first-in first-out memory circuit 8, 11 is a condition determination circuit, and 12 is a polling signal output from the condition determination circuit 11.

Also in this embodiment, the downlink signal shown in FIG. 3 will be described as an example of the input downlink signal 1. That is, the input downstream signal 1 includes a frame signal having a period Tf, and is sandwiched between the frame signals and at the interval Tp, the polling signal regions (1) to
There is (4). At this time, a certain polling signal area (i) consists of the same polling signal for each frame signal, and therefore the signal in the polling signal area (i) has a period T.
It becomes a repeating signal of f. It is optional where the polling signal addressed to the own device is in the polling signal areas (1) to (4), and whether there is one or a plurality of polling signals. The polling signal addressed to the own apparatus in the area sandwiched by the frame signals is arbitrary. The signal has no periodicity.

The polling signal and the frame signal addressed to the own device in the downlink signal 1 can be detected by the polling signal detecting circuit 2 and the frame signal detecting circuit 4 by means such as monitoring the bit patterns of the signals.
Since the frame signal is a repetitive signal of the cycle Tf and its position is fixed, it is possible to perform synchronization protection by the conventional method. Therefore, it is assumed that the frame signal detection circuit 4 outputs the frame signal detection signal 5 with the synchronization protection. The polling signal detection circuit 2 detects the polling signal detection signal 3 only when it detects the polling signal addressed to itself in one or more of the polling signal areas (1) to (4) of the downlink signal 1 for each frame signal. Is output. The polling signal addressed to this device is the polling signal area (1)-
Since the location of (4) is arbitrary, when the signal in the polling signal area is disturbed by noise or the like, the polling signal addressed to the own device may not be detected.

The polling signal position counting circuit 6 increments the count value at the interval Tp of the polling signal area of the downlink signal 1 and is initialized by the input of the frame signal detection signal 5. In this way, the polling signal position counting circuit 6 operates in the respective polling signal areas (1) to (1) of the downlink signal 1.
The polling signal position count value 7 is output in synchronization with (4).

The first-in first-out memory circuit 8 outputs the polling signal position count value (referred to as position count value P) and the number of times the polling signal detection signal is output (protection count value) for each polling signal area in which the polling signal addressed to the self device is detected. S) is stored. The first-in first-out memory circuit 8 inputs and stores the position count value P and the protection count value S as the write signal 10 under the control of the condition determination circuit 11, and outputs the read signal 9 in the input order.

The condition judging circuit 11 is a song internal register R1,
Has R2. Here, the internal register R1 stores a set of the position count P and the protection count value S output as the read signal 9 from the first-in first-out memory circuit 8. The internal register R2 and the first-in-first-out memory circuit 8 have one set of P and S as one data.
A value indicating the total number of data in is stored. The condition determination circuit 11 receives the polling signal detection signal 3 of the polling signal detection circuit 2 and the polling signal position count value 7 of the polling signal position count circuit 6 as inputs and outputs the position count value P and the protection count value S of the internal register R1. A polling signal 12 addressed to its own device, which is synchronously protected, is output as a determination criterion.

The operation of the condition judgment circuit 11 will be described below with reference to the flowchart of FIG.

The condition judging circuit 11 firstly executes step S1.
The contents of the first-in first-out memory circuit 8 are cleared in step S2, the contents of the internal register R2 are set to zero in step S2, and step S2 is executed.
At 3, the position count value P and the protection count value S of the internal register R1 are set to zero, and the process proceeds to step S4. In step 4, the polling signal detection signal 3 is monitored every time the polling signal position count value 7 is input. Since the input signal of the polling signal position count value 7 (referred to as input value C) is synchronized with the polling signal area, if there is no polling signal detection signal 3, the polling signal addressed to the own device is not in the polling signal area. , And proceeds to step S5. In step S5, at the first stage, since the position count value P of the internal register R1 is zero in step S3, it does not match the input value C of the polling signal position count value 7, and the process loops to step S4. This loop is continued until the polling signal detection signal 3 is detected in step S4.

In step S4, the polling signal detection signal 3
If the input value C of the polling signal position count value 7 and the position count value P of the internal register R1 match, the process proceeds to step S6. In this first step, since P is zero in step 3, C and P do not match, and the process proceeds to step S7. In step S7, the input value C of the polling signal position count value 7 is set as the position count value P, and 1 is set as the protection count value S, which is written in the first-in first-out memory circuit 8. In the next step S8, the internal register R2 is incremented by 1, and the process proceeds to step S9. In step S9, when R2 is 1, the process proceeds to step S10, and when R2 is not 1, the process immediately loops to step S4. In step S10, a set of position count value P and protection count value S is read from the first-in first-out memory circuit 8 in the first-in first-out order, set in the internal register R1, and looped to step S4.

When the polling signal detection signal 3 is detected again in step S4 and the input value C of the polling signal position count value 7 and the position count value P of the internal register R1 do not match in step S6, in step S7, The input value C of the polling signal position count value 7 corresponding to the newly detected polling signal detection signal 3 is set as the position count value P, and 1 is set as the protection count value S, which is newly written in the first-in first-out memory circuit 8, and in step S8. R
Increase 2 by 1. At this time, since R2 has a value other than 1, the process immediately loops to step S4 in step S9. Therefore, assuming that the polling signal addressed to the own device is first detected in the polling signal area (1) and then detected in the polling signal area (3), in this staircase, the polling signal area ( With the position count value P corresponding to 1) and the protection count value C of "1" still set, the position count value P corresponding to the polling signal area (3) and "1" are set in the first-in first-out memory circuit 8.
The protection count value C of is newly stored. The value of the internal register R2 is "2".

As described above, when a new polling signal addressed to itself is newly detected in any of the polling signal areas (1) to (4) sandwiched between the frame signals of the downlink signal 1, steps S4 to S10 are performed. Alternatively, by looping S9, the position count value and protection count value of each area can be registered using the internal register R1 and the first-in first-out memory circuit 8.

Then, in step S4, the polling signal detection signal 3 is detected, and in step S6, the input value C of the polling signal position count value 7 at that time and the internal register R are detected.
If the position count values P of 1 match, the process proceeds to step S11. In step S11, S of the internal register R1
Is incremented by 1 and the process proceeds to step 12. Step S12
Then, if the value of S is smaller than the predetermined value N, the process proceeds to step S13 without doing anything. If the value of S is N or more, the value of S is set to the predetermined value N + M and polling is performed. The signal 12 is output and the process proceeds to step S13. In step S13, the position count value P of the internal register R1 and the updated protection count value S are written in the first-in first-out memory circuit 8. In step S10, a new set of position count values P from the first-in first-out memory circuit 8 is newly added.
And the protection count value S are read out, set in the S internal register R1, and looped to step S4. As a result, once the protection count value S becomes equal to or more than N with respect to the same position count value P, thereafter, the polling signal 12 is output each time the own device polling signal corresponding to the position count value is detected. You can

In step S4, the polling signal detection signal 3
If is not detected, the process proceeds to step S5. Step S5
Then, if the input value C of the polling signal position count value 7 at that time and the position count value P of the internal register R1 match, the process proceeds to step S14, and the protection count value S of the internal register R1 is decremented by 1 and step Proceed to S15.
In step S15, it is determined whether S is N or less. If S is larger than N, the polling signal 12 is output in step S16, and steps S13 and S10 are executed.
Loop to step S4. As a result, once the protection count value S becomes a value of N or more, even if the polling signal addressed to the own device is not detected for the same position count value P, the polling signal is detected until it is not continuously detected M times. 12 can be continuously output.

When the value of S becomes N or less in step S15, the process proceeds to step S17, and the internal register R2 is decremented by 1. In the next step S18, it is determined whether R2 is zero, and when it is not zero, step S10 is executed and the process loops to step S4. As a result, the position count value and the protection count value that have been read from the first-in first-out memory circuit 8 to the internal register R1 are not rewritten in the first-in first-out memory circuit 8. That is, when S becomes equal to or less than N, the corresponding set of P and S is erased from the first-in first-out memory circuit 8 and removed from the polling protection target.

When the internal register R2 becomes zero in step S18, it means that there is no pair of P and S in the first-in first-out memory circuit 8 to be protected by polling. In this case, the process loops to step S3 to enter the initial state.

By the above operation, the circuit shown in FIG. 1 can perform the synchronization protection of the polling signal addressed to the own device in the polling signal area illustrated in the downlink signal of FIG. As can be seen from the flowchart of FIG. 2, the condition determination circuit 1
1 is a condition determination circuit 2 of the conventional synchronization protection circuit shown in FIG.
The operation is almost the same as that of No. 6 and can therefore be realized by circuits of almost the same scale. In the case of the frame format in which the polling signal area exists immediately after the frame signal, when the polling signal position counting circuit 6 is initialized by the input of the frame signal detection signal 5, the initial value thereof is set to 1. As long as the flowchart of FIG. 2 operates without contradiction, the description has been limited to the downlink signal, but it goes without saying that the circuit of FIG. 1 can be applied to the uplink signal having the same configuration as the downlink signal.

[0034]

As described above, according to the present invention, a set of a frame signal detecting circuit, a polling signal detecting circuit, a polling signal position counting circuit, a first-in first-out memory circuit, and a condition judging circuit are used only for periodical intervals between frame signals. Since it is possible to perform the synchronization protection of the polling signal addressed to the own device located at an arbitrary position in the polling signal area arranged in, the polling synchronization protection circuit can be realized with a small circuit scale.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a polling signal synchronization protection circuit of the present invention.

FIG. 2 is a flowchart illustrating the operation of the condition determination circuit in the embodiment of the present invention.

FIG. 3 is a configuration diagram showing an example of a downlink signal having a plurality of polling signal areas sandwiched between frame signals.

FIG. 4 is a block diagram of a conventional synchronization protection circuit.

[Explanation of symbols]

 1 Downstream signal 2 Polling signal detection circuit 3 Polling signal detection signal 4 Frame signal detection circuit 5 Frame signal detection signal 6 Polling signal position count circuit 7 Polling signal position count value 8 First-in first-out memory circuit 9 Read signal 10 Write signal 11 Condition determination circuit 12 Polling signal 13 Master device 14 Slave device

Claims (1)

[Claims] 1. When a master device and a plurality of slave devices communicate with each other, a frame signal is periodically included in a signal from the master device to the slave device, and a plurality of polling signal areas are sandwiched between the frame signals. In the polling communication method in which the slave device sends signals to the master device when there is a polling signal addressed to itself in the polling signal area, the slave device has a plurality of polling signals between the frame signals. A circuit that performs synchronization protection of a polling signal addressed to its own device that exists arbitrarily in a region, a frame signal detection circuit that detects the frame signal and outputs a frame signal detection signal, and a polling signal region addressed to its own device A polling signal detection circuit that detects a polling signal and outputs a polling signal detection signal, and is initialized by the frame signal detection signal. A polling signal position count circuit that updates the count value in synchronization with each polling signal area and outputs the count value as a polling signal position count value, and the polling signal position count value (corresponding to the polling signal detection signal Hereinafter referred to as position count value)
And a first-in first-out memory circuit that stores the number of times the polling signal detection signal is output (hereinafter referred to as a protection count value) and that is read out in the order in which the stored contents are written, and a position count value and a protection count value from the first-in first-out memory circuit. Synchronous protection having means for reading and rewriting one set at a time, using the polling signal detection signal and the polling signal position count value as input, and using the position count value and protection count value read from the first-in first-out memory circuit as a criterion. A polling signal synchronization protection circuit including a condition determination circuit that outputs a polling signal addressed to the device itself.