JPH06224261A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device in which the damage of the electrode of a semiconductor chip can be prevented by relaxing a stress applied to the semiconductor chip when a lead frame and an inner lead are brought into contact with each other and also the semiconductor chip and the lead frame can be surely connected. CONSTITUTION:A double-sided adhesive tape 6 is placed between a semiconductor chip 1 with electrodes 4 formed on the surface and the inner leads 3 of a lead frame 2 made of a conductive material and is temporarily fastened by thermo compression bonding and at the same time the electrodes 4 of the semiconductor chip 1 and the inner leads 3 are interconnected by plating, and the tips of the inner leads 3 is brought into contact with the electrodes 4 of the semiconductor chip 1 in advance and at the same time a notch is provided in a least one place nearer to the tip-side part than the double-sided adhesive tape 6 of the inner leads 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to ICs, LSIs, VLSs.
The present invention relates to a semiconductor device in which a highly integrated semiconductor chip such as I is mounted on a lead frame, and in particular, stress applied to an electrode of the semiconductor chip when the inner lead of the lead frame is in contact is relaxed to prevent damage to the electrode of the semiconductor chip. The present invention also relates to a semiconductor device capable of reliably connecting a semiconductor chip and a lead frame.

[0002]

2. Description of the Related Art Generally, lead frames are often used for mounting semiconductor chips such as ICs, LSIs and VLSIs. This lead frame usually consists of an island formed in the center and inner leads formed around the island, and the semiconductor chip is die-bonded onto the island.

Under such circumstances, recently, there is no portion corresponding to an island, and a semiconductor chip is provided below or above the surface of the lead frame, that is, so-called LOC (L
ead on chip) or COL (chip)
A semiconductor device having a lead frame of on lead structure has been developed. This LOC or COL
Advantages of the structure include product deployment in various packages, noise countermeasures for high-speed operation and simultaneous output of multi-bit version, support for larger semiconductor chips, shortened lead frame design time, etc. A great effect can be expected in solving many problems in producing the most advanced semiconductor chip.

FIG. 4 is a plan view showing a structural example of a semiconductor device having a lead frame of this type of LOC structure, and FIG.
(A) And (b) is the top view and sectional drawing which expand and show the structural example of the inner lead part of the same semiconductor device.
4 and 5, a lead frame 2 made of a conductive material (such as 42 alloy or a copper material sandwiched between 42 alloys from both sides thereof) is placed on a semiconductor chip 1. The tip of each inner lead 3 of 2 is positioned with respect to each electrode (aluminum electrode, etc.) 4 of the semiconductor chip 1, and the tip of each inner lead 3 and each electrode 4 of the semiconductor chip 1 are bonded by a bonding wire (Au). Wires and Al wires, etc.) 5 are wire-bonded to each other.

The positioning of the tip of each inner lead 3 and each electrode 4 of the semiconductor chip 1 is performed before the wire bonding is performed.
Are temporarily fixed with the double-sided adhesive tape 6. As the double-sided adhesive tape 6, for example, a double-sided tape using an acrylic adhesive can be used.

By the way, in such a connection by wire bonding, the shortest distance between the bonding wires 5 adjacent to each other is restricted by the outer shape of the bonding capillary (needle) used, and the distance between the electrodes 4 on the semiconductor chip 1 is reduced. It is difficult to reduce the size to about 100 μm or less.

Further, because of the metal connection between the Au wire or Al wire and the aluminum electrode 4 on the semiconductor chip 1, it is necessary to apply a physical load such as heating, pressurization, ultrasonic vibration, etc. The lower semiconductor chip 1 itself may be damaged.

Therefore, in order to solve the above-mentioned problems, recently, for example, one disclosed in "Japanese Patent Laid-Open No. 4-37149" has been proposed. That is, in the one shown here, the inner lead of the lead frame and the electrode of the semiconductor chip are connected by metal plating or by using a conductive adhesive and metal plating in combination.

However, the semiconductor device having such a connection has the following problems.

That is, as described above, in the case of manufacturing a semiconductor device, when the semiconductor chip 1 is temporarily fixed to the inner lead 3 of the lead frame 2 by thermocompression bonding,
When the tip of the inner lead 3 is brought into contact with the electrode 4 of the semiconductor chip 1, there is a problem that the stress is applied to the electrode of the semiconductor chip 1 and the electrode 4 of the semiconductor chip 1 is damaged.

Further, the semiconductor chip 1 and the lead frame 2
Since and are fixed by being adhered by the double-sided adhesive tape 6, it is not possible to fill the gap between them by plating. Also, even if the space could be filled,
Since the plating film grows isotropically (100 μm downward and about 100 μm left and right), the inner lead 3 will grow when the plating is performed to grow in the direction of the electrode 4 and connect.
They will come into contact with each other and short-circuit. Therefore, the semiconductor chip 1 and the lead frame 2 are not reliably connected,
There is a problem in dealing with high pin count and high density.

[0012]

As described above, in the conventional semiconductor device, when the tip of the inner lead is brought into contact with the electrode of the semiconductor chip, the stress is applied to the electrode of the semiconductor chip and the stress of the semiconductor chip is increased. The electrode is damaged,
Alternatively, there is a problem that the semiconductor chip and the lead frame cannot be reliably connected.

The present invention has been made to solve the above problems, and an object of the present invention is to reduce the stress applied to the electrodes of the semiconductor chip when the inner leads of the lead frame are in contact with each other. An object of the present invention is to provide a highly reliable semiconductor device capable of preventing damage to electrodes and reliably connecting a semiconductor chip and a lead frame.

[0014]

In order to achieve the above object, the present invention provides a double-sided adhesive tape between a semiconductor chip having electrodes formed on its surface and an inner lead of a lead frame made of a conductive material. In the semiconductor device which is temporarily fixed by thermocompression with the interposition of, and the electrode of the semiconductor chip and the inner lead are connected by plating, the tip of the inner lead is in contact with the electrode of the semiconductor chip in advance, In addition, a notch is provided in at least one part of the inner lead on the tip side of the double-sided adhesive tape.

Here, in particular, as a structure in which the tips of the inner leads come into contact with the electrodes of the semiconductor chip, the tips of the inner leads are inclined by depressing.

The notch is provided by half etching, press working, or laser working.

Further, the depressing angle at the tip of the inner lead is made closer to a right angle and deepened.

Further, as the inner lead, only one layer of the multi-layered lead frame made of different assembly materials is left, and a predetermined portion is removed by etching to provide the cutout portion.

[0019]

Therefore, in the semiconductor device of the present invention, since the notch is provided at least at one portion of the inner lead on the tip side of the double-sided adhesive tape, the strength of the inner lead is reduced and the inner lead is made elastic. The stress applied to the electrodes of the semiconductor chip at the time of contact with the inner leads can be relieved to prevent the electrodes of the semiconductor chip from being damaged.

Further, since the tip of the inner lead is brought into contact with the electrode of the semiconductor chip in advance, plating is simultaneously deposited on the inner lead and the electrode of the semiconductor chip. It is possible to obtain a strength higher than the connection strength, and it is possible to reliably connect the semiconductor chip and the lead frame.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a plan view showing a structural example of a semiconductor device having a lead frame of LOC structure according to the present invention, FIG.
(A) And (b) is the top view and sectional drawing which expand and show the structural example of the inner lead part of the same semiconductor device,
The same elements as those in FIGS. 4 and 5 are designated by the same reference numerals, and the description thereof will be omitted. Here, only different portions will be described.

That is, in the semiconductor device of this embodiment, the bonding wires 5 for connecting the tips of the inner leads 3 of the lead frame 2 and the electrodes 4 of the semiconductor chip 1 in FIGS. 4 and 5 are omitted. However, instead of this, by making the tip of each inner lead 3 inclined (hereinafter, referred to as depressing. 7 is a depressed portion), the tip of each inner lead 3 is preliminarily attached to the semiconductor chip 1. It is configured to be in contact with each electrode 4,
Further, a notch 8 is formed, for example, by half etching on the entire surface (on one side) of the inner lead 3 on one side (in this example, the side surface of the semiconductor chip 1) on the tip side of the double-sided adhesive tape 6.

Here, the depress portion 7 at the tip of each inner lead 3 is provided by depressing each inner lead 3 only by the thickness of the double-sided adhesive tape 6 for temporary adhesion, and the angle can be set. As far as possible, it is desirable to approach a right angle and make it deeper.

Further, as the double-sided adhesive tape 6, for example, one obtained by applying an adhesive on both sides of polyimide can be used.

Next, in the semiconductor device of the present embodiment having the above-described structure, the entire front end portion of the one side of each inner lead 3 of the lead frame 2 with respect to the double-sided adhesive tape 6 is half-etched and cut out. By providing the portion 8, the strength of each inner lead 3 can be reduced and the inner lead 3 can be made to have elasticity. Therefore, the stress applied to the lead frame 2 of the double-sided adhesive tape 6 portion by the pressure bonding at the time of temporary fixing can be reduced. It is possible to reduce the stress toward each of the electrodes 3 and thus alleviate the stress applied to each electrode 4 of the semiconductor chip 1 when each inner lead 3 contacts.

Further, in this case, by making the angle of the depressed portion 7 at the tip of each inner lead 3 as close to the right angle as possible and deepening it, the stress applied in the horizontal direction in addition to the stress applied in the vertical direction is relaxed. You can

This makes it possible to reduce the damage given to each electrode 4 of the semiconductor chip 1 and prevent the damage to each electrode 4 of the semiconductor chip 1.

On the other hand, when the tip of each inner lead 3 is brought into contact with each electrode 4 of the semiconductor chip 1 in advance, plating is simultaneously deposited on each inner lead 3 and each electrode 4 of the semiconductor chip 1, so that the conventional method is used. As compared with the case of no contact, it is possible to obtain strength higher than the connection strength by wire bonding in a short time.

As a result, unlike the prior art, there is no need to perform plating for growing and connecting in the direction of the electrodes 4 and the inner leads 3 do not come into contact with each other to cause a short circuit. It is possible to reliably connect to the lead frame 2 and cope with the increase in the number of pins and the increase in density.

As described above, in this embodiment, the double-sided adhesive tape 6 is interposed between the semiconductor chip 1 having the electrode 4 formed on the surface and the inner lead 3 of the lead frame 2 made of a conductive material. In the semiconductor device in which the electrodes 4 of the semiconductor chip 1 and the inner leads 3 are connected by plating by thermocompression bonding, the inner leads 3 of the inner leads 3 are The tip is configured to come into contact with each electrode 4 of the semiconductor chip 1 in advance, and each inner lead 3
A notch 8 is formed by half etching on the entire one side (side surface of the semiconductor chip 1) of the double-sided adhesive tape 6 (one place), and the angle of the depress portion 7 is made as close to a right angle as possible. It was made to be deep.

Therefore, the following effects can be obtained.

(A) Since the notch portion 8 is provided on the entire one side of each inner lead 3 on the tip side of the double-sided adhesive tape 6, the strength of each inner lead 3 can be reduced and elasticity can be provided. , The stress applied to each electrode 4 of the semiconductor chip 1 when each inner lead 3 is contacted is relaxed,
It is possible to prevent damage to each electrode 4 of the semiconductor chip 1.

(B) Since the tips of the inner leads 3 are brought into contact with the respective electrodes 4 of the semiconductor chip 1 in advance, plating is simultaneously deposited on the respective inner leads 3 and the respective electrodes 4 of the semiconductor chip 1. It is possible to obtain strength higher than the connection strength by wire bonding in a shorter time than in the case of no contact. This ensures the connection between the semiconductor chip 1 and the lead frame 2,
It is possible to support high pin count and high density.

(C) Since the angle of the depressed portion 7 is made as close to the right angle as possible and deepened, the effect of the above (a) can be more remarkably exhibited.

The present invention is not limited to the above embodiment, but can be implemented in the same manner as described below.

(A) In the above embodiment, the inner lead 3
The case where the tip of the inner lead 3 has a shape that is inclined by depressing as the configuration in which the tip of the inner surface contacts the electrode 4 of the semiconductor chip 1 has been described. You may make it a shape.

(B) In the above embodiment, the case where the notch 7 is provided by half etching has been described, but the present invention is not limited to this, and it may be provided by press working, for example.

As described above, by pressing the tip side of the double-sided adhesive tape 6 of the inner lead 3, the stress applied to the tip of the inner lead 3 at the time of pressurization is reduced, and each of the semiconductor chips 1 is reduced. It is possible to prevent the electrode 4 from being damaged.

Further, in the case of this press working, thermocompression bonding is carried out when temporarily fixing with the double-sided adhesive tape 6, but the inner lead 3 which once contacts the electrode 4 is prevented from being warped by the working, and the semiconductor chip 1 and the lead frame 2 can be more reliably brought into contact with each other.

(C) In the above embodiment, the case where the notch 7 is provided by half etching has been described, but the present invention is not limited to this, and it may be provided by laser processing, for example.

Particularly, in the case of this laser processing,
Instead of providing the cutout portion, one or more holes may be provided in the portion of the inner lead 3 which is closer to the tip than the double-sided adhesive tape 6.

(D) In the above embodiment, the inner lead 3
The case where the angle of the depress portion 7 at the tip is made closer to a right angle and deepened has been described, but this is not an essential requirement of the present invention.

(E) In the above embodiment, the inner lead 3
The case where the notch 8 is provided on the entire one side (the side of the semiconductor chip 1) of the double-sided adhesive tape 6 on one side (on one side) has been described, but the present invention is not limited to this and, for example, FIG.
As shown in the plan view and the sectional view in (a) and (b), one side of the inner lead 3 (side surface of the semiconductor chip 1)
The notches 8 may be provided at two locations (three or more locations) on the tip side of the double-sided adhesive tape 6.

As described above, by providing the cutouts 8 at two or more locations on the inner lead 3, the strength of the lead frame 2 is further reduced and the stress applied during the pressure bonding is removed, and each electrode 4 of the semiconductor chip 1 is removed. It becomes possible to prevent damage more effectively.

(F) In the above embodiment, the inner lead 3
The case where the cutouts 8 are provided only on one side (side surface of the semiconductor chip 1) has been described. However, the present invention is not limited to this, and the cutouts 8 are provided only on both sides of the inner lead 3, that is, the side surface of the semiconductor chip 1 and the side surface opposite to the semiconductor chip 1. It may be provided.

Further, the notch 8 may be provided at one place or two places (three or more places may be provided) on the side surface of the inner lead 3 opposite to the semiconductor chip 1.

(G) In the above embodiment, as the inner lead 3, only one layer of the lead frame having a multi-layer structure made of different materials is left, and a predetermined portion is removed by etching, so that the notch 8 is formed. Even if the above is provided, the same effect as described above can be obtained.

For example, even if the notch 8 is provided by laminating two layers of copper alloy and 42 alloy and removing a predetermined portion of the copper alloy layer by etching, the same as the above. It is possible to obtain an effect.

Further, three layers are laminated so that both sides of the copper alloy are sandwiched by 42 alloys, and only one layer (for example,
Even if the notch 8 is provided by removing a predetermined portion by etching while leaving one alloy layer 42), the same effect as described above can be obtained.

[0051]

As described above, according to the present invention, a double-sided adhesive tape is interposed between a semiconductor chip having electrodes formed on the surface thereof and an inner lead of a lead frame made of a conductive material, and heat is applied. In a semiconductor device that is temporarily fixed by crimping and the electrode of the semiconductor chip and the inner lead are connected by plating, the tip of the inner lead is in contact with the electrode of the semiconductor chip in advance, and both sides of the inner lead are Since the notch is provided at least at one position on the tip side of the adhesive tape, the stress applied to the electrode of the semiconductor chip when the inner lead of the lead frame comes into contact can be relieved to prevent the electrode of the semiconductor chip from being damaged. A highly reliable semiconductor device that can reliably connect a semiconductor chip to a lead frame It can do today.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a semiconductor device having a LOC structure according to the present invention.

FIG. 2 is an enlarged view showing a configuration example of an inner lead portion in the embodiment.

FIG. 3 is an enlarged view showing a configuration example of an inner lead portion in another embodiment of the LOC structure semiconductor device according to the present invention.

FIG. 4 is a plan view showing a configuration example of a conventional semiconductor device having a LOC structure.

FIG. 5 is an enlarged view showing a configuration example of an inner lead portion in the conventional semiconductor device.

[Explanation of symbols]

1 ... Semiconductor chip, 2 ... Lead frame, 3 ... Inner lead, 4 ... Electrode, 6 ... Double-sided adhesive tape, 7 ... Depressed portion, 8 ... Notched portion.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takao Fujitsu, 1 Komukai-Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Toshiba Corporation Tamagawa factory (72) Inventor Yoshimasa Kudo Toshiba, Mukai-ku, Kawasaki-shi, Kanagawa Town No. 1 In stock company Toshiba Tamagawa Plant (72) Inventor Shinya Shimizu No. 1 Komukai Toshiba Town, Kouki-ku, Kawasaki City, Kanagawa Inside Company Tamagawa Plant

Claims (7)

[Claims] 1. A double-sided adhesive tape is interposed between a semiconductor chip having an electrode formed on its surface and an inner lead of a lead frame made of a conductive material to temporarily fix the same by thermocompression bonding, and In a semiconductor device configured by connecting electrodes and inner leads by plating, the tip of the inner lead is in contact with the electrode of the semiconductor chip in advance, and the tip side of the inner lead is more than the double-sided adhesive tape. A semiconductor device comprising a cutout portion provided at least at one portion. 2. The semiconductor device according to claim 1, wherein the tip of the inner lead is in contact with the electrode of the semiconductor chip in that the tip of the inner lead is inclined by depressing. . 3. The semiconductor device according to claim 1, wherein the cutout portion is provided by half etching. 4. The semiconductor device according to claim 1, wherein the cutout portion is provided by press working. 5. The semiconductor device according to claim 1, wherein the cutout portion is provided by laser processing. 6. The depressing angle at the tip of the inner lead is made closer to a right angle and deepened.
The semiconductor device according to. 7. The inner lead is characterized in that only one layer of a lead frame having a multi-layer structure made of different assembly materials is left and a predetermined portion is removed by etching to provide the cutout portion. Item 2. The semiconductor device according to item 1.