JPH06222987A - Reader of semiconductor storage device - Google Patents

Abstract

PURPOSE:To shorten access time to discontinuous address by temporarily storing the information of an address in a sub recorder capable of high-speed reading, when there is a discontinuous part in address. CONSTITUTION:A main storage circuit 1 is a circuit for storing information corresponding to the address, and the main storage circuit 1 inputs/outputs the information through an input/output control circuit 3 to the designated address inputted from the outside by a storage control circuit 2. An address evaluation circuit 4 is connected to the storage control circuit 2, the address to be read this time is compared with the preceding address and when both of them are discontinuous, the effect is transmitted to the storage control circuit 2. The input/output control circuit 3 is connected to a sub storage circuit capable of high-speed access, and when the addresses of information to be read are discontinuous, this sub storage circuit 5 compares the first address of the discontinued part with the address stored in the sub storage circuit 5, transmits the result to the storage control circuit 2 and reads the address at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device in which information is stored in address units and which can be read out by addressing the information from the outside, and particularly to respond to a high-speed read request from the outside. The present invention relates to a semiconductor memory device reading device.

[0002]

2. Description of the Related Art Conventionally, in response to a request for reading information from the processing device side, the semiconductor memory device side decodes the requested address and reads the corresponding memory contents. With the increase in the speed of, it has become desirable to improve the responsiveness of the storage device side.
For example, a high-speed readable SRAM or the like has been used as a storage device. This is a so-called cache memory, and is generally provided as a high-speed small-capacity buffer storage device between a low-speed large-capacity main storage device and a processing device.

However, since the SRAM described above is relatively expensive, especially in a small-scale system, the cost increase by setting the cache memory greatly affects the cost of the entire device. It cannot be used, and only a low-speed storage device such as DRAM is actually used. This low-speed storage device can access continuous addresses at high speed, but when accessing discontinuous addresses, the discontinuity is caused by the delay in the startup time of the sense amplifier. There was a problem that the access to the first address in the part where it became is extremely slow.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the problems of the prior art as described above, and its main purpose is to address discontinuous addresses when a low-speed storage device is used. It is an object of the present invention to provide a reading device of a semiconductor memory device capable of speeding up reading.

[0005]

According to the present invention, there is provided a semiconductor memory device reading device capable of storing information in address units and reading the information by externally addressing the information. A main memory circuit, a sub memory circuit capable of storing at least one unit in units of information stored in the main memory circuit and its corresponding address, and capable of high-speed access, and output of information from each memory circuit to the outside. An output control circuit for controlling
An address evaluation circuit for inspecting whether or not the address to be read this time and the address to be read last time are continuous with respect to the main memory circuit, and this time is read when the respective addresses are discontinuous. An address comparison circuit for checking whether an address and information corresponding to the address are stored in the sub storage circuit, and a control circuit for controlling the main storage circuit, the sub storage circuit, the address evaluation circuit, and the address comparison circuit. When the addresses are discontinuous, and the address to be read this time and the information corresponding to the address are not stored in the sub memory circuit, the main memory circuit is directly read. The address to be read this time and the information corresponding to the address are stored in the sub memory circuit, and the addresses are discontinuous. Further, when the address to be read this time and the information corresponding to the address are stored in the sub memory circuit, the semiconductor memory device is characterized in that the information is read from the sub memory circuit in preference to the main memory circuit. It is achieved by providing a reading device of

[0006]

As described above, when there is a discontinuous portion of the address during the reading of information, the information of the address of the jumped destination is temporarily stored in the sub-recording device capable of high-speed reading. In this way, when the same reading is performed again, the information of the jump destination address is read from the side of the secondary storage device, so that, for example, in a low-speed storage device using a DRAM or flash ROM The read operation is performed at high speed by using page mode, etc., and if the read address is skipped due to a jump command, etc., the address of the jump destination and the information corresponding to that address are stored in the sub memory circuit side. For example, reading is performed from this sub memory circuit side, and while the information is being read from this sub memory circuit, the next address of the jump destination on the main memory circuit side is read. If to perform less access even for accessing a discontinuous addresses it is possible to read at high speed.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a schematic structure of a semiconductor memory device to which the present invention is applied. Main memory circuit 1
Is a memory circuit, such as a DRAM, in which an address as shown in FIG. 3 is set and information corresponding to this address can be stored. The main memory circuit 1 can input / output information to / from a designated address externally input by the storage control circuit 2 via the input / output control circuit 3. In addition, the storage control circuit 2
An address evaluation circuit 4 is connected to this address, and at the time of reading, the address to be read this time is compared with the address of the read performed immediately before that, and if both are discontinuous, the fact is notified to the storage control circuit. Has become. Further, the input / output control circuit 3 is also connected to the sub memory circuit 5 which can be accessed at high speed, and when the addresses of the information read according to the procedure described later are discontinuous, the first address of the interrupted part, Information corresponding to the address and a flag indicating the validity of the information are stored. Further, the sub memory circuit 5 is also connected to the address comparison circuit 6, and when the addresses of the information to be read are discontinuous, the first address of the interrupted portion and the address stored in the sub memory circuit are set. The result is compared and the result is transmitted to the memory control circuit 2. Then, in the storage control circuit 2, the input / output control circuit 3 controls which of the main storage circuit 1 and the sub storage circuit 5 outputs information to the outside.

The operating procedure of this embodiment will be described in detail below with reference to FIGS. 2 and 3. First, as shown in the flowchart of FIG. 2, when a designated address for reading is input to the storage control circuit 2 in step 1, the process proceeds to step 2 and the address evaluation circuit 4 immediately (previously) reads it. It is judged whether or not the address and the address designated in step 1 are continuous, and if they are continuous, the process proceeds to step 3 where the normal reading from the main memory circuit 1 is performed, and the process proceeds to step 1. Return. If the address read immediately before in step 2 and the address to be read this time are not consecutive, the process proceeds to step 4 and the address stored in the sub memory circuit 5 and the address read this time in the address comparison circuit 6 are read. It is determined whether or not there is a match with the address for performing the operation. If they do not match, the process proceeds to step 5 and the address currently read from the main memory circuit 1 to the sub memory circuit 5 via the input / output control circuit 3, The information corresponding to this address and the valid / invalid flag (for example, T or F) are stored, and the routine proceeds to step 3 where the normal read processing is performed.

On the other hand, when the address stored in the sub memory circuit 5 in step 4 and the address to be read this time match, the process proceeds to step 6 and the sub memory circuit 5 is read.
The storage control circuit 2 determines whether or not the information corresponding to the address stored in is valid. If invalid, the processes of steps 5 and 3 are performed. If valid, the process proceeds to step 7. Then, the information is read from the sub memory circuit 5, and the process returns to step 1.

Here, when the data is read from the sub memory circuit 5 in step 7, the fact is transmitted to the memory control circuit 2 and a response signal is output to the processing device side. Based on this response signal, the processor side inputs the next read designation address to the storage control circuit 2 at an early stage.

The above procedure will be described with reference to the diagram showing the address space of FIG. 3. When continuous addresses are read, normal reading is performed from the main memory circuit 1, and for example, a jump instruction (JMP) at address 4 is performed. ) Etc. to return to address 0001, this address 000
1 and the information content thereof are stored in the sub storage circuit 5, and if not stored, the address,
Store the corresponding information and flags. Then, when the next jumping to the address 0001 by a similar jump instruction or the like, if the read processing is performed from the main memory circuit 1, the read processing may be delayed due to a slow drive time of the sense amplifier. Immediately after this jump instruction, the information at address 0001 is read out from the sub memory circuit 5 at high speed, while the main memory circuit 1 side reads address 0002.
Since it is possible to access, the high speed reading can be ensured.

The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the technical scope thereof. For example, this embodiment uses a low speed memory circuit such as a DRAM as a main memory circuit. Although the present invention is applied to a semiconductor memory device, it goes without saying that when the present invention is applied to a semiconductor memory device having a high-speed SRAM as a main memory circuit, a higher speed can be achieved. Further, in the present embodiment, one address and correspondence information are stored in the sub storage circuit, but by providing a plurality of sub storage circuits and storing one address and correspondence information as one unit, a large number of units are stored at the same time.
Read access to many types of discontinuous addresses can be speeded up.

[0014]

As is apparent from the above description, according to the input / output structure of the semiconductor memory device of the present invention, when a discontinuous address is accessed by a jump instruction or the like at the time of reading, the first address of the jump destination address is read. Information is stored in a sub-memory circuit that can be accessed at high speed, and when the address of the jump destination is read out again by the next jump or the like, the sub-memory circuit is read at high speed, and in the meantime the main memory circuit side jumps. With the configuration in which the address next to the previous address is accessed, the access time to the discontinuous addresses is shortened, and high-speed read processing can be performed even with a low-speed storage device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor memory device to which the present invention is applied.

FIG. 2 is a flowchart showing an operating procedure of the embodiment shown in FIG.

3 is an explanatory diagram showing an address space of a main memory circuit and stored contents of a sub memory circuit in the embodiment of FIG. 1. FIG.

[Explanation of symbols]

 1 main memory circuit 2 memory control circuit 3 input / output control circuit 4 address evaluation circuit 5 sub memory circuit 6 address comparison circuit

Claims (1)

[Claims] 1. A reading device of a semiconductor memory device capable of reading information by storing the information in address units and externally addressing the main memory circuit, and information stored in the main memory circuit. And at least one unit of the corresponding address as a unit and capable of high-speed access, an output control circuit for controlling output of information from each of the storage circuits to the outside, and a main storage circuit. Address evaluation circuit that inspects whether the address to be read this time and the address to be read last time are continuous, and if the addresses are discontinuous, the address to be read this time and the address corresponding to the address Address comparing circuit for checking whether or not the information to be stored is stored in the sub memory circuit, the main memory circuit, and the sub memory A control circuit for controlling a circuit, an address evaluation circuit, and an address comparison circuit, each address is discontinuous, and an address to be read this time and information corresponding to the address are stored in the sub storage circuit. If not, the main memory circuit is directly read, and the address to be read this time and the information corresponding to the address are stored in the sub memory circuit. The respective addresses are discontinuous and the current read is performed. A reading device of a semiconductor memory device, wherein when an address and information corresponding to the address are stored in the sub memory circuit, the information is read from the sub memory circuit in preference to the main memory circuit.