JPH0621989B2 - Register array circuit - Google Patents

Description

The present invention relates to a register circuit, and more particularly to a mode control register for a single chip microcomputer or the like.

[Conventional technology]

A single-chip microcomputer has peripheral hardware and a large number of I / O ports in one chip, and these are address-mapped in an I / O space or a memory space. The CPU rewrites the control register of the peripheral hardware by writing data to this address to control.

The mode control registers of the timer are shown in Tables 1 and 2 as one row of this control register, which will be briefly described.

Table 1 is an operation specification table of the 4-bit control register TCON0 that specifies the operation mode of the timer 0. The 0th bit is the frequency designation of the counter lock. The first bit is the designation of the operation method. The second bit is the mask specification of the interrupt to the CPU by the overflow signal. The third bit is the designation of activation. The address of this TCON0 is 0 ^OCT in octal.

Now, it is assumed that there are four timers, and the control registers TCON0 to TCON3 are assigned addresses as shown in Table 2. Table 1 shows the mode designation of each timer
It is the same as TCON0.

[Problems to be solved by the invention]

In the above-described conventional timer, the control bit address is assigned to each timer. Therefore, for example, even if it is desired to perform interrupt mask control for all timers, it is necessary to write the control register to each of the four timers. This requires writing once, which not only complicates the processing program but also increases the processing time.

Further, even if the address is assigned from each timer to each function, all control registers must be set when only one timer is used, so that there is a disadvantage that it is necessary to write four times.

[Means for solving problems]

The register array circuit of the present invention has a two-dimensional array of register arrays, a row decoder for selecting any one row of the register array, and a column decoder for selecting any one column of the register array. Each cell of the register array is connected to a row data line through a row data selection circuit and a column data line through a column data selection circuit, and the row data selection circuit is selected by the column decoder and the column The data selection circuit is selected by the row decoder, and the row data line and the column data line may be connected for each data bit and connected as a data input / output line of a register array to a write / read buffer controlled by a write / read signal. Characterize things.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

Fig. 1 shows mode control of 4 timers. 4
4 shows a register array circuit of 4 bits. A0 to A2 are address signals. R / W is a register read / write signal, which is read when R / W = 1 and write when R / W = 0. DB0 to DB3 are 4-bit data buses that write data on the bus to registers or read data from the registers to the data buses. D0 to D3 are data lines for writing data to the register array and reading data from the register array. TCON00
~ 03, TCON10 ~ 13, TCON20 ~ 23, TCON30 ~ 33
Is the mode control register array of the timer, 2
The digit in the first digit indicates which of the four timers 0 to 3 is used, and the digit in the first digit indicates the bit position of each register. The designated contents of the bit position are the same as those in the conventional example shown in Table 1. Next, explaining the inside of the mode control register array, I1 and I2 are inverters
A latch is composed of these. TX and TY are transfer gates, and control to write data on D0 to D3 to the latches of I1 to I2 or read data of the latch of I1 to I2 to D0 to D3.

AD0 to AD7 are address decoders to which the address signals A0 to A3 are input. AX0 is the output signal of AD0
Timer 0 is selected by inputting to the TY gate in TCON00-03. AX1 is an output signal of AD1 and TCON0 to
The timer 1 is selected by being input to the TY gate in 13. AX2 is the output signal of AD2 and TCON of TCON20-23.
The timer 2 is selected by being input to the Y gate. AX
3 is an output signal of AD3, which is input to the TY gates of TCONs 30 to 33 to select the timer 3. AY0 is AD4
Is input to the TX gates in TCON00, 10, 20, and 30, and the frequency designation of the count clock is selected. AY1 is the output signal of AD5, TCON01, 11,
The operation mode designation is selected by inputting to the TX gate in 21 and 31. AY2 is the output signal of AD6, TCON02,
The mask designation is selected by inputting to the gate of TX in 12, 22, and 32. AY3 is the output signal of AD7 and TCON0
The start designation is selected by inputting into the TX gate in 3, 13, 23, and 33.

I0 is an inverter that generates an inverted signal of the R / W signal.
RW0 to RW3 are read / write buffers. RW
The inside of 0 to RW3 is composed of a read buffer RB and a write buffer WB, and when R / W = 1, RB is selected to output the data of D0 to D3 to DB0 to DB3.
When / W = 0, WB is selected and the data of DB0 to DB3 is output to D0 to D3.

TCON 00-03, 10-13, 20-23, 30-33
The output of each bit is input to the hardware of the timer for control, but this is not shown in FIG. 1 because it is not directly related to the content of the present invention.

Next, the operation of the first timer mode control register will be described. Now, the address signals A2 to A0 are 110 (=
6 ^OCT ), the decoder activates AD6 and selects TCON 32, 22, 12, 02. If R / W = 0 here, the data of DB3 to DB0 is output to D3 to D0 via RW3 to RW0 and TCON3 is output.
Written to latches I1-I2 via TX in 2, 22, 12, 02. Since WB has a drive capacity sufficiently larger than I2, if the data of the latches of I1-I2 and WB are
Even if the output data is different, the data output from WB is written in the latch. If R / W = 1, then I1-
The data of the latch of I2 is output to D3 to D0 via TX in TCON32, 22, 12, and 02, and the data is R
It is read to DB3 to DB0 via B.

In this way, if the address is selected as 6 ^OCT , TCON32,
Each bit of 22, 12, 02, that is, the mask designation of the timers 3 to 0 can be written or read by one access.

Similarly, if addresses 0 ^OCT to 2 ^OCT are selected, timers 0 to 3 can be selected to write or read.

〔The invention's effect〕

As described above, according to the present invention, by addressing the registers in both the row direction and the column direction, it is possible to access two types of registers for each timer operation mode or each timer, and the program can be freely accessed. Not only does this increase the frequency and ease of program creation, but it also has the effect of significantly increasing the register access processing speed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. A0-A3 ... Address signal, DB0-DB3 ... Data path, R / W ... Read / write signal, AD0-AD
6 ... Address decoder, AX0-AX3 ... AD0
Output signal of AD3, AY0 to AY3 ... AD4 to AD7
Output signal of TCON00-03, TCON10-13, TCON20
~ 23, TCON30 ~ 33 ...... Register array, I0 ~ I
2 ... Inverter, TX, TY ... Transfer gate, D0-D3 ... Register array data line, RB ...
... Read buffer, WB ... Write buffer, RW0
RW3 ... Read / write buffer.

Claims (1)

[Claims] 1. A register array having a two-dimensional array, a row decoder for selecting any one row of the register array, and a column decoder for selecting any one column of the register array. Each cell is connected to a row data line via a row data selection circuit and connected to a column data line via a column data selection circuit, and the row data selection circuit is selected by the column decoder. Is selected by the row decoder, and the row data line and the column data line are connected for each data bit to serve as a data input / output line of a register array and connected to a write / read buffer controlled by a write / read signal. Characteristic register array circuit.