JPH0621785A - Chattering preventing system - Google Patents

Abstract

PURPOSE:To prevent the malfunction due to chattering from occurring without increasing a hardware scale in a digital circuit. CONSTITUTION:A start-up signal is sent out from a latch circuit 14 by depressing a push-button switch 11, and a central processing unit(CPU) 10 is started up by the start-up signal, and executes prescribed processing. The chattering occurs when the push-button switch is depressed or released, however, the CPU resets the latch circuit after the lapse of time set in advance when the prescribed processing is completed. Therefore, since the latch circuit can be prevented from being reset until the time set in advance elaspes after it is operated once, the influence due to the chattering generated when the push- button switch is released can be prevented from being given, and since only one time of operation of the digital circuit is performed by one time of operation of the push-button switch, the malfunction due to the chattering can be prevented from occurring without increasing the hardware scale.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chattering prevention system for preventing chattering in a digital circuit, and more particularly to a chattering prevention system for preventing a chattering in a digital circuit when a switch is activated.

[0002]

2. Description of the Related Art Generally, a digital circuit is provided with a chattering prevention circuit in hardware, and this chattering prevention circuit prevents malfunction of the digital circuit due to chattering.

Now, a conventional chattering prevention circuit will be outlined with reference to FIG. In addition, the digital circuit is provided with a central processing unit (CPU) 20 here, and C
A push button switch 21 is provided in the PU peripheral circuit.

First, referring to FIG. 2A, the CPU 20
Is connected to a peripheral circuit, and the peripheral circuit includes a chattering prevention circuit 22. An input port 23 and an output port 24 are connected to the CPU 20 via a CPU bus 20a, and a latch circuit with reset 25 is connected to the input port 23 and the output port 24. When a latch signal is applied to the L terminal, the latch circuit 25 outputs a switch-on signal to its output terminal (note that a predetermined voltage is applied to the D terminal). The output terminal of the chattering prevention circuit 22 is connected to the L terminal of the latch circuit 25, and the pull-up resistor 26 and the switch 21 are connected to the input terminal thereof.

Referring to FIGS. 2B and 2C as well, when the switch 21 is pressed, the chattering circuit 22 is supplied with the switch signal A. This switch signal A is low (Lo
w) level signal, which changes from a high level to a low level when the switch 21 is pressed. On the other hand, when the switch 21 is released, the low level changes to the high level, and the transmission of the switch signal is substantially stopped.

By the way, when the switch 21 is pressed and released, minute pulses are inevitably generated. That is, chattering occurs. The chattering prevention circuit 22 removes minute pulses (chattering) of the switch signal A and sends out a latch signal B.
The latch circuit 25 sends a switch-on signal C that changes from a low level to a high level with a timing when the latch signal B changes from a low level to a high level as a latch timing. This switch-on signal C is input port 2
3 to the CPU 20.

The CPU 20 monitors the signal (switch information) from the input port 23 at a predetermined cycle (step SS1), and when the switch-on signal is given, that is, when the switch information is at high level (step SS).
2) In response to the switch-on signal, the CPU 20 activates and executes the processing program (step SS3). On the other hand, when the switch information is at the low level, the time Tc is waited (step SS4), and the step SS1 is executed again.

When the CPU 20 finishes executing the processing program, it sends a reset pulse E to the latch circuit 25 via the output port 24 to reset the latch circuit 25 (step SS5). As a result, the switch-on signal C
Is stopped. That is, the output of the latch circuit 25 changes from high level to low level. Then, after waiting time Tc, the process returns to step SS1 again. That is, the CPU 20 monitors whether or not the switch-on signal has been sent at the predetermined cycle Tc.

[0009]

By the way, in the above digital circuit, a chattering prevention circuit by hardware is provided in order to prevent chattering due to the operation of the switch 21, and as a result, the hardware scale in the digital circuit increases. There is a problem that it ends up.

On the other hand, if a chattering circuit is not provided in order to prevent an increase in hardware scale, chattering occurs when the switch is pressed and released as described above. Therefore, when the switch is pressed as shown in FIG. The chattering causes the latch circuit to operate and the switch-on signal is transmitted. As a result, the CPU starts the program. Similarly, the latch circuit operates due to chattering when the switch is released, and a switch-on signal is transmitted. As a result, the CPU starts the program. That is, there is a problem that the CPU is activated twice by a single switch operation, and as a result, the CPU malfunctions.

An object of the present invention is to provide a chattering prevention system which does not cause malfunctions without increasing the hardware scale.

[0012]

According to the present invention, there is provided a processing system having a latch circuit for sending a start signal by pressing a push button switch and a digital circuit for starting a predetermined process by the start signal. It is a chattering prevention system for preventing malfunction of the digital circuit due to chattering that occurs when the push button switch is pressed and released, and a preset time when the predetermined process is completed. There is provided a chattering prevention system characterized by comprising reset means for resetting the latch circuit after a lapse of time.

[0013]

According to the present invention, when the predetermined processing by the digital circuit is completed, the latch circuit is reset after a preset time has elapsed. Generally, the push button switch is pressed for a very short time (pressing time), and if the preset time is set longer than this pressing time, it is latched by chattering generated when the push button switch is pressed and released. Even if the circuit operates twice for convenience, the latch circuit is not reset until the preset time elapses after the latch circuit operates once. Therefore, the chattering that occurs when the push button switch is released has no effect. Therefore, the digital circuit is activated only once by one operation of the push button switch, and malfunction due to chattering can be prevented without providing the chattering prevention circuit.

[0014]

EXAMPLES The present invention will be described below with reference to examples.

First, referring to FIG. 1A, the illustrated digital circuit includes a central processing unit (CPU) 10 and a push button switch 11 in a CPU peripheral circuit. The input port 12 and the output port 13 are connected to the CPU 10 via the CPU bus 10a, and the input port 1
A latch circuit with reset 14 is connected to the output port 2 and the output port 13. When a latch signal is applied to the L terminal, the latch circuit 14 outputs a switch-on signal to the output terminal thereof (note that a predetermined voltage is applied to the D terminal). The pull-up resistor 15 and the switch 11 are connected to the L terminal of the latch circuit 14.

Referring also to FIGS. 1B and 1C, when the switch 11 is pressed, the switch signal A is sent out as a latch signal. This switch signal A is a low level signal, and when the switch 11 is pressed, it is high (H).
It changes from the high level to the low level. On the other hand, when the switch 11 is released, the low level changes to the high level, and the transmission of the switch signal is substantially stopped.

The latch circuit 14 sends out a switch-on signal B which changes from low level to high level with the timing when the switch signal A changes from low level to high level as a latch timing.

By the way, when the switch 11 is pressed and released, chattering occurs as described above. As a result of this chattering, the switch-on signal B is transmitted in the vicinity where the switch signal A changes from the high level to the low level as shown in FIG. That is, the output of the latch circuit 14 changes from low level to high level. The switch-on signal B is given to the CPU 10 via the input port 12.

The CPU 10 monitors the signal (switch information) from the input port 12 at a predetermined cycle (Tc) (step S1), and when a switch-on signal is given,
That is, when the switch information is at the high level (step S2), the CPU 10 activates and executes the processing program in response to the switch-on signal (step S3). On the other hand, when the switch information is at the low level, the time Tc is waited (step S4) and the step S1 is executed again.

When the execution of the processing program is completed in the CPU 10, the preset time (Tr) is counted by the built-in timer (step S5), and when it is counted up, the reset pulse C is sent through the output port 13 to the latch circuit 14. To reset the latch circuit 14 (step S6). As a result, the transmission of the switch-on signal B is stopped. That is, the output of the latch circuit 14 changes from high level to low level. After that, the process returns to step 1 again after waiting the time Tc. That is, the CPU 10 has a predetermined cycle T
In c, it is monitored whether or not the switch-on signal is sent.

By the way, the above-mentioned preset time Tr
Is sufficiently longer than the time Ts during which the switch 11 is pressed, and as a result, even if the switch signal is transmitted again due to chattering that occurs when the switch signal A changes from the low level to the high level, the latch circuit 14 Output is still high level, and CPU1
In 0, even if the processing is stopped, the state where the switch-on signal is monitored is not returned until the set time Tr elapses, and as a result, the CPU 10 does not execute the program activation again. That is, the chattering that occurs when the switch signal A changes from the low level to the high level is substantially ignored. Therefore, it is possible to prevent an erroneous operation in which the program is activated twice by one switch operation.

Note that the latch circuit 1 is caused by chattering when the switch signal A changes from high level to low level.
4 may not latch, but in this case, there is no problem because the latch circuit 14 sends the switch-on signal at the timing when the switch signal A changes from the low level to the high level.

[0023]

As described above, according to the present invention, a malfunction due to chattering can be prevented without using a chattering prevention circuit, so that the program can be started accurately without increasing the hardware scale. is there.

[Brief description of drawings]

FIG. 1A is a diagram schematically showing an embodiment of a processing system to which a chattering prevention method according to the present invention is applied;
(B) is a timing chart showing the output signal of each part of the processing system shown in (a), and (c) is a flow chart for explaining the operation of the central processing unit (CPU) shown in (a).

2A is a diagram schematically showing a processing system to which a conventional chattering prevention method is applied, FIG. 2B is a timing chart showing output signals of respective parts of the processing system shown in FIG. 2A, and FIG. 6 is a flowchart for explaining the operation of the central processing unit (CPU) shown in (a).

FIG. 3 is a timing chart showing output signals of respective parts of the processing system when the chattering prevention circuit is removed in the processing system shown in FIG.

[Explanation of symbols]

 10 Central Processing Unit (CPU) 10a CPU Bus 11 Push Button Switch 12 Input Port 13 Output Port 14 Latch Circuit 15 Pull-up Resistor

Claims (2)

[Claims] 1. A push-button switch used in a processing system, comprising: a latch circuit that sends a start signal by pressing the push-button switch; and a digital circuit that is started by the start signal and executes a predetermined process. And a chattering prevention method for preventing malfunction of the digital circuit due to chattering that occurs when released, and a reset for resetting the latch circuit after a preset previous time has elapsed when the predetermined processing is completed. A chattering prevention method characterized in that means is provided. 2. The chattering prevention system, wherein the digital circuit according to claim 1 is a central processing unit, and the reset means is provided in the central processing unit.