JPH06216539A - Printed wiring board nad semiconductor device - Google Patents
Printed wiring board nad semiconductor deviceInfo
- Publication number
- JPH06216539A JPH06216539A JP5004584A JP458493A JPH06216539A JP H06216539 A JPH06216539 A JP H06216539A JP 5004584 A JP5004584 A JP 5004584A JP 458493 A JP458493 A JP 458493A JP H06216539 A JPH06216539 A JP H06216539A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- hole
- holes
- multilayer printed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、多層プリント配線板と
それを用いて作成したＰＧＡ等の半導体装置に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board and a semiconductor device such as PGA made by using the same.
【０００２】[0002]
【従来の技術】図３に示すプリント配線板Ａは、最外層
に積層板を用いて厚い絶縁層９が形成してあると共に内
部に多数の回路１を設けてある多層プリント配線板４と
して形成してあり、回路１同士を電気的に接続するため
のスルーホール３が設けてある。スルーホール３は多層
プリント配線板４にドリルで両表面に開口する貫通孔を
穿ち、その貫通孔の内壁に銅等でスルーホールメッキを
施すことによって形成されるものである。2. Description of the Related Art A printed wiring board A shown in FIG. 3 is formed as a multilayer printed wiring board 4 in which a thick insulating layer 9 is formed using a laminated plate as the outermost layer and a large number of circuits 1 are provided inside. A through hole 3 for electrically connecting the circuits 1 to each other is provided. The through hole 3 is formed by forming a through hole on both surfaces with a drill in the multilayer printed wiring board 4 and plating the inner wall of the through hole with copper or the like.
【０００３】[0003]
【発明が解決しようとする課題】しかし厚い絶縁層９を
持つ多層プリント板４では、多層プリント板４の厚みが
厚くなるために貫通孔を穿つ際にドリルが折れ易かっ
た。また多層プリント板４とドリルの摩擦によって熱が
発生し、多層プリント板４に含浸してある樹脂等が溶融
してスミヤが発生し、スルーホールメッキが不良になる
という問題があった。また多層プリント板４の板厚が厚
いので、貫通孔の厚み方向の長さと孔径との比率、つま
りアスペクト比が大きくなり、貫通孔内にメッキ液が入
りにくく、スルーホールメッキが施しにくくなるという
問題があった。さらにこの多層プリント配線板４を用い
て半導体装置を作成するにはスルーホール３に端子ピン
８を取り付けなければならないが、厚み方向の長さが長
いスルーホール３に半田が入りにくいために半田の充填
が不十分となり、端子ピン８の取り付けが確実におこな
うことができなかった。However, in the multilayer printed board 4 having the thick insulating layer 9, since the thickness of the multilayer printed board 4 becomes thick, the drill is easily broken when the through hole is formed. Further, there is a problem that heat is generated due to friction between the multilayer printed board 4 and the drill, the resin or the like impregnated in the multilayer printed board 4 is melted, smear is generated, and through-hole plating becomes defective. Further, since the thickness of the multilayer printed board 4 is large, the ratio of the length in the thickness direction of the through hole to the hole diameter, that is, the aspect ratio becomes large, and it is difficult for the plating solution to enter the through hole and for the through hole plating to be difficult. There was a problem. Further, in order to manufacture a semiconductor device using this multilayer printed wiring board 4, it is necessary to attach the terminal pins 8 to the through holes 3, but it is difficult for solder to enter the through holes 3 having a long length in the thickness direction. The filling was insufficient and the terminal pin 8 could not be securely attached.
【０００４】本発明は上記の点に鑑みてなされたもので
あり、スルーホールメッキに不良がないプリント配線板
を提供することを目的とするものである。また端子ピン
を確実に取り付けた半導体装置を提供することを目的と
するものである。The present invention has been made in view of the above points, and an object of the present invention is to provide a printed wiring board having no defect in through-hole plating. Another object of the present invention is to provide a semiconductor device in which the terminal pins are securely attached.
【０００５】[0005]
【課題を解決するための手段】本発明に係るプリント配
線板Ａは、内部に回路１を設けた多層プリント配線板４
にスルーホール３を形成し、スルーホール３の開口部５
を覆わないようにして多層プリント配線板４の表面に絶
縁基板６を積層して成ることを特徴とするものである。A printed wiring board A according to the present invention is a multilayer printed wiring board 4 having a circuit 1 therein.
The through hole 3 is formed in the opening, and the opening 5 of the through hole 3 is formed.
It is characterized in that the insulating substrate 6 is laminated on the surface of the multilayer printed wiring board 4 so as not to cover it.
【０００６】また本発明に係る半導体装置Ｂは、上記プ
リント配線板Ａに半導体チップ７を実装すると共にスル
ーホール３の開口部５に端子ピン８を設けて成ることを
特徴とするものである。The semiconductor device B according to the present invention is characterized in that the semiconductor chip 7 is mounted on the printed wiring board A and the terminal pins 8 are provided in the openings 5 of the through holes 3.
【０００７】[0007]
【作用】内部に回路１を設けた多層プリント配線板４に
スルーホール３を形成し、スルーホール３の開口部５を
覆わないようにして多層プリント配線板４の表面に絶縁
基板６を積層したので、スルーホール３を形成するため
の貫通孔を厚みの薄い多層プリント配線板４に穿つこと
によってドリリングの時に発生する熱を減少させること
ができ、スミアの発生を防止することができる。また貫
通孔のアスペクト比が小さくすることができ、メッキ液
が貫通孔内に入り易くなる。The through hole 3 is formed in the multilayer printed wiring board 4 having the circuit 1 inside, and the insulating substrate 6 is laminated on the surface of the multilayer printed wiring board 4 so as not to cover the opening 5 of the through hole 3. Therefore, by forming a through hole for forming the through hole 3 in the thin multilayer printed wiring board 4, heat generated during drilling can be reduced and smear can be prevented. Further, the aspect ratio of the through hole can be reduced, and the plating solution can easily enter the through hole.
【０００８】さらに上記プリント配線板Ａに半導体チッ
プ７を実装すると共にスルーホール３の開口部５に端子
ピン８を設けたので、端子ピン８を取り付けたスルーホ
ール３に半田が入り易くなる。Further, since the semiconductor chip 7 is mounted on the printed wiring board A and the terminal pin 8 is provided in the opening 5 of the through hole 3, solder easily enters the through hole 3 to which the terminal pin 8 is attached.
【０００９】[0009]
【実施例】以下本発明を実施例によって詳述する。多層
プリント配線板４は回路１を形成した複数枚の銅張板を
プリプレグを介して積層することによって形成すると共
に、スルーホール３を設けたものである。スルーホール
３は多層プリント配線板４にドリリングして両表面に開
口する貫通孔を形成し、貫通孔の内壁に銅等のメッキ液
を流し込んでスルーホールメッキを施すと共に回路１同
士を電気的に接続することによって形成されるものであ
る。EXAMPLES The present invention will be described in detail below with reference to examples. The multilayer printed wiring board 4 is formed by laminating a plurality of copper clad boards on which the circuit 1 is formed via a prepreg, and is provided with a through hole 3. The through hole 3 is drilled on the multilayer printed wiring board 4 to form a through hole that opens on both surfaces, a plating solution such as copper is poured into the inner wall of the through hole to perform through hole plating, and the circuits 1 are electrically connected to each other. It is formed by connecting.
【００１０】絶縁基板６は積層板やプラスチック成形板
やセラミック板等で形成してあり、大きさは上記多層プ
リント配線板４と同じである。また絶縁基板６には両表
面に開口し、多層プリント配線板４に設けたスルーホー
ル３の外径よりも大きく開口する端子孔１１が設けてあ
り、この端子孔１１はスルーホール３の位置に対応した
位置に形成されるものである。この絶縁基板６を多層プ
リント配線板４の表面に接着して積層することによって
図１に示すようなプリント配線板Ａが作成されるもので
あり、絶縁層９は絶縁基板６によって形成されるもので
ある。The insulating substrate 6 is formed of a laminated plate, a plastic molded plate, a ceramic plate or the like, and has the same size as that of the multilayer printed wiring board 4. Further, the insulating substrate 6 is provided with a terminal hole 11 which is open on both surfaces and is larger than the outer diameter of the through hole 3 provided in the multilayer printed wiring board 4, and the terminal hole 11 is located at the position of the through hole 3. It is formed at a corresponding position. A printed wiring board A as shown in FIG. 1 is produced by adhering and laminating the insulating substrate 6 on the surface of the multilayer printed wiring board 4, and the insulating layer 9 is formed by the insulating substrate 6. Is.
【００１１】このようにして作成されるプリント配線板
Ａは、絶縁基板６を積層する前の厚みの薄い多層プリン
ト配線板４においてスルーホール３を形成するので、ド
リリングの時に使用されるドリルの磨耗を減少させ、ド
リルが折れることも防止できるものである。またドリリ
ングの時に発生する熱を減少させることができるので、
スミヤの発生を防止することができる。また貫通孔のア
スペクト比が小さくすることができので、メッキ液が入
り易くなるものである。In the printed wiring board A thus produced, the through holes 3 are formed in the thin multilayer printed wiring board 4 before the insulating substrates 6 are laminated, so that the drill used during drilling is worn out. It is also possible to prevent the drill from breaking. Also, since the heat generated during drilling can be reduced,
It is possible to prevent smear. Moreover, since the aspect ratio of the through holes can be reduced, the plating solution can easily enter.
【００１２】図２には上記プリント配線板Ａを用いて作
成したＰＰＧＡ（プラスチックピングリッドアレイ）等
の半導体装置Ｂが示してあり、プリント配線板Ａの多層
プリント配線板４に半導体チップ７が搭載してあると共
に半導体チップ７はボンディングワイヤー１０によって
回路１と電気的に接続してある。またプリント配線板Ａ
の端子孔１１を貫通して多層プリント配線板４のスルー
ホール３に端子ピン８が圧入され、半田で固定されてい
る。FIG. 2 shows a semiconductor device B such as a PPGA (Plastic Pin Grid Array) made by using the printed wiring board A, and a semiconductor chip 7 is mounted on the multilayer printed wiring board 4 of the printed wiring board A. In addition, the semiconductor chip 7 is electrically connected to the circuit 1 by the bonding wire 10. Printed wiring board A
The terminal pin 8 is press-fitted into the through hole 3 of the multilayer printed wiring board 4 through the terminal hole 11 of FIG.
【００１３】この実施例においては多層プリント配線板
４の厚み方向の長さが小さいスルーホール３に端子ピン
８を取り付けることができるので、スルーホール３内に
半田等を十分に充填して端子ピン８を固定することがで
きるものである。In this embodiment, the terminal pins 8 can be attached to the through holes 3 having a small length in the thickness direction of the multilayer printed wiring board 4, so that the through holes 3 can be sufficiently filled with solder or the like. 8 can be fixed.
【００１４】[0014]
【発明の効果】上記のように本発明は、内部に回路を設
けた多層プリント配線板にスルーホールを形成し、スル
ーホールの開口部を覆わないようにして多層プリント配
線板の表面に絶縁基板を積層したので、スルーホールを
形成するための貫通孔を厚みの薄い多層プリント配線板
に穿つことによってドリリングの時に発生する熱を減少
させることができ、スミアの発生を防止することがで
き、スルーホールメッキが確実に施すことができるもの
である。また貫通孔のアスペクト比が小さくすることが
でき、メッキ液が貫通孔内に入り易くなり、スルーホー
ルメッキを確実に施すことができるものである。As described above, according to the present invention, a through hole is formed in a multilayer printed wiring board having a circuit inside, and an insulating substrate is formed on the surface of the multilayer printed wiring board so as not to cover the opening of the through hole. By stacking the through holes for forming the through holes in the thin multilayer printed wiring board, it is possible to reduce the heat generated during drilling and prevent the occurrence of smear. Hole plating can be reliably applied. Further, the aspect ratio of the through hole can be reduced, the plating solution can easily enter the through hole, and the through hole plating can be reliably performed.
【００１５】また上記プリント配線板に半導体チップを
実装すると共にスルーホールの開口部に端子ピンを設け
たので、端子ピンを取り付けたスルーホールに半田は入
り易くなり、スルーホール内に半田等を十分に充填して
端子ピンを固定することができ、プリント配線板に端子
ピンを確実に取り付けることができるものである。Further, since the semiconductor chip is mounted on the printed wiring board and the terminal pin is provided in the opening of the through hole, the solder easily enters the through hole to which the terminal pin is attached, and the solder or the like is sufficiently filled in the through hole. It is possible to fix the terminal pins by filling in and to securely attach the terminal pins to the printed wiring board.
【図１】本発明の一実施例のプリント配線板の断面図で
ある。FIG. 1 is a cross-sectional view of a printed wiring board according to an embodiment of the present invention.
【図２】同上の半導体装置の断面図である。FIG. 2 is a sectional view of the above semiconductor device.
【図３】従来例の断面図である。FIG. 3 is a sectional view of a conventional example.
１ 回路 ３ スルーホール ４ 多層プリント配線板 ５ 開口部 1 Circuit 3 Through Hole 4 Multilayer Printed Wiring Board 5 Opening
Claims (2)
にスルーホールを形成し、スルーホールの開口部を覆わ
ないようにして多層プリント配線板の表面に絶縁基板を
積層して成るプリント配線板。1. A printed wiring board formed by forming a through hole in a multilayer printed wiring board having a circuit inside and laminating an insulating substrate on the surface of the multilayer printed wiring board so as not to cover the opening of the through hole. .
導体チップを実装すると共にスルーホールに端子ピンを
設けて成る半導体装置。2. A semiconductor device in which a semiconductor chip is mounted on the printed wiring board according to claim 1 and terminal pins are provided in through holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5004584A JPH06216539A (en) | 1993-01-14 | 1993-01-14 | Printed wiring board nad semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5004584A JPH06216539A (en) | 1993-01-14 | 1993-01-14 | Printed wiring board nad semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06216539A true JPH06216539A (en) | 1994-08-05 |
Family
ID=11588093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5004584A Pending JPH06216539A (en) | 1993-01-14 | 1993-01-14 | Printed wiring board nad semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06216539A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005286209A (en) * | 2004-03-30 | 2005-10-13 | Denso Corp | Element device |
| KR100954488B1 (en) * | 2003-06-26 | 2010-04-22 | 엘지디스플레이 주식회사 | A multi-layer pcb and the fabricating method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02237142A (en) * | 1989-03-10 | 1990-09-19 | Sumitomo Bakelite Co Ltd | Manufacture of board for semiconductor mounting use |
| JPH02271653A (en) * | 1989-04-13 | 1990-11-06 | Sumitomo Bakelite Co Ltd | Manufacture of substrate for mounting semiconductor |
| JPH03101196A (en) * | 1989-09-13 | 1991-04-25 | Ibiden Co Ltd | Multilayer printed interconnection board and its manufacture |
-
1993
- 1993-01-14 JP JP5004584A patent/JPH06216539A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02237142A (en) * | 1989-03-10 | 1990-09-19 | Sumitomo Bakelite Co Ltd | Manufacture of board for semiconductor mounting use |
| JPH02271653A (en) * | 1989-04-13 | 1990-11-06 | Sumitomo Bakelite Co Ltd | Manufacture of substrate for mounting semiconductor |
| JPH03101196A (en) * | 1989-09-13 | 1991-04-25 | Ibiden Co Ltd | Multilayer printed interconnection board and its manufacture |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100954488B1 (en) * | 2003-06-26 | 2010-04-22 | 엘지디스플레이 주식회사 | A multi-layer pcb and the fabricating method |
| JP2005286209A (en) * | 2004-03-30 | 2005-10-13 | Denso Corp | Element device |
| JP4512980B2 (en) * | 2004-03-30 | 2010-07-28 | 株式会社デンソー | Element device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19981110 |