JPH06216525A - Manufacture of multi layer printed circuit board - Google Patents

Manufacture of multi layer printed circuit board

Info

Publication number
JPH06216525A
JPH06216525A JP50A JP757493A JPH06216525A JP H06216525 A JPH06216525 A JP H06216525A JP 50 A JP50 A JP 50A JP 757493 A JP757493 A JP 757493A JP H06216525 A JPH06216525 A JP H06216525A
Authority
JP
Japan
Prior art keywords
photosensitive polyimide
polyimide film
wiring pattern
photosensitive
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50A
Other languages
Japanese (ja)
Inventor
Kazuhiko Yamano
和彦 山野
Makoto Miyazaki
信 宮崎
Shunjiro Imagawa
俊次郎 今川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP50A priority Critical patent/JPH06216525A/en
Publication of JPH06216525A publication Critical patent/JPH06216525A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve packing density, by covering an insulating board including a wiring pattern and a circuit element with a photosensitive polymeric insulating film, and forming an interlayer conductor in a longitudinal hole after the longitudinal hole is formed in the photosensitive insulating film in an exposure- development step. CONSTITUTION:An alumina board 2 having a base wiring pattern 3 and a resistor 4 thereon is coated with photosensitive polyimide to form a first photosensitive polyimide film 5. A viahole 6 is formed in the first photosensitive polyimide film 5 in an exposure-development step. After the first photosensitive polyimide film 5 is hardened in a thermo-setting step, a first copper plated circuit 7 and an intermediate wiring pattern 8 are formed on the first photosensitive polyimide film 5. Then, a second photosensitive polyimide film 9 is formed over the first photosensitive polyimide film 5. Finally, a necessary electronic component other than the resistor 4 is mounted on the second photosensitive polyimide film 9.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、LSI等の電子部品の
実装基板として用いられる多層配線基板の製造方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board used as a mounting board for electronic parts such as LSI.

【0002】[0002]

【従来の技術】従来から多層配線基板を製造する方法と
して、絶縁基板の両面にスクリーン印刷法等によって配
線パターンを形成したのち、絶縁基板にスルーホールを
形成して両面の配線パターンを互いに接続する方法があ
る。また、特開昭61−294895号公報に示された
ように、配線パターンが形成された絶縁基板上に層間絶
縁膜として低誘電率の高分子膜(例えばポリイミド膜)
を一層ないし複数層形成し、これら高分子膜中に層間配
線を形成して多層化する方法もある。
2. Description of the Related Art Conventionally, as a method of manufacturing a multilayer wiring board, wiring patterns are formed on both sides of an insulating substrate by screen printing or the like, and then through holes are formed in the insulating substrate to connect the wiring patterns on both sides to each other. There is a way. In addition, as disclosed in Japanese Patent Laid-Open No. 61-294895, a low dielectric constant polymer film (for example, a polyimide film) is used as an interlayer insulating film on an insulating substrate on which a wiring pattern is formed.
There is also a method of forming a single layer or a plurality of layers and forming an interlayer wiring in these polymer films to form a multilayer.

【0003】[0003]

【発明が解決しようとする課題】ところで、上記従来の
方法には次のような問題があった。すなわち、絶縁基板
の両面をスルーホールで製造する第1の方法では、一枚
の絶縁基板の両面どうしスルーホールで接続するだけで
あるので、高密度な実装を実現できない。また、高分子
膜を用いる第2の方法では、高密度実装および多層化が
可能であるが、層間配線等のパターンが複雑になるう
え、LSI、抵抗、およびコンデンサ等の電子部品は高
分子膜表面にしか実装できず、その意味で高密度実装に
限界があった。
However, the above-mentioned conventional method has the following problems. That is, according to the first method of manufacturing both surfaces of the insulating substrate with the through holes, since only the both surfaces of one insulating substrate are connected with the through holes, high-density mounting cannot be realized. Also, the second method using a polymer film enables high-density mounting and multi-layering, but the pattern of interlayer wiring and the like becomes complicated, and electronic parts such as LSI, resistors, and capacitors are polymer films. Since it can only be mounted on the surface, there was a limit to high-density mounting in that sense.

【0004】したがって、本発明においては、多層配線
基板の実装密度を高めることを目的としている。
Therefore, an object of the present invention is to increase the packaging density of the multilayer wiring board.

【0005】[0005]

【課題を解決するための手段】このような目的を達成す
るために、本発明においては、絶縁基板に配線パターン
および回路素子を印刷形成する工程と、配線パターンお
よび回路素子が形成された絶縁基板上に感光性高分子絶
縁膜を形成する工程と、前記感光性高分子絶縁膜に露光
現像プロセスにより層間接続用の縦穴を形成するととも
に、該縦穴に、前記配線パターンを感光性高分子絶縁膜
表面まで導出する層間配線を形成する工程とを含んで多
層配線基板の製造方法を構成した。
In order to achieve such an object, in the present invention, a step of printing a wiring pattern and a circuit element on an insulating substrate, and an insulating substrate on which the wiring pattern and the circuit element are formed. A step of forming a photosensitive polymer insulating film thereon, and forming a vertical hole for interlayer connection in the photosensitive polymer insulating film by an exposure and development process, and forming the wiring pattern in the vertical hole with the photosensitive polymer insulating film. A method of manufacturing a multilayer wiring board is configured including a step of forming an interlayer wiring leading to the surface.

【0006】[0006]

【作用】上記構成によれば、抵抗といったような回路素
子を絶縁基板と感光性高分子絶縁膜との層間に配設でき
る分、実装密度は高まることになる。
According to the above structure, the circuit density such as a resistor can be disposed between the insulating substrate and the photosensitive polymer insulating film, so that the mounting density is increased.

【0007】また、回路素子の一部を層間に配設できる
分、これら回路素子を接続する配線のパターンは簡略化
が可能になる。
Further, since a part of the circuit elements can be arranged between the layers, the wiring pattern connecting these circuit elements can be simplified.

【0008】[0008]

【実施例】以下、本発明の一実施例を図面を参照して詳
細に説明する。図1は本発明の多層配線基板の製造方法
によって製造された多層配線基板の構造を示す断面図で
あり、図2はこの多層配線基板の製造工程をそれぞれ示
す断面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing a structure of a multilayer wiring board manufactured by a method for manufacturing a multilayer wiring board according to the present invention, and FIG. 2 is a sectional view showing a manufacturing process of the multilayer wiring board.

【0009】この多層配線基板1は高純度(例えば9
9.5%)のアルミナ基板2を有している。アルミナ基
板2の表面にはAg−Pdからなる基底部配線パターン
3と、この基底部配設パターン3に接続されたRuO2
からなる抵抗4が配設されている。アルミナ基板2表面
には感光性高分子絶縁膜である第1感光性ポリイミド膜
5が配設されている。第1感光性ポリイミド膜5には厚
み方向にバイアホール6が穿たれており、このバイアホ
ール6には第1銅メッキ配線7が設けられている。第1
銅メッキ配線7は第1感光性ポリイミド膜5表面まで延
出して中間部配線パターン8を形成している。第1銅メ
ッキ配線7は基底部配線パターン3に接続されており、
これによって基底部配線パターン3は第1感光性ポリイ
ミド膜5表面まで導出されている。
This multilayer wiring board 1 has a high purity (for example, 9
9.5%) of the alumina substrate 2. On the surface of the alumina substrate 2, a base wiring pattern 3 made of Ag-Pd and RuO 2 connected to the base arrangement pattern 3 are formed.
A resistor 4 consisting of is provided. A first photosensitive polyimide film 5, which is a photosensitive polymer insulating film, is provided on the surface of the alumina substrate 2. A via hole 6 is formed in the first photosensitive polyimide film 5 in the thickness direction, and a first copper-plated wiring 7 is provided in the via hole 6. First
The copper-plated wiring 7 extends to the surface of the first photosensitive polyimide film 5 to form an intermediate wiring pattern 8. The first copper-plated wiring 7 is connected to the base wiring pattern 3,
As a result, the base wiring pattern 3 is led out to the surface of the first photosensitive polyimide film 5.

【0010】第1感光性ポリイミド膜5の表面にはさら
に第2感光性ポリイミド膜9が配設されている。第2感
光性ポリイミド膜9には厚み方向にバイアホール10が
穿たれており、このバイアホール10には第2銅メッキ
配線11が設けられている。第2銅メッキ配線11は第
2感光性ポリイミド膜9表面まで延出して表層部配線パ
ターン12を形成している。第2銅メッキ配線11は中
間部配線パターン8に接続されており、これによって中
間部配線パターン8は第2感光性ポリイミド膜9表面ま
で導出されている。そして、第2感光性ポリイミド膜9
表面の表層部配線パターン12上には前記した抵抗4以
外の電子部品(LSI、コンデンサ等)13,…が表面
実装されている。
A second photosensitive polyimide film 9 is further provided on the surface of the first photosensitive polyimide film 5. A via hole 10 is formed in the second photosensitive polyimide film 9 in the thickness direction, and a second copper plated wiring 11 is provided in the via hole 10. The second copper-plated wiring 11 extends to the surface of the second photosensitive polyimide film 9 to form a surface layer wiring pattern 12. The second copper-plated wiring 11 is connected to the intermediate wiring pattern 8 so that the intermediate wiring pattern 8 is extended to the surface of the second photosensitive polyimide film 9. Then, the second photosensitive polyimide film 9
Electronic components (LSI, capacitors, etc.) other than the resistor 4 are mounted on the surface wiring pattern 12 on the surface.

【0011】次に上記構成の多層配線基板1の製造工程
を順を追って説明する。まず、アルミナ基板2にAg−
Pdの配線パターン原料をスクリーン印刷によってパタ
ーンニングしたうえで850℃で焼付けて基底部配線パ
ターン3を形成する。さらに、アルミナ基板2上に抵抗
原料であるRuO2をスクリーン印刷によってパターン
ニングしたうえで850℃で焼付けて抵抗4を形成す
る。このように、抵抗4の形成を、高温加熱処理が施せ
ない感光性ポリイミド膜5,9を形成する前に行うの
で、なんら問題なく抵抗4をアルミナ基板2上に形成す
ることができる。図2(a)参照 基底部配線パターン3および抵抗4を形成したアルミナ
基板2上に感光性ポリイミド樹脂(例えば東レ社製フォ
トニース:商品名)を塗布して、第1感光性ポリイミド
膜5を形成する。 図2(b)
参照 さらに、第1感光性ポリイミド膜5に露光現像プロセス
を施してバイアホール6を形成したうえで第1感光性ポ
リイミド膜5を加熱硬化させる。図2(c)参照 このように形成した第1感光性ポリイミド膜5上にセミ
アディティブ法により第1銅メッキ配線7および中間部
配線パターン8を形成する。すなわち、第1感光性ポリ
イミド膜5にヒドラジンによる表面処理を施し、さらに
パラジュウムによる触媒活性化処理を施す。そして、こ
のような処理を施したのち、アルミナ基板2を硫酸銅メ
ッキ液中に浸漬することにより、第1感光性ポリイミド
膜5表面、およびバイアホール10の底部に露出してい
る基底部配線パターン8上に膜厚500オングストロー
ムの無電解銅メッキ層20を形成する。このようにして
形成した無電解銅メッキ層20上にフォトレジスト(例
えばヘキスト社製AZ4620:商品名)を塗布し、さ
らにフォトレジストに露光現像プロセスを施してレジス
トパターン21を形成する。そして、このレジストパタ
ーン21から露出している無電解メッキ層20の部分に
電解銅メッキを施して、5μmの電解銅メッキ層22を
形成する。 図2(d)参
照 そして、レジストパターン21およびレジストパターン
21の下層に位置する無電解銅メッキ層20を除去する
ことにより、第1銅メッキ配線7および中間部配線パタ
ーン8を形成する。 図2(e)
参照 さらに、第1感光性ポリイミド膜5上に第2感光性ポリ
イミド膜9を形成し、この第2感光性ポリイミド膜9
に、上記した第1感光性ポリイミド膜5と同様の工程を
施すことにより、バイアホール10、第2銅メッキ配線
11、および表層部配線パターン12を形成する。
図2(f)参照 最後に第2感光性ポリイミド膜9の表層部配線パターン
12上に、前記した抵抗4以外で必要な電子部品(LS
I、コンデンサ等)を表面実装し、これによって図1に
示す多層配線基板1が完成する。
Next, the manufacturing process of the multilayer wiring board 1 having the above structure will be described step by step. First, Ag-
The Pd wiring pattern raw material is patterned by screen printing and then baked at 850 ° C. to form the base wiring pattern 3. Further, RuO 2 , which is a resistance material, is patterned on the alumina substrate 2 by screen printing and then baked at 850 ° C. to form the resistance 4. In this way, the resistor 4 is formed before forming the photosensitive polyimide films 5 and 9 that cannot be subjected to the high-temperature heat treatment, so that the resistor 4 can be formed on the alumina substrate 2 without any problem. See FIG. 2A. A photosensitive polyimide resin (for example, Photo Nice: trade name, manufactured by Toray Industries, Inc.) is applied on the alumina substrate 2 on which the base wiring pattern 3 and the resistor 4 are formed to form the first photosensitive polyimide film 5. Form. Figure 2 (b)
Reference Further, the first photosensitive polyimide film 5 is subjected to an exposure and development process to form a via hole 6, and then the first photosensitive polyimide film 5 is cured by heating. Referring to FIG. 2C, the first copper-plated wiring 7 and the intermediate wiring pattern 8 are formed on the first photosensitive polyimide film 5 thus formed by the semi-additive method. That is, the first photosensitive polyimide film 5 is subjected to a surface treatment with hydrazine and further subjected to a catalyst activation treatment with palladium. After such treatment, the alumina substrate 2 is dipped in a copper sulfate plating solution to expose the base wiring pattern exposed on the surface of the first photosensitive polyimide film 5 and the bottom of the via hole 10. An electroless copper plating layer 20 having a film thickness of 500 angstrom is formed on the substrate 8. A photoresist (for example, AZ4620 manufactured by Hoechst: trade name) is applied on the electroless copper-plated layer 20 thus formed, and the photoresist is subjected to an exposure and development process to form a resist pattern 21. Then, electrolytic copper plating is applied to the portion of the electroless plating layer 20 exposed from the resist pattern 21 to form a 5 μm electrolytic copper plating layer 22. Then, the resist pattern 21 and the electroless copper-plated layer 20 located under the resist pattern 21 are removed to form the first copper-plated wiring 7 and the intermediate wiring pattern 8. Figure 2 (e)
Further, a second photosensitive polyimide film 9 is formed on the first photosensitive polyimide film 5, and the second photosensitive polyimide film 9 is formed.
Then, the same steps as those for the first photosensitive polyimide film 5 described above are performed to form the via holes 10, the second copper plated wirings 11, and the surface layer wiring patterns 12.
See FIG. 2 (f) Finally, on the surface layer wiring pattern 12 of the second photosensitive polyimide film 9, electronic components (LS) other than the resistor 4 described above are required.
I, capacitors, etc.) are surface-mounted, and the multilayer wiring board 1 shown in FIG. 1 is completed by this.

【0012】本件出願者は、このような多層配線基板の
製造方法により、どの程度実装の高密度化が促進された
のかを調べるために、比較品として次のようなものを作
成し、実施例品との間で実装度を比較したところ、実施
例品は比較品のほぼ1.35倍の実装度が得られること
がわかった。なお、比較品とは、実施例品と同様、アル
ミナ基板上にバイアホールを備えた感光性ポリイミド膜
を2層積層形成し、抵抗以外の構成要素、すなわち、基
底部、中間部、および表層部の各配線パターン、第1、
第2の各銅メッキ配線をそれぞれ形成し、さらには、抵
抗を含むすべての電子部品を第2感光性ポリイミド膜表
面に表面実装することにより得られたものをいう。ま
た、実装度は所定の回路構成を形成するのに最小限必要
な基板の平面積として算出した。
The applicant of the present invention prepared the following as a comparative product in order to investigate to what extent the high density of mounting was promoted by the manufacturing method of such a multilayer wiring board, and When the mounting degree was compared with that of the product, it was found that the mounting strength of the example product was about 1.35 times that of the comparative product. The comparative product is the same as the embodiment product in that two layers of a photosensitive polyimide film having a via hole are laminated on an alumina substrate, and constituent elements other than the resistance, that is, a base portion, an intermediate portion, and a surface layer portion are formed. Each wiring pattern, first,
The second copper-plated wiring is formed, and further, all electronic components including resistors are surface-mounted on the surface of the second photosensitive polyimide film. The mountability was calculated as the minimum plane area of the substrate required to form a predetermined circuit configuration.

【0013】[0013]

【発明の効果】以上のように本発明によれば、抵抗等の
回路素子を、絶縁基板と感光性高分子絶縁膜とからなる
多層配線基板の層間に配設することが可能になったの
で、その分、実装の高密度化が達成できた。
As described above, according to the present invention, it becomes possible to arrange a circuit element such as a resistor between layers of a multilayer wiring board including an insulating substrate and a photosensitive polymer insulating film. Therefore, high density packaging was achieved.

【0014】また、回路素子の一部を多層配線基板の層
間に配設できるので、これら回路素子を接続する配線の
パターンを簡略化することが可能になり、その分でもさ
らに実装の高密度化が可能になった。
Further, since a part of the circuit elements can be arranged between the layers of the multilayer wiring board, it is possible to simplify the wiring pattern for connecting these circuit elements, and the mounting density is further increased by that amount. Became possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の製造方法によって製造され
た多層配線基板の構造を示す断面図である。
FIG. 1 is a cross-sectional view showing the structure of a multilayer wiring board manufactured by a manufacturing method according to an embodiment of the present invention.

【図2】本発明の一実施例の多層配線基板の製造方法の
各工程をそれぞれ示す断面図である。
FIG. 2 is a cross-sectional view showing each step of the method for manufacturing a multilayer wiring board according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

2 アルミナ基板 3 基底部配線パターン 4 抵抗 5 第1感光性ポリイミド膜 6 バイアホール 7 第1銅メッキ配線 8 中間部配線パターン 2 Alumina substrate 3 Base wiring pattern 4 Resistor 5 First photosensitive polyimide film 6 Via hole 7 First copper plated wiring 8 Intermediate wiring pattern

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶縁基板に配線パターンおよび回路素子を
印刷形成する工程と、 配線パターンおよび回路素子が形成された絶縁基板上に
感光性高分子絶縁膜を形成する工程と、 前記感光性高分子絶縁膜に露光現像プロセスにより層間
接続用の縦穴を形成するとともに、該縦穴に、前記配線
パターンを感光性高分子絶縁膜表面まで導出する層間配
線を形成する工程とを含むことを特徴とする多層配線基
板の製造方法。
1. A step of printing a wiring pattern and a circuit element on an insulating substrate, a step of forming a photosensitive polymer insulating film on the insulating substrate on which the wiring pattern and the circuit element are formed, and the photosensitive polymer. Forming a vertical hole for interlayer connection in the insulating film by an exposure and development process, and forming an interlayer wiring for leading the wiring pattern to the surface of the photosensitive polymer insulating film in the vertical hole. Wiring board manufacturing method.
JP50A 1993-01-20 1993-01-20 Manufacture of multi layer printed circuit board Pending JPH06216525A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50A JPH06216525A (en) 1993-01-20 1993-01-20 Manufacture of multi layer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50A JPH06216525A (en) 1993-01-20 1993-01-20 Manufacture of multi layer printed circuit board

Publications (1)

Publication Number Publication Date
JPH06216525A true JPH06216525A (en) 1994-08-05

Family

ID=11669584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50A Pending JPH06216525A (en) 1993-01-20 1993-01-20 Manufacture of multi layer printed circuit board

Country Status (1)

Country Link
JP (1) JPH06216525A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1075038A (en) * 1996-06-28 1998-03-17 Ngk Spark Plug Co Ltd Wiring board and its manufacture method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1075038A (en) * 1996-06-28 1998-03-17 Ngk Spark Plug Co Ltd Wiring board and its manufacture method

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