JPH06216375A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH06216375A
JPH06216375A JP523293A JP523293A JPH06216375A JP H06216375 A JPH06216375 A JP H06216375A JP 523293 A JP523293 A JP 523293A JP 523293 A JP523293 A JP 523293A JP H06216375 A JPH06216375 A JP H06216375A
Authority
JP
Japan
Prior art keywords
thin film
polycrystalline silicon
gate electrode
silicon thin
oxidation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP523293A
Other languages
Japanese (ja)
Inventor
Masami Hane
正巳 羽根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP523293A priority Critical patent/JPH06216375A/en
Publication of JPH06216375A publication Critical patent/JPH06216375A/en
Pending legal-status Critical Current

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To weaken the inverse short channel effect that the threshold value of an MOSFET once increases as the channel length is made shorter, when the MOS type transistor is finely miniaturized. CONSTITUTION:After the material for a gate electrode 3 of an MOS type semiconductor device is patterned and formed, a process for forming a polycrystalline silicon thin film 4 is introduced, and only the formed polycrystalline silicon thin film 4 is subjected to oxidation treatment. In the case of re-oxidation treatment of the polycrystalline silicon thin film 4 deposited on a single crystal, diffusion acceleration of impurities which is generated at the time of oxidizing single crystal silicon is not generated. Hence the nonuniformity of impurity distribution in a channel which is caused by oxidation acceleration diffusion at the gate end and ordinary diffusion just under the gate, and which has been a problem in the conventional method can be restrained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、集積回路に用いる半導
体装置であるMOS型トランジスタを、その性能を保っ
たままより微細化できるようにする半導体装置の製造方
法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device which can be further miniaturized while maintaining its performance, which is a MOS type transistor used in an integrated circuit.

【0002】[0002]

【従来の技術】大規模集積回路に使用する半導体装置
は、できるだけ微細であることが集積度を高める上で不
可欠である。それぞれの素子を微細化することで集積度
を向上できるが、MOS型電界効果トランジスタ(MO
SFET)を微細化する、すなわち、ある設計ルールの
MOSFETのチャネル長を縮小すると、それにつれて
MOSFETのしきい値が設計値より下がる短チャネル
効果や、しきい値が上がる逆短チャネル効果という問題
が顕在化してくる。特に、チャネル長の減少に伴い、し
きい値が一旦上昇した後、急激に低下するような特性を
示す場合を逆短チャネル効果と呼び、長チャネルのトラ
ンジスタ特性を保ったまま素子寸法を縮小する設計を困
難にしている。
2. Description of the Related Art It is essential for semiconductor devices used in large-scale integrated circuits to be as fine as possible in order to increase the degree of integration. Although the degree of integration can be improved by miniaturizing each element, MOS field effect transistors (MO
If the SFET) is miniaturized, that is, the channel length of the MOSFET of a certain design rule is reduced, a short channel effect in which the threshold value of the MOSFET falls below the design value and an inverse short channel effect in which the threshold value rises are associated with it. It becomes apparent. In particular, the case where the threshold value rises and then drops sharply as the channel length decreases is called the reverse short channel effect, and the element size is reduced while maintaining the long channel transistor characteristics. Making design difficult.

【0003】[0003]

【発明が解決しようとする課題】MOSFETの逆短チ
ャネル効果は、ゲート電極端近傍とゲート電極中央近傍
でのチャネル部分の不純物濃度が異なること、またチャ
ネル長が長い場合は、ゲート端近傍の影響は小さいが、
チャネル長が短くなるにつれてゲート電極端近傍の影響
が強くなることで生じる。チャネル部の不純物分布がゲ
ート電極端と中央部で異なる原因としては、半導体表面
を酸化したときに生じる半導体中の不純物の拡散増速が
ある。図2は、単結晶半導体基板1のチャネル部の全面
にゲート酸化膜2を形成し、酸化膜2に覆われた半導体
基板1上にゲート電極3をパターニングして形成した後
に、再度表面に再酸化膜5の形成を行う従来法にしたが
った工程を行った後の断面状態を示している。すなわ
ち、ゲート電極3で覆われていない半導体基板1の表面
上での酸化のため、基板半導体中の不純物の拡散は増速
する(図2の領域7)が、ゲート電極3の下部の基板半
導体での不純物は、酸化が電極によってマスクされるた
め、酸化時の温度で通常の拡散が行われる(図2の領域
6)。ここでの不純物の分布について次に述べる。
The reverse short channel effect of the MOSFET is that the impurity concentration of the channel portion near the gate electrode end is different from that near the center of the gate electrode, and when the channel length is long, the influence near the gate end is affected. Is small,
This occurs because the influence near the edge of the gate electrode becomes stronger as the channel length becomes shorter. The cause of the difference in the impurity distribution in the channel portion between the gate electrode end and the central portion is the acceleration of diffusion of impurities in the semiconductor that occurs when the semiconductor surface is oxidized. In FIG. 2, the gate oxide film 2 is formed on the entire surface of the channel portion of the single crystal semiconductor substrate 1, and the gate electrode 3 is patterned and formed on the semiconductor substrate 1 covered with the oxide film 2. The cross-sectional state after performing the step according to the conventional method of forming the oxide film 5 is shown. That is, the diffusion of impurities in the substrate semiconductor is accelerated due to the oxidation on the surface of the semiconductor substrate 1 not covered by the gate electrode 3 (region 7 in FIG. 2), but the substrate semiconductor below the gate electrode 3 is increased. Since the oxidation of the impurities is masked by the electrode, normal diffusion is performed at the temperature during the oxidation (region 6 in FIG. 2). The distribution of impurities here will be described below.

【0004】従来のMOSFET製造工程においては、
チャネル領域にしきい値制御用として不純物をイオン注
入する。この不純物の深さ方向の分布は、表面側が低
く、基板中で最大値を持つガウス分布のような分布とな
る。したがって、不純物が拡散すると、そのような分布
がなだらかになり、表面側は濃度が上昇する。この概略
を図3に示す。図3において、分布8は、イオン注入後
であって、酸化前の不純物分布,分布9は、熱処理後の
不純物分布,分布10は、熱処理時に酸化増速拡散が起
こった場合の不純物分布である。酸化による増速拡散の
ため、チャネル端近傍での表面濃度の上昇は、酸化の影
響を受けにくいチャネル中央部近傍よりも大きくなり、
局部的なしきい値が上昇する。
In the conventional MOSFET manufacturing process,
Impurities are ion-implanted into the channel region for controlling the threshold value. The distribution of the impurities in the depth direction is low on the surface side and has a maximum value in the substrate, such as a Gaussian distribution. Therefore, when the impurities diffuse, such a distribution becomes gentle and the concentration increases on the surface side. This outline is shown in FIG. In FIG. 3, distribution 8 is an impurity distribution after ion implantation and before oxidation, distribution 9 is an impurity distribution after heat treatment, and distribution 10 is an impurity distribution when oxidation enhanced diffusion occurs during heat treatment. . Due to the accelerated diffusion due to oxidation, the increase in the surface concentration near the channel edge is larger than that near the channel center, which is less susceptible to oxidation.
The local threshold rises.

【0005】短チャネルMOSFETでは、局部的なし
きい値の上昇分がチャネル全体に対し大きなウェイトを
占めるようになるため、しきい値が設計値に対してず
れ、設計が困難になるという問題が顕在化してきた。
In the short-channel MOSFET, the local increase in threshold value occupies a large weight for the entire channel, so that there is a problem that the threshold value deviates from the design value and the design becomes difficult. It has turned into.

【0006】本発明の目的は、素子寸法を縮少する時に
発生する逆短チャネル効果を抑制する半導体装置の製造
方法を提供することにある。
An object of the present invention is to provide a method of manufacturing a semiconductor device which suppresses the reverse short channel effect which occurs when the element size is reduced.

【0007】[0007]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置の製造方法は、ゲート電極
形成工程と、再酸化工程とを有する半導体装置の製造方
法であって、ゲート電極形成工程は、基板上のMOS型
半導体装置のゲート電極となる材料をパターニングし
て、基板上にゲート電極を形成する工程であり、再酸化
工程は、パターン化された前記ゲート電極を含む基板の
全面を覆ってシリコン薄膜を成膜し、該シリコン薄膜の
みを酸化処理することにより、該シリコン薄膜を酸化膜
に再酸化する工程である。
To achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including a gate electrode forming step and a reoxidation step. The forming step is a step of patterning a material to be a gate electrode of the MOS type semiconductor device on the substrate to form a gate electrode on the substrate, and the reoxidation step is a step of forming a substrate including the patterned gate electrode. In this step, a silicon thin film is formed so as to cover the entire surface, and only the silicon thin film is oxidized to reoxidize the silicon thin film into an oxide film.

【0008】また、前記シリコン薄膜は、多結晶シリコ
ンまたはアモルファスシリコンである。
The silicon thin film is polycrystalline silicon or amorphous silicon.

【0009】[0009]

【作用】次に本発明の作用を説明する。図1は、本発明
に係る半導体装置の製造方法を工程順に示す断面図であ
る。まず、図1(a)において、単結晶半導体基板1上
にゲート酸化膜2を選択的に形成し、ゲート酸化膜2上
にゲート電極3を設ける。
Next, the operation of the present invention will be described. 1A to 1D are cross-sectional views showing a method of manufacturing a semiconductor device according to the present invention in the order of steps. First, in FIG. 1A, a gate oxide film 2 is selectively formed on a single crystal semiconductor substrate 1, and a gate electrode 3 is provided on the gate oxide film 2.

【0010】その後、図1(b)に示すように、半導体
基板1及びゲート電極3上に多結晶シリコン4を薄く成
膜する。
Thereafter, as shown in FIG. 1B, a thin film of polycrystalline silicon 4 is formed on the semiconductor substrate 1 and the gate electrode 3.

【0011】次に、図1(c)に示すように、多結晶シ
リコン4の厚味分だけ酸化処理し、多結晶シリコン4を
酸化膜5に再酸化する。
Next, as shown in FIG. 1C, the polycrystalline silicon 4 is oxidized by a thickness corresponding to the thickness of the polycrystalline silicon 4 to re-oxidize the polycrystalline silicon 4 into an oxide film 5.

【0012】ここで、酸化による不純物の増速拡散につ
いて説明する。単結晶半導体中の拡散は、主に結晶中の
点欠陥により引き起こされる。単結晶半導体表面の酸化
は、酸化膜と結晶の界面での酸化反応によって進むが、
その際、反応は点欠陥を生じ、この点欠陥は、一部が半
導体基板中に流入し、その結果、不純物の拡散が増速さ
れる。
Here, accelerated diffusion of impurities by oxidation will be described. Diffusion in single crystal semiconductors is mainly caused by point defects in the crystal. Oxidation of the surface of the single crystal semiconductor proceeds by the oxidation reaction at the interface between the oxide film and the crystal,
At that time, the reaction causes a point defect, and a part of the point defect flows into the semiconductor substrate, and as a result, diffusion of impurities is accelerated.

【0013】しかし、単結晶シリコン上に多結晶シリコ
ンを成膜し、これを酸化した場合、下層の単結晶シリコ
ン中の不純物分布には、酸化による増速拡散現象はほと
んど見られないことが、実験事実として報告されてい
る。この理由としては、多結晶シリコンは、ほぼ単結晶
の微小な結晶粒と、その間の結晶粒界とからなり、特に
結晶粒界は、原子的な構造が曖昧なため、酸化反応によ
り発生した点欠陥が多結晶シリコン中の粒界に吸収さ
れ、下地の単結晶シリコンに流出しないためであると、
推測されている。
However, when polycrystalline silicon is formed on single crystal silicon and is oxidized, an enhanced diffusion phenomenon due to oxidation is hardly found in the impurity distribution in the lower single crystal silicon. It is reported as an experimental fact. The reason for this is that polycrystalline silicon is composed of minute crystal grains, which are almost single crystals, and crystal grain boundaries between them. In particular, the crystal grain boundaries have a vague atomic structure, so that they are generated by an oxidation reaction. This is because the defects are absorbed in the grain boundaries in the polycrystalline silicon and do not flow out to the underlying single crystal silicon.
Has been speculated.

【0014】そこで本発明のように、ゲート電極形成後
の再酸化工程前に、多結晶シリコン膜を薄く成膜した
後、酸化を行うようにすれば、酸化は多結晶シリコン膜
上で起こるため、下地単結晶半導体中の不純物の拡散増
速は生ぜず、チャネル領域での不純物拡散状況を一様に
することが可能となる。多結晶シリコン膜が酸化により
全て酸化膜に変わり、消滅した後は、増速拡散が起こり
始めるので、ここで再酸化を終えるようにすれば、逆短
チャネル効果が抑制できる。
Therefore, as in the present invention, if the polycrystalline silicon film is thinly formed before the reoxidation step after the gate electrode is formed and then the oxidation is performed, the oxidation occurs on the polycrystalline silicon film. The diffusion speed of impurities in the base single crystal semiconductor does not increase, and the impurity diffusion state in the channel region can be made uniform. After the polycrystalline silicon film is completely converted into an oxide film by oxidation and disappears, accelerated diffusion starts to occur, so that if the reoxidation is finished here, the reverse short channel effect can be suppressed.

【0015】また、この薄い多結晶シリコン膜は、所望
の再酸化膜厚が得られるように充分薄くし、結局再酸化
により全て酸化膜に変えてしまうため、後工程には影響
せず、最終的な構造は、従来の製造方法によるもとの外
見上は、変わらないようにできる。
Further, this thin polycrystalline silicon film is made sufficiently thin so that a desired reoxidized film thickness can be obtained, and eventually it is entirely converted into an oxide film by reoxidation. The conventional structure can be unchanged in appearance from the conventional manufacturing method.

【0016】[0016]

【実施例】以下、半導体装置形成方法に関する本発明の
典型的な一実施例を図により説明する。図1(a)から
(c)は、一実施例における各工程での断面図にも相当
している。図1(a)に示すように、単結晶シリコン基
板1の表面を、酸素雰囲気中で酸化し、100オングス
トロームの厚みの二酸化シリコン膜(以下、単に酸化膜
という)2を成長させた後、ゲート電極3となる多結晶
シリコンを低圧化学的気相成長法(LPCVD法)によ
りシリコン基板1の全面に0.5μmの厚みで成膜した
後、ドライエッチング法によりゲート電極部をパターン
化した。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A typical embodiment of the present invention relating to a method for forming a semiconductor device will be described below with reference to the drawings. FIGS. 1A to 1C also correspond to cross-sectional views in each process in one embodiment. As shown in FIG. 1A, the surface of the single crystal silicon substrate 1 is oxidized in an oxygen atmosphere to grow a silicon dioxide film (hereinafter, simply referred to as an oxide film) 2 having a thickness of 100 Å, and then a gate is formed. Polycrystalline silicon to be the electrode 3 was deposited on the entire surface of the silicon substrate 1 to a thickness of 0.5 μm by the low pressure chemical vapor deposition method (LPCVD method), and then the gate electrode portion was patterned by the dry etching method.

【0017】次に図1(b)に示すように、再び多結晶
シリコン薄膜4をLPCVDにより500オングストロ
ームの厚みでシリコン基板1の全面に成膜した。成膜温
度は550℃程度とし、粒径を平均で20オングストロ
ーム程度と膜厚に比較して充分小さくした。
Next, as shown in FIG. 1 (b), a polycrystalline silicon thin film 4 was again formed on the entire surface of the silicon substrate 1 by LPCVD to a thickness of 500 angstroms. The film forming temperature was about 550 ° C., and the average particle size was about 20 Å, which was sufficiently smaller than the film thickness.

【0018】次にこれをドライ酸化雰囲気で、900
℃,30分の酸化処理を行った。これは、500オング
ストロームの厚みの多結晶シリコン薄膜4をちょうど全
て酸化しきる条件をあらかじめ求めておいたものであ
る。この酸化処理により多結晶シリコン薄膜4は、ゲー
ト再酸化膜5に再酸化された。
Next, this is dried in a dry oxidizing atmosphere at 900
Oxidation treatment was performed at 30 ° C. for 30 minutes. This is a condition in which the polycrystalline silicon thin film 4 having a thickness of 500 Å is completely oxidized in advance. By this oxidation treatment, the polycrystalline silicon thin film 4 was reoxidized to the gate reoxidized film 5.

【0019】尚、実施例では、多結晶シリコン薄膜4を
用いたが、これに代えてアモルファスシリコン薄膜を用
いても同様の効果が得られる。
Although the polycrystalline silicon thin film 4 is used in the embodiment, the same effect can be obtained by using an amorphous silicon thin film instead of the polycrystalline silicon thin film 4.

【0020】[0020]

【発明の効果】以上説明したように本発明の半導体装置
製造方法によれば、ゲート再酸化工程前に、多結晶シリ
コン薄膜を導入し、ゲート再酸化多結晶シリコン薄膜を
介して酸化する工程とすることにより、酸化による下地
シリコン基板中の不純物分布の増速拡散を抑制し、チャ
ネル領域で一様な不純物分布を実現し、逆短チャネル効
果を抑制できるという効果を有している。また、従来法
に比較して余分な多結晶シリコン薄膜は、充分薄くてよ
いため、酸化しきってしまうことにより後工程には影響
を与えない。
As described above, according to the semiconductor device manufacturing method of the present invention, before the gate reoxidation step, a step of introducing a polycrystalline silicon thin film and oxidizing it through the gate reoxidation polycrystalline silicon thin film is performed. This has the effect of suppressing accelerated diffusion of the impurity distribution in the underlying silicon substrate due to oxidation, realizing a uniform impurity distribution in the channel region, and suppressing the reverse short channel effect. Further, since the extra polycrystalline silicon thin film may be sufficiently thin as compared with the conventional method, it does not affect the subsequent steps due to being completely oxidized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明により形成されるMOSFETの製造工
程途中の一連のゲート電極形成工程における断面形状を
示す断面図である。
FIG. 1 is a cross-sectional view showing a cross-sectional shape in a series of gate electrode forming steps in the process of manufacturing a MOSFET formed according to the present invention.

【図2】従来法によるゲート電極形成工程での酸化とそ
の不純物に対する影響(酸化増速拡散)を説明する図で
ある。
FIG. 2 is a diagram for explaining oxidation in a gate electrode formation process by a conventional method and its influence on impurities (oxidation enhanced diffusion).

【図3】チャネル領域での不純物の深さ方向分布が酸化
時の拡散によりどのように変化するかを説明する図であ
る。
FIG. 3 is a diagram for explaining how the depthwise distribution of impurities in a channel region changes due to diffusion during oxidation.

【符号の説明】[Explanation of symbols]

1 単結晶シリコン基板 2 ゲート酸化膜 3 ゲート電極 4 多結晶シリコン薄膜 5 再酸化膜 6 通常拡散領域 7 酸化増速拡散領域 8 酸化前の不純物濃度深さ方向分布 9 酸化増速拡散が無い場合の熱処理後の不純物濃度深
さ方向分布 10 酸化増速拡散がある場合の熱処理後の不純物濃度
深さ方向分布
1 Single Crystal Silicon Substrate 2 Gate Oxide Film 3 Gate Electrode 4 Polycrystalline Silicon Thin Film 5 Reoxidation Film 6 Normal Diffusion Region 7 Oxidation Enhanced Diffusion Region 8 Impurity Concentration Before Oxidation Depth Distribution 9 Oxidation Enhanced Diffusion Impurity concentration depth direction distribution after heat treatment 10 Impurity concentration depth direction distribution after heat treatment when there is oxidation enhanced diffusion

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 ゲート電極形成工程と、再酸化工程とを
有する半導体装置の製造方法であって、 ゲート電極形成工程は、基板上のMOS型半導体装置の
ゲート電極となる材料をパターニングして、基板上にゲ
ート電極を形成する工程であり、 再酸化工程は、パターン化された前記ゲート電極を含む
基板の全面を覆ってシリコン薄膜を成膜し、該シリコン
薄膜のみを酸化処理することにより、該シリコン薄膜を
酸化膜に再酸化する工程であることを特徴とする半導体
装置の製造方法。
1. A method of manufacturing a semiconductor device comprising a gate electrode forming step and a reoxidation step, wherein the gate electrode forming step comprises patterning a material to be a gate electrode of a MOS type semiconductor device on a substrate, The step of forming a gate electrode on the substrate, the re-oxidation step, by forming a silicon thin film to cover the entire surface of the substrate including the patterned gate electrode, by oxidizing only the silicon thin film, A method of manufacturing a semiconductor device, comprising a step of reoxidizing the silicon thin film into an oxide film.
【請求項2】 前記シリコン薄膜は、多結晶シリコンま
たはアモルファスシリコンであることを特徴とする請求
項1に記載の半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon thin film is polycrystalline silicon or amorphous silicon.
JP523293A 1993-01-14 1993-01-14 Manufacture of semiconductor device Pending JPH06216375A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP523293A JPH06216375A (en) 1993-01-14 1993-01-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP523293A JPH06216375A (en) 1993-01-14 1993-01-14 Manufacture of semiconductor device

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JPH06216375A true JPH06216375A (en) 1994-08-05

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5656641A (en) * 1979-10-13 1981-05-18 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS56146254A (en) * 1980-04-14 1981-11-13 Matsushita Electronics Corp Manufacture of semiconductor device
JPS5852850A (en) * 1981-09-24 1983-03-29 Nec Corp Manufacture of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5656641A (en) * 1979-10-13 1981-05-18 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS56146254A (en) * 1980-04-14 1981-11-13 Matsushita Electronics Corp Manufacture of semiconductor device
JPS5852850A (en) * 1981-09-24 1983-03-29 Nec Corp Manufacture of semiconductor device

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