JPH06214752A - Sorting processor - Google Patents

Abstract

PURPOSE:To provide a sorting processor adding codes indicating that data are equal when equal data exist in a sorting processing and adding the number of the bytes of an equal part to data when data are not equal so as to output them. CONSTITUTION:A comparator 4 comparing the contents of first and second registers 9 and 10 with each other, judging the register of a larger value or that of a smaller value and outputting the result, a result register 7 storing the judged result of the comparator 4 and designating either of the registers whose compared result value is larger or smaller, a duplex flag generation part 11 monitoring the contents of the result register 7, and detecting a state that the compared results of the comparator 4 are equal to each other when the results are equal so as to generate a flag, and a counter for the number of equal bytes 12 counting the number of times of comparison in the comparator 4 while the compared results are equal to each other are provided. A comparator control part 8 refers to the duplex key flag generation part 11 and the counter for the number of equal bytes 12 after the comparison of previously given lengths is terminated and outputs the flag and the number of the equal bytes to a prescribed position of data in a local memory 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sort processing device,
In particular, the present invention relates to a sort processing device for checking the magnitude relationship of numerical values or characters in two input data and rearranging the input data in the ascending or descending order.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing an example of a conventional sort processing apparatus of this type.

As shown in FIG. 4, a sort processing device mainly composed of hardware of the related art has an input buffer 1 for temporarily storing input data and an input buffer 1 connected to an output side of the input buffer 1. A first register 9 that stores the output as first comparison data, a local memory 3 that receives the output of the input buffer 1, and a local memory 3
Contents of the second register 10 that receives the second comparison data output from the first register 9 and the contents of the first register 9 and the second register 10 according to a comparison instruction signal generated by a comparator control unit 8A described later. The output that stores the output data output from the local memory 3 and the result register 7 that stores the result compared by the comparator 4, and the output that is output to the outside by the output instruction signal The buffer 2 and the length of the digit to be compared in the comparison data (that is, the key length) stored from the outside are stored, the number of times of the comparison instruction signal is counted, and the stored digit length is set to the stored digit length. A key length counter 5 that outputs a count end instruction signal to the comparator control unit 8A when it reaches, and a record length storage that stores the record length of the input data to be compared and is connected to the comparator control unit 8A. Compared to 6, the input buffer 1 and the output buffer 2 and the local memory 3 device 4 and the key length counter 5
And a comparator control unit 8A for controlling the record length storage unit 6.

The local memory 3 has first and second storage areas, and the first input data is stored in, for example, the first storage area, and then the data is output from the input buffer 1. Then, if the input data is already present in the first storage area, the data in the first storage area is moved to the second storage area, and the newly input data is stored in the first storage area. Let

FIG. 3 is an explanatory diagram showing an example of the relationship between the data to be processed by the conventional sort processing apparatus of this type shown in FIG. 4 and the sort processing apparatus of the present invention described later and the sort area for this data. Is.

Referring to FIGS. 3 and 4, target data is data having a predetermined record length. In FIG. 3, the data length has a record length of 20 digits.
In the record length storage unit 6, 20 is previously input and stored as a record length from the outside.

In FIG. 3, the portion of the data to be actually sorted is the key area 21, which has three consecutive digits from the top of the input data. The digit number 3 is input to the key length counter 5 from the outside and stored in advance.

The comparator 4 starts from the most significant digit of the upper three digits (key area 21) of the data stored in the first and second registers 9 and 10 by one comparison instruction signal. , The stored contents of the first and second registers are compared to check the magnitude relationship, and a signal for designating a predesignated one, for example, a register storing the larger data is output to the result register 7. To do. In the following description, it is assumed that the comparator 4 outputs a signal designating the register storing the data having the larger comparison result value.

If the result of the above comparison by the comparator 4 is:
When both are equal, no signal designating either the first or second register 9 or 10 is output.

The start instruction signal is externally supplied from the comparator control unit 8A.
In addition, the comparator control unit 8A outputs an output instruction signal to the output buffer 2 and outputs the contents already stored in the output buffer 2 as output data to the outside.

Subsequently, the comparator control unit 8A refers to the contents of the result register 7 to retrieve the data in the first or second storage area in the local memory 3 corresponding to the designated first or second register. The output data is output to the output buffer 2 and the second register 10 and stored therein, and then the data remaining in the local memory 3 is transferred to the second storage area of the local memory 3. In this case, if the remaining data is in the second storage area of the local memory 3, it is left as it is.

If neither the first register 9 nor the second register 10 is designated by the result register 7, the corresponding data in the local memory 3 storing the contents of the second register 10, That is, the comparator controller 8A causes the output buffer 2 to output the data stored in the second storage area of the local memory 3.

Next, the comparator control unit 8A outputs the data stored in the second storage area to the second register 10 as the second comparison data, stores the data, and stores the data stored in the input buffer 1 until then. Is stored in the first storage area of the local memory 3 and is also stored in the first register 9 as the first comparison data.

Next, the comparator controller 8A inputs new input data added from the outside and stores it in the input buffer 1.

Subsequently, the comparator control unit 8A outputs a comparison instruction signal to the comparator 4, causes the key length counter 5 to count the number of comparison instruction signals, and the comparator 4 causes the first and second registers 9 to 9a. And the contents of 10 are compared. When the comparison for the number of digits stored in the key length counter 5 has already been completed, the comparator control unit 8A does not output the comparison instruction signal.

That is, if the key length stored in the key length counter 5 is 3, as shown in FIG. 3, the first comparison data and the second comparison data stored in the above-mentioned registers 9 and 10, respectively. The comparator 4 compares the values from the most significant digit of the key area 21 of the comparison data to the third most significant digit.

The above-described operation is repeated in the order of output / input / comparison by the record length which is input from the outside and stored in the record length storage unit 6 in advance, and as a result, the first comparison data is the first. If it is larger than the value of the comparison data of 2,
The value designating the first register is stored in the result register. If the values in the key area 21 of the first comparison data and the second comparison data compared by the comparator 4 are equal, the value designating any register is not stored in the result register 7.

The operation of the comparator controller 8A ends when an end instruction signal is externally applied.

If N sort processing devices of this kind are connected in series, the order of data can be rearranged in the order of 2 ^N -1 pieces of data from the largest to the smallest or from the smallest to the largest.

Even if the content of the target key area is not a number but a character, a number is assigned to the character in advance in the order of arrangement of the respective characters, and when the comparator 4 compares the numbers, the number is assigned to the character. By comparison, the data can be rearranged by sorting in alphabetical order or Iloha order.

[0021]

In the above-described conventional sort processing apparatus, if the key area 2 of the data to be processed is
Even if the values of 1 are the same, these plural data which are equal to each other are only output in the order in which they are input,
Since a code indicating equality is not given to these data, in order to distinguish two or more data having the same value of the key area 21 from each other, the sort processing device is used in this way. All the data in the processed data group needs to be processed by the program for checking the contents of the above-mentioned entire record, but the sort process is the first to be processed by such a program. It has a drawback that it takes a lot of time to target all the data sorted by the apparatus.

The above-mentioned conventional sorting is also used when grouping records in which a part of the key area is the same or performing a totaling process on a specific key of the key area of the grouped data group. It is necessary to perform grouping processing and totaling processing by the program for all the data groups processed by the processing device, but the processing target is sorted by the program to target all the data first sorted by the processing device It has the disadvantage that it takes more time than it takes to execute the process again.

Another conventional sorting apparatus is disclosed in, for example, Japanese Patent Laid-Open No. 61-16326 and Japanese Patent Laid-Open No. 61-28942.
Although disclosed in Japanese Patent Laid-Open No. 4-7, these sort processing devices also have the same drawbacks as the sort processing device of FIG.

An object of the present invention is to add a code indicating that data having the same key areas of target data to each other when sorting is performed by the sort processing device, and immediately before the last stage of the sort processing device. By outputting a record with added information indicating how many digits are counted from the beginning of the key area from the output record, the processing algorithm and the amount of information in the program as described above can be minimized. An object of the present invention is to provide a sort processing device capable of shortening processing time by a program.

[0025]

According to the present invention, when an output instruction signal is applied, the data stored until then is output to the outside, and an output buffer for storing the input data, and the output instruction. When the signal is applied, the data to which the output flag is added among the data stored inside is output as the next output data, and the first comparison data is stored in the area where the next output data is output, A local memory for outputting the other remaining stored data as the second comparison data and, when an input instruction signal is applied, outputs the input data stored until then as the first comparison data. And also stores an input buffer for storing new input data, a first register for storing the first comparison data, and the second comparison data. No. 2 register, a comparator controlled by a comparison instruction signal to compare the contents of the first and second registers to determine the magnitude relationship, and a result register for storing the determination result of the magnitude relationship which is the output of the comparator. And, the contents of the result register are monitored, and if there is an equal relationship, a double key flag generating unit for generating and storing a double key flag, and a record length of each data to be sorted inputted in advance from outside is stored. Record length storage unit, a key length counter that stores the length of data to be compared by the comparator that is input in advance from the outside as a key length, and start by a start instruction signal added from the outside, By referring to the contents of the result register and the dual key flag generation unit, when the dual key flag is generated, the two data stored in the local memory are stored. A dual key flag is given to the defined area, and the corresponding data side in the local memory storing the data belonging to the one designated by the result register in the magnitude relation is designated as the next output data, or When the double key flag generation unit is generating the double key flag, the same data in the local memory that is stored in the second register is designated as the next output data, and the record length storage unit A comparator control unit that outputs an output instruction signal and an input instruction signal for the stored record length, and outputs the comparison instruction signal for the key length of the key length counter. A sort processing device for performing the above is obtained.

Further, according to the present invention, there is further provided a match byte number counter for referring to the comparison result of the comparator and storing the number of comparison bytes until the contents of the first and second registers do not match. The comparator control unit is started by a start instruction signal applied from the outside, refers to the contents of the result register and the double key flag generation unit, and stores the local memory when the double key flag is generated. A double key flag is given to a predetermined area of two data, and the corresponding data side in the local memory which stores the data belonging to the one designated by the result register in the magnitude relation is set as the next output data. Or as the same as the one stored in the second register when the dual key flag generator is generating the dual key flag. The data in the local memory is designated as the next output data, the contents of the coincidence byte number counter are stored in a predetermined area of the next output data, and only the record length stored in the record length storage section is output. A sort processing device is obtained which outputs an instruction signal and an input instruction signal, and outputs the comparison instruction signal for the key length of the key length counter.

[0027]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of a sort processing apparatus according to one embodiment of the present invention, and FIG. 2 is a sort processing according to another embodiment of the present invention in which a plurality of sort processing apparatuses shown in FIG. 1 are connected. It is a block diagram of an apparatus.

The sort processing apparatus according to one embodiment of the present invention has already been described with reference to FIG. 4 except for the components other than the comparator control unit 8, the double key flag control unit 11 and the matching byte number counter 12, as shown in FIG. Since it is the same as the conventional device of this type, the description of these already-described components will be omitted.

That is, in the sort processing apparatus of the present invention shown in FIG. 1, when the contents of the result register 7 are monitored and the comparison result by the comparator 4 is equivalent, this state is detected and the double key flag is set. Double key flag generation unit 11 to be set
And the comparison result of the comparator 4 is referred to, and the first register 9
Of the key area 2 in the contents of 2 and the contents of the second register 10.
The matching byte number counter 12 that counts the number of matching digits (that is, the number of bytes) from the beginning of 1 and the comparison control unit 8 is used instead of the comparison control unit 8A described in FIG. The comparator control unit 8 is connected to the key length counter 5, the record length storage unit 6, the input buffer 1, the output buffer 2, the local memory 3, the comparator 4 and the result register 7, and the double key flag generation unit 11 is also provided. Is also connected to.

The double key flag generator 11 monitors the contents of the result register 7 and, if the comparison result is equal after the comparison has been performed by the comparator 4 the number of times stored in the key length counter 5. Detects this result and sets a dual key flag.

The matching byte number counter 12 refers to the number of comparisons and the comparison result in the comparator 4, and the contents of the first register 9 and the contents of the second register 10 match from the beginning of the key area 21. Count the number of digits. This makes it possible to detect how many bytes from the head of the key area 21 are the same in the two data to be compared.

When the comparator control unit 8 outputs the comparison instruction signal to the comparator 4 by the number of the values stored in the key length counter 5, the contents of the result register 7 are referred to and the first register 9 or the first register 9 When any one of the two registers 10 is designated, the same data as the data stored in the register designated by the result register 7 is locally stored in the data stored in the local memory 3. Memory 3
From the output register 2 to the output buffer 2 is the same as the comparator control unit 8A described in FIG. 4, but the result register 7 is the first register 9 and the second register 10.
When neither of the two is specified, the contents of the double key flag generation unit 11 are referred to. If the double key flag is set, the data of the respective data stored in the first and second storage areas in the local memory 3 are A code (flag) indicating that each data is equal is given to a predetermined position (for example, the end), and then the contents of the matching byte number counter 12 are referred to and the first storage in the local memory 3 is performed. The matching byte number count value is written at a predetermined position (for example, the tail of the double key flag) of the data stored in the area. Of the data thus added, the data stored in the second storage area of the local memory 3 together with the flag thus added are output buffer 2
The data stored in the first storage area in the local memory 3 is moved to the second storage area and stored therein. In this way, the data output from the output buffer 2 has a three-digit key area 21 followed by a remaining record area 22, a double key flag area 23,
It has a matching byte number counting area 24.

After the value of the key area in the data is compared by the comparator 4 as described above, the contents of the result register 7 and the double key flag generator 11 are referred to, and the contents of the local memory 3 are stored based on the reference result. Other than the operation of controlling the output of the data of the
Is the same as

In another embodiment of the present invention shown in FIG. 2, the sort processing devices 30A to 30N described in FIG.
N + 1 units up to +1 are connected in series. The input buffer 1 of the first-stage sort processing device 30A receives input data from the outside, and the output of the output buffer 2 of the first-stage sort processing device 30A is changed to the second stage. Connected to the input buffer 1 of the sort processing apparatus 30B, and thereafter the output buffer 2 of the sort processing apparatus of the previous stage is connected to the input buffer 1 of the sort processing apparatus of the next stage.
Is connected to, and by connecting in this way, 2 ^N −
For one piece of data, the value of the key area can be output to the outside from the output buffer 2 of the sort processing device 30N in order from the largest value to the smallest value.

Further, the sort processing device 3 described with reference to FIG.
By connecting 0N + 1 to the final stage and inputting sorted input data from the sort processing device 30N, the sort processing device detects the double key and counts the number of matching bytes with the data output immediately before. You can

If the result register 7 designates the smaller one of the key areas for the two data compared by the respective comparators 4 of the respective sort processing devices 30A to 30N + 1, the result shown in FIG. From the sort processing device 30N + 1, the data is sorted and output in order from the smallest key area to the largest key area.

Further, the sort processing device 30 shown in FIG.
As N + 1, the sort processing device shown in FIG. 1 is used,
For other sort processing devices, even if the sort processing device shown in FIG. 4 is used, all sort processing devices 30A
From 30N + 1 to 30N + 1, the same operation as that using the sort processing apparatus shown in FIG. 1 can be performed.

[0039]

As described above, the sort processing apparatus of the present invention changes the value of the designated key area in the target data from the largest value to the smallest value or vice versa. When sorting, rearranging, and outputting, when the data has the same key value, the data is output with a double key flag indicating that the values compared with the predetermined positions of these data are equal. Therefore, after that, when processing whether a value equal to the value of these key areas exists by using a separately prepared program, it suffices to focus only on such double key flag portion in the entire data. Therefore, there is an effect that the processing time by the program can be shortened as compared with the conventional case where data having no double key flag is sorted.

Further, since the number of matching bytes of the key area with the data output immediately before is stored and output at a predetermined position in the sorted data, the items of the plurality of items in these key areas are then matched. Detect and group,
When processing such as totaling is performed by a separately prepared program, it is sufficient to focus only on such a portion of the matching byte number information in the entire data, so that the processing time by the program can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of a sort processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of a sort processing apparatus according to another embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a relationship between data to be sorted and a key area to be sorted in FIGS. 1 and 4.

FIG. 4 is a block diagram of an example of a conventional sort processing device.

[Explanation of symbols]

 1 Input Buffer 2 Output Buffer 3 Local Memory 4 Comparator 5 Key Length Counter 6 Record Length Storage 7 Result Register 8 Comparator Control 8A Comparator Control 9 First Register 10 Second Register 11 Double Key Flag Generator 12 Matching Bytes Counter 21 Key Area 22 Remaining Record Area 23 Double Key Flag Area 24 Matching Bytes Count Area 30A to 30N + 1 Sort Processing Device

Claims (5)

[Claims] 1. When an output instruction signal is applied, the data that has been stored up to that time is output to the outside, and an output buffer that stores the input data, and an output buffer that is internally stored when the output instruction signal is applied. The data to which the output flag is added is output as the next output data, and the first comparison data is stored in the area where the next output data is output, and the other stored data is stored. When a local memory that outputs two data as the second comparison data and an input instruction signal are added, the input data stored until then is output as the first comparison data, and the newly input data is output. An input buffer for storing, a first register for storing the first comparison data, a second register for storing the second comparison data, and a comparison instruction signal A comparator for controlling the contents of the first and second registers to determine the magnitude relationship, a result register for storing the determination result of the magnitude relationship which is the output of the comparator, and the contents of the result register. A double key flag generation unit that monitors and generates and stores a double key flag when they are in the same relationship, and a record length storage unit that stores the record length of each data to be sorted that is input in advance from the outside. , A key length counter that stores the length of data to be compared by the comparator, which is input in advance from the outside, as a key length, and a start instruction signal that is externally applied to start the result register and the double key flag. Referring to the contents of the generation unit, when the double key flag is generated, the double key flag is stored in a predetermined area of the two data stored in the local memory. Assign the corresponding data side in the local memory that stores the data belonging to the one designated by the result register among the magnitude relations, or designate the corresponding data side as the next output data, When the key flag is being generated, the same data in the local memory as that stored in the second register is designated as the next output data, and only the record length stored in the record length storage unit is designated. A sort processing device, comprising: a comparator control unit that outputs an output instruction signal and an input instruction signal, and outputs the comparison instruction signal by the key length of the key length counter. 2. A sort processing device, wherein a plurality of sort processing devices according to claim 1 are connected in series. 3. The sort processing device according to claim 1, wherein a match byte number counter that stores the number of comparison bytes until the contents of the first and second registers do not match with each other by referring to the comparison result of the comparator. Further comprising, the comparator control unit is started by a start instruction signal added from the outside,
Referring to the contents of the result register and the double key flag generation unit, when the double key flag is generated, the dual key flag is given to a predetermined area of the two data stored in the local memory, Either the corresponding data side in the local memory storing the data belonging to the one designated by the result register in the magnitude relation is designated as the next output data, or the dual key flag generation unit generates the dual key flag. When doing the second
The same data stored in the register of the local memory is designated as the next output data, the content of the coincidence byte number counter is stored in a predetermined area of the next output data, and the record length is stored. A sort processing device, which outputs an output instruction signal and an input instruction signal for a record length stored in a unit, and outputs the comparison instruction signal for a key length held by the key length counter. 4. A sort processing device, wherein a plurality of sort processing devices according to claim 3 are connected in series. 5. A key area that is a sort target key, a record area that is not a sort target, a double key detection flag storage area, and a matching byte count storage area in the record that was output immediately before in one input record. It has a control flag area and stores the result of double key detection determined by the sort processing by hardware and the count result of the number of matching bytes in a predetermined area in the record and outputs it to the upper software. 4. The sort according to claim 3, wherein the results are aggregated, grouped, and a double key error is reported without re-comparing the sort key parts by referring to the contents of the area in the record. Processing equipment.