JPH06214685A - Electronic equipment - Google Patents

Abstract

PURPOSE:To provide an electronic equipment capable of preventing the discharge of a battery for holding data by a memory. CONSTITUTION:When the control terminal of a power source disconnection circuit 11 is at a low level, since a transistor 7b is turned OFF, the transistor 7a is turned OFF and the power of a main power source 12 is not supplied through the transistor 7a. In this case, the power of the battery 1 is supplied through a diode 2a to the memory 3 and a CMOSIC 4 and also a PNP type transistor 8 is turned ON. Thus, since a power source line 17 is grounded through the transistor 8, when a peripheral equipment 14 is connected to a connector 13, the power source of the peripheral equipment 14 is turned ON and a signal line 15 is turned to a high level, the current is made flow through the diode 16, the power source line 17 and the transistor 8 to a grounded side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device having a main power supply and a memory for holding data by a battery, and an interface circuit with peripheral devices.

[0002]

2. Description of the Related Art FIG. 3 shows the configuration of a conventional electronic device.
The battery 1 supplies power to the memory 3 and the C via the diode 2a.
The data is supplied to the MOSIC 4, and the memory 3 holds the data by the power from the battery 1 or the main power supply 10. CMOS
The IC 4 is a memory peripheral circuit such as a decoder and a buffer, and is supplied with power from the same power sources 1 and 10 as the memory 3. Both the buffer 5 and the input buffer circuit (interface circuit) 6 are connected to the main power source 10 via the transistor 7. Power is supplied via. The buffer 5 stores the data in CMOSI
The data is output to the memory 3 via C4, and the peripheral device 14 outputs the data to the input buffer circuit 6 via the signal line 15 and the connector 13. The input buffer circuit 6 is a peripheral device 14
The signal line 15 and the power supply line 17 are connected to each other via the input stage protection diode 16 in the input buffer circuit 6.

In such a configuration, the transistor 7
Is turned on and off under the control of the power supply disconnection circuit 17, and when the transistor 7 is on, the power of the main power supply 10 is supplied to the buffer 5 and the input buffer circuit 6 via the transistor 7, and also via the diode 2b. Memory 3 and CM
Supplied to OSIC4. On the other hand, when the transistor 7 is off, the power of the battery 1 is supplied to the memory 3 and the CMOS IC 4 through the diode 2a, and therefore the memory 3 continuously retains the data even when the main power supply 10 is off. can do.

[0004]

However, in the above-mentioned conventional electronic equipment, the power supply line 17 of the input buffer circuit 6 which is an interface circuit with the peripheral equipment 14 varies depending on whether the transistor 7 is turned on or off. Power supply 1
When 0 is off, the peripheral device 14 is connected to the connector 13, the power of the peripheral device 14 is turned on, and the signal line 1
When 5 becomes high level, this current flows into the power supply line 17 via the input stage protection diode 16 in the input buffer circuit 6.

In this case, a CM which is a peripheral circuit of the memory 3
The input of the OSIC 4, that is, the output of the buffer 4 may be an intermediate level voltage that is neither low level nor high level. Due to its characteristics, the CMOSIC4 has a p-channel MOS transistor and an n-channel MO transistor at an intermediate level voltage.
Since both S transistors are turned on at the same time, a large through current flows. Therefore, in the conventional electronic device,
When the main power supply 10 is off and the peripheral device 14 is on, there is a problem that the battery 1 is rapidly discharged.

In view of the above-mentioned conventional problems, it is an object of the present invention to provide an electronic device capable of preventing discharge of a battery for holding data in a memory.

[0007]

In order to achieve the above object, the present invention provides a main power source, a memory for holding data by the main power source and a battery, a power source supplied from the main power source, and peripheral devices. Data is input from the interface circuit, the data line is connected to the main power supply, and an interface circuit for grounding the power supply line between the main power supply and the interface circuit when the main power supply is cut off. It is characterized by having.

[0008]

According to the present invention, when the data line of the peripheral device is turned on while the main power supply is off, this current flows to the ground side through the power supply line.
It is possible to prevent a through current from flowing through the battery, and thus prevent discharge of the battery.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of an electronic device according to the present invention, and the same components as those shown in FIG. 3 are designated by the same reference numerals.

In the electronic device 12 of FIG. 1, the battery 1 supplies electric power to the memory 3 and the CMOS IC 4 via the diode 2a as in the conventional example, and the memory 3 uses the battery 1
Alternatively, the data is held by the power from the main power supply 10. C
The MOSIC 4 is a memory peripheral circuit such as a decoder and a buffer, and is supplied with power from the same power supplies 1 and 10 as the memory 3. Both the buffer 5 and the input buffer circuit 6 are supplied from the main power supply 10 via the PNP transistor 7a. Power is supplied. The buffer 5 outputs the data to the memory 3 via the CMOSIC 4, and the peripheral device 14 outputs the data to the input buffer circuit 6 via the signal line 15 and the connector 13. The input buffer circuit 6 constitutes an interface circuit with the peripheral device 14, and includes a signal line 15 and a power supply line 17.
Is a diode 1 for protecting the input stage in the input buffer circuit 6.
It is connected via 6.

The main power supply 10 is connected to the emitter of the transistor 7a, and the collector of the transistor 7a is PNP.
The transistor 8 is connected to the emitter thereof, and the collector of the transistor 8 is grounded. Transistor 7
Power from the collector of a is supplied to the power supply line 17 and the buffer 5, and is also supplied to the memory 3 via the diode 2b.
And CMOS IC4.

The power supply disconnecting circuit 11 controls the power supply of the main power supply 10 to be turned on and off, and its control terminal is connected to the bases of the NPN type transistor 7b and the transistor 8 via the base resistors 9a and 9b, respectively. Has been done. The collector of the transistor 7b is connected to the base of the transistor 7a via the base resistor 9c, and the emitter is grounded.

Next, the operation of the above embodiment will be described. Figure 1
In the case where the control terminal of the power supply disconnecting circuit 11 is at a high level, the transistor 7b is turned on, so that the transistor 7a is turned on. Therefore, the power of the main power supply 11 is supplied to the memory 3, the CMOSIC 4, the buffer 5, It is supplied to the input buffer circuit 6. In this case, since the PNP transistor 8 is off, the power of the main power supply 11 does not flow to the ground side via the transistor 8.

On the other hand, when the control terminal of the power supply disconnecting circuit 11 is at a low level, the transistor 7b is turned off, so that the transistor 7a is turned off. Therefore, the power of the main power supply 11 is not supplied via the transistor 7a. In this case, the power of the battery 1 is supplied to the memory 3 and the CMOS IC 4 via the diode 2a, and the PNP transistor 8 is turned on. Therefore, since the power supply line 17 is grounded through the transistor 8, the peripheral device 14 is connected to the connector 13 in this state, the power of the peripheral device 14 is turned on, and the signal line 15 becomes high level. This current flows to the ground side via the diode 16, the power supply line 17, and the transistor 8. Therefore, it is possible to prevent a through current from flowing through the CMOSIC 4, and it is possible to prevent the battery 1 from being discharged.

In this embodiment, since the power supply line 17 commonly connected to the internal circuits 3 to 5 is grounded via the transistor 8, the transistor 8 is connected even when a plurality of peripheral devices 14 are connected. Has the effect that only one is required.

Next, a second embodiment will be described with reference to FIG. FIG. 2 is a circuit diagram showing a second embodiment of the electronic apparatus according to the present invention, and the same components as those shown in FIGS. 1 and 3 are designated by the same reference numerals. In the first embodiment, the power supply line 1 commonly connected to the internal circuits 3 to 5 is used.
The power of the main power source 10 is supplied to the input buffer circuit 6 via the power source line 7. In the second embodiment, the power source line 1 is used.
7 and a power supply line 18 which can be separated by a power supply cutoff transistor 19, the power of the main power supply 10 is supplied to the input buffer circuit 6 through the power supply line 17, the transistor 19 and the power supply line 18 in this order. To be done. The power supply cutoff transistor 19 is also used in the conventional configuration and is for cutting off the power supply from the plurality of peripheral devices 14, 14 'to the power supply line 17, and its base is the peripheral device power supply cutoff circuit 20. And the collector is connected to the input buffer circuit 6 of each peripheral device 14, 14 '.
6'is connected.

Furthermore, the emitter of the PNP type transistor 19 is connected to the power supply line 17 commonly connected to the internal circuits 3 to 5, and the collector is connected to the emitter of the transistor 8 and the input buffer via the power supply line 18. It is connected to the power input side of the circuit 6 and the cathode of the diode 16 in the input buffer circuit 6. The other circuit configuration is shown in FIG.
3 and the same as the case shown in FIG. 3, detailed description thereof will be omitted.

In such a configuration, the power supply disconnecting circuit 1
When the control terminal of No. 1 is at high level, the transistor 7b is turned on as in the first embodiment.
a turns on. Therefore, the power of the main power supply 10 is supplied to the memory 3, the CMOSIC 4, the buffer 5, and the input buffer circuit 6 via the transistor 7a. If the transistor 19 is turned on at this time, the power supply line 17,
It is supplied to the input buffer circuit 6 through the transistor 19 and the power supply line 18 in order.

On the other hand, when the control terminal of the power supply disconnecting circuit 11 is at a low level, the transistor 7 is provided as in the first embodiment.
Since b turns off, the transistor 7a turns off, and the PNP transistor 8 turns on, so that the power supply line 18 is grounded via the transistor 8. However, when at least one of the peripheral devices 14 and 14 'is turned on, the transistor 19 is kept on. Therefore, considering that a large-capacity capacitor is normally connected to the power supply line 17, the inrush current at the moment when the transistor 8 is turned on can be reduced, and as a result, the transistor 8 with a small power and current rating can be reduced.
Can be used.

In the above embodiment, the bipolar transistors 7a, 7b, 8 and the like are used as the switching elements, but it goes without saying that switching elements such as relays and FETs can be used instead.

[0021]

As described above, according to the present invention, the main power source, the memory for holding data by the main power source and the battery, the power source supplied from the main power source, and the data input from the peripheral device. Since the data line has an interface circuit connected to the main power supply and grounding means for grounding the power supply line between the main power supply and the interface circuit when the main power supply is cut off, the CMO
It is possible to prevent a through current from flowing through the SIC,
Therefore, discharge of the battery can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an electronic device according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the electronic device according to the present invention.

FIG. 3 is a circuit diagram showing a conventional electronic device.

[Explanation of reference numerals] 1 battery 3 memory 4 CMOSIC 6 input buffer circuit (interface circuit) 7a, 7b, 8 transistors (grounding means) 10 main power supply 14 peripheral device

Claims (1)

[Claims] 1. A main power supply, a memory that holds data by the main power supply and a battery, power is supplied from the main power supply, data is input from a peripheral device, and this data line is connected to the main power supply. And a grounding means for grounding a power supply line between the main power supply and the interface circuit when the main power supply is cut off.