JPH0621440A - Mis-type fet - Google Patents

Abstract

PURPOSE:To prevent a contact resistance for the gate electrode of a metal wiring from increasing by constituting the gate electrode with a film where polycrystalline silicon, tungsten silicide, and titanium silicide are laminated successively. CONSTITUTION:First, a gate insulation film 102 is formed on the surface of a silicon substrate 101 and polycrystalline silicon 103, tungsten silicide 104, and titanium silicide 105 are laminated successively on it. thus forming a three- layer lamination film. Then, the lamination film is subjected to patterning, thus forming a gate electrode consisting of titanium silicide 105a, tungsten silicide 104a, and polycrystalline silicon 103a. Then, a source/drain diffusion layer 106 is formed by implanting an impurity with the gate electrode as a mask. Then, an interlayer insulation film 107 is formed and contact opening 108 is formed thus reducing the contact resistance of a metal wiring for the gate electrode of a manufactured MIS-type FET.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a MIS type FET,
In particular, it relates to the structure of the gate electrode of the MIS type FET.

[0002]

2. Description of the Related Art Referring to FIG. 4 which is a sectional view in order of steps for explaining a method of manufacturing a MIS type FET, a conventional M
The IS type FET is formed as follows. First,
For example, a gate insulating film 202 is formed on the surface of a P-type silicon substrate 201, a laminated film made of polycrystalline silicon and titanium silicide is formed on the entire surface, and then the laminated film is patterned to form polycrystalline silicon 203a and titanium silicide. 205a to form a gate electrode [FIG.
(A)]. Next, an N-type source is formed on the surface of the silicon substrate 201 by ion implantation using this gate electrode as a mask.
The drain diffusion layer 206 is formed, and the interlayer insulating film 20 is formed on the entire surface.
After depositing 7, the contact opening 208 reaching the gate electrode or the like is provided in the interlayer insulating film 207.

As described above, the fact that the gate electrode is formed of a laminated film made of polycrystalline silicon 203a and titanium silicide 205a is one of the lowest specific resistances of titanium silicide compared to other silicides. Because. In the product base, a gate electrode composed of a laminated film of polycrystalline silicon and tungsten silicide or molybdenum silicide, which has a specific resistance about five times higher than that of titanium silicide, is used. With the recent high integration of LSIs, the gate electrode is used. It is also important to reduce the resistance value of, and titanium silicide is starting to be emphasized as a constituent material of the gate electrode.

[0004]

DISCLOSURE OF THE INVENTION The conventional MIS described above
In the gate electrode of the type FET, there is a problem that the contact resistance increases when the metal wiring is connected to the gate electrode through the contact opening 208. The existence of such a problem is a great obstacle to the structure of the operating speed of the MIS type FET. The reason why the contact resistance increases in this way is as follows.

Contact opening 20 reaching titanium silicide 205a by anisotropically etching interlayer insulating film 207
When the metal film for metal wiring is formed after forming No. 8, it is necessary to remove the natural oxide film on the surface of the titanium silicide 205a exposed in the contact opening 208. This natural oxide film is removed with dilute hydrofluoric acid, dilute sulfuric acid, or the like, but this treatment also melts and thins the titanium silicide 205a, increasing the sheet resistance of the titanium silicide 205a. Alternatively, if the titanium silicide 205a is also completely removed by this treatment, the metal wiring will be directly connected to the polycrystalline silicon 203a having a resistivity that is an order of magnitude higher than that of titanium silicide.

[0006]

According to the present invention, a MIS
The gate electrode of the type FET is made of a film in which polycrystalline silicon, tungsten silicide, and titanium silicide are sequentially stacked.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1 which is a cross-sectional view of a MIS type FET, a MIS type FET according to an embodiment of the present invention includes a P type silicon substrate 101 and an N type source provided on the surface of the silicon substrate 101. The drain diffusion layer 106, the gate insulating film 102, the polycrystalline silicon 103a,
A gate electrode provided on a gate insulating film 102 made of a film in which tungsten silicide 104a and titanium silicide 105a are sequentially stacked; an interlayer insulating film 107 covering the silicon substrate 101 including the gate electrode;
The titanium silicide 1 provided on the interlayer insulating film 107
At least a contact opening 108 reaching 05a.

Since the gate electrode has such a structure,
When the natural oxide film on the surface of the titanium silicide 105a is removed with dilute hydrofluoric acid or dilute sulfuric acid as a pretreatment for forming the metal film for the metal wiring, the contact resistance does not increase unlike the conventional case. Titanium silicide 1 by this treatment
Even if 05a is melted to be thin or removed, the underlying tungsten silicide 104a is not melted. The specific resistance of the tungsten silicide 104a is about 5 times the specific resistance of the titanium silicide 105a, but is one digit or more smaller than the specific resistance of polycrystalline silicon. Therefore, a large increase in contact resistance can be avoided. As a result of experimental measurement, in the structure of the above-mentioned one embodiment, the value of the contact resistance was reduced by about 15% as compared with the MIS type FET having the conventional structure.

Referring also to FIG. 2 which is a sectional view in order of steps for explaining the method for manufacturing the MIS-type FET, the method for manufacturing the MIS-type FET having the structure of the first embodiment will be described below. Gate insulating film 1 on the surface of silicon substrate 101 of
02 is formed. Then, the polycrystalline silicon 103 and the tungsten silicide 10 are sequentially formed on the gate insulating film 102.
4, and titanium silicide 105 are formed to form a three-layer laminated film [FIG. 2 (a)]. Next, this laminated film is patterned by anisotropic etching to form a gate electrode made of titanium silicide 105a, tungsten silicide 104a, and polycrystalline silicon 103a. Subsequently, the source / drain diffusion layer 106 is formed by ion implantation of N-type impurities using the gate electrode as a mask [FIG. 2 (b)]. Next, by forming an interlayer insulating film 107 and forming a contact opening 108,
A MIS type FET having the structure shown in FIG. 1 is formed.

Referring also to FIG. 3 which is a cross-sectional view for explaining the method of manufacturing the MIS type FET, another method of manufacturing the MIS type FET having the structure of the first embodiment is the third layer. Instead of forming the titanium silicide 105, a second polycrystalline silicon film is formed, and a three-layer laminated film including the second polycrystalline silicon film is patterned to form a laminated film including the polycrystalline silicon 113a, the tungsten silicide 104a, and the polycrystalline silicon 103a. A pattern is formed, and a sidewall insulating film 1 made of a material different from that of the gate insulating film 102 is formed on the side surface of the laminated pattern.
17 is formed, and the source / drain diffusion layer 106 is formed before and after this. Subsequently, titanium 115 is formed on the entire surface [FIG. 3]. Then, heat treatment in an inert atmosphere,
Titanium silicide is formed by the silicidation reaction between polycrystalline silicon 113a and titanium 115, and the gate electrode having the structure shown in FIG. 1 is formed.

In the above another manufacturing method, when the side wall insulating film 117 is formed of the same material as the gate insulating film 102, titanium silicide is also formed on the surface of the source / drain diffusion layer 106, so that a so-called salicide structure source / drain layer is formed. A drain diffusion layer is obtained.

[0013]

As described above, the MIS type F of the present invention
ET reduces the contact resistance of the metal wiring to the gate electrode. Therefore, the operating speed of the MIS type FET is significantly improved.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining an embodiment of the present invention.

2A to 2D are cross-sectional views in order of the processes, for illustrating the manufacturing method of the one embodiment.

3A to 3D are cross-sectional views in order of the processes, for illustrating another manufacturing method of the one embodiment.

4A to 4C are cross-sectional views in order of processes for explaining a conventional MIS-FET according to a manufacturing method.

[Explanation of symbols]

101, 201 silicon substrate 102, 202 gate insulating film 103, 103a, 113a, 203a polycrystalline silicon 104, 104a tungsten silicide 105, 105a, 205a titanium silicide 106, 206 source / drain diffusion layer 107, 207 interlayer insulating film 108, 208 Contact opening 115 Titanium 117 Side wall insulating film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/338 29/812

Claims (1)

[Claims] 1. A MIS type F formed on a silicon substrate.
A MIS type FET which is an ET and has a gate electrode formed by stacking polycrystalline silicon, tungsten silicide, and titanium silicide.