JPH0621310A - Surface mounted semiconductor device - Google Patents

Surface mounted semiconductor device

Info

Publication number
JPH0621310A
JPH0621310A JP4175377A JP17537792A JPH0621310A JP H0621310 A JPH0621310 A JP H0621310A JP 4175377 A JP4175377 A JP 4175377A JP 17537792 A JP17537792 A JP 17537792A JP H0621310 A JPH0621310 A JP H0621310A
Authority
JP
Japan
Prior art keywords
semiconductor device
soldering
external leads
bent
type semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4175377A
Other languages
Japanese (ja)
Inventor
Tetsuo Yabushita
哲男 薮下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP4175377A priority Critical patent/JPH0621310A/en
Publication of JPH0621310A publication Critical patent/JPH0621310A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a semiconductor device of multipin while moreover being hard to cause a shortcircuit at the time of soldering in a surface mounting type semiconductor device. CONSTITUTION:In this surface mounted semiconductor device consisting of a semiconductor chip where a plurality of electrodes are formed on the surface, the internal leads to be connected by the electrodes and fine wires, the resin sealing these and the external leads connecting to the neighboring external leads 2, 3 inside one side are different in the bending shapes and the parts 7, 8 to be soldered are not piled up in a straight line on the sides.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は表面実装型の半導体装置
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount type semiconductor device.

【0002】[0002]

【従来の技術】従来の表面実装型半導体装置は図5に一
実施例を示すように、外部リード2は全て同一形状で、
ハンダ付け部7は同一直線上に並ぶように成形されてい
た。従って従来の表面実装型半導体装置をハンダ付けす
るときのハンダ付けランド配置は、図6のようにハンダ
付けランド5は一直線上に配置されていた。
2. Description of the Related Art In a conventional surface mount type semiconductor device, as shown in FIG.
The soldering parts 7 were formed so as to be aligned on the same straight line. Therefore, when the conventional surface mount semiconductor device is soldered, the soldering lands 5 are arranged in a straight line as shown in FIG.

【0003】[0003]

【発明が解決しようとする課題】現在、表面実装方式は
非常にポピュラーになっており、それにともなって表面
実装型半導体装置はめざましく数量及び種類が増加して
きている。
At present, the surface mounting method is very popular, and the number and kinds of surface mounting type semiconductor devices are increasing remarkably accordingly.

【0004】電子機器はますます軽薄短小化してきてお
り、それに用いられる回路基板もますます小型化・薄型
化せざるを得なくなってきた。又、一方では電子機器の
高機能化にともない、これらに用いられる半導体装置も
高機能化して、多数の外部出力用の端子が必要となり、
いわゆる多ピン化しつつある。この両方を満足させるた
め多ピン表面実装型半導体装置を使用する事がますます
多くなってきた。
Electronic devices are becoming lighter, thinner, shorter, and smaller, and the circuit boards used therein are also becoming smaller and thinner. On the other hand, along with the sophistication of electronic devices, the semiconductor devices used for these have also become so sophisticated that many terminals for external output are required,
So-called multi-pins are becoming more common. In order to satisfy both of these requirements, it has become more and more popular to use a multi-pin surface mount semiconductor device.

【0005】しかしながら、小型化という制約から半導
体装置の寸法を大きくする事は出来ず、しかし多ピン化
という要求を満足させる技術が必要となり、その結果外
部端子のピッチを小さくし多ピン化する方法が定着して
きた。EIAJでもピッチの規格が制定されており、通
常の表面実装型半導体装置では0.3mmが最小とされて
いる。この時、外部リード幅は推奨値が0.1mmとなっ
ており、リード間スキマは0.2mmしかなく回路基板へ
ハンダ付けする際ショートする危険が増大する欠点があ
った。
However, the size of the semiconductor device cannot be increased due to the restriction of miniaturization, but a technique for satisfying the requirement of increasing the number of pins is required, and as a result, the pitch of the external terminals is reduced to increase the number of pins. Has become established. The EIAJ also establishes the pitch standard, and the normal surface mount semiconductor device has a minimum of 0.3 mm. At this time, the recommended value for the external lead width is 0.1 mm, and the gap between the leads is only 0.2 mm, which has a drawback that the risk of short-circuiting when soldering to the circuit board increases.

【0006】本発明は上記の欠点を解決すべくなされた
もので、ハンダ付けの際ショートする危険性を低減で
き、かつ多ピン化された表面実装型半導体装置を得る事
を目的としたものである。
The present invention has been made to solve the above-mentioned drawbacks, and an object thereof is to obtain a surface mounting type semiconductor device which can reduce the risk of short-circuiting at the time of soldering and which has a large number of pins. is there.

【0007】[0007]

【課題を解決するための手段】本発明の表面実装型半導
体装置を、小さくされたピッチにたいして隣接する外部
リード曲げ形状を変えて、ハンダ付けする部分が辺の一
直線上に重ならない様にする事で回路基板に設置される
ハンダ付けパターンの距離を離す事により達成できる。
In the surface mount type semiconductor device of the present invention, the external lead bending shape adjacent to the reduced pitch is changed so that the soldered portion does not overlap the straight line of the side. Can be achieved by increasing the distance of the soldering pattern installed on the circuit board.

【0008】[0008]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Embodiments of the present invention will now be described with reference to the drawings.

【0009】図1(a)は本発明の斜視図であり、図1
(b)は本発明の断面図である。図1(a),図1
(b)に示すように本実施例はパッケージ本体1から外
部と接続するために外側へ出されガルウイング形に曲げ
られた外部リード2と同じく隣接してガルウイング形に
曲げられた外部リード3の曲げ形状を変更し、回路基板
4に設置されたハンダ付けランド5が一直線上に重なら
ないように配列する事ができる表面実装型半導体装置で
ある。本実施例では外部リード2と外部リード3の第1
曲げ部6を変更し、外部リード2のハンダ付け部7と外
部リード3のハンダ付け部8がパッケージ本体1から同
じ距離にならないようにしている。
FIG. 1A is a perspective view of the present invention.
(B) is sectional drawing of this invention. 1 (a) and 1
As shown in (b), this embodiment is such that the outer lead 2 which is outwardly bent to be connected to the outside from the package body 1 and which is bent in the gull wing shape is bent, and the outer lead 3 which is bent adjacent to the gull wing shape is also bent. It is a surface-mounted semiconductor device in which the shape can be changed and the soldering lands 5 installed on the circuit board 4 can be arranged so as not to overlap in a straight line. In this embodiment, the first of the external leads 2 and 3
The bent portion 6 is changed so that the soldering portion 7 of the external lead 2 and the soldering portion 8 of the external lead 3 are not at the same distance from the package body 1.

【0010】図2は本発明の表面実装型半導体装置を用
いるときのハンダ付けランド配置図で回路基板4に設置
されたハンダ付けランド5は千鳥型に配置され、隣接し
たハンダ付けランド間のショートの危険性を低減でき
る。
FIG. 2 is a layout diagram of soldering lands when the surface mount semiconductor device of the present invention is used. The soldering lands 5 installed on the circuit board 4 are arranged in a staggered pattern, and short-circuiting between adjacent soldering lands is performed. The risk of can be reduced.

【0011】図3は本発明の他の実施例の断面図であ
る。本実施例では外部リード3はJ字形に曲げられてお
り、ハンダ付け部8とハンダ付け部7がパッケージ本体
1から同じ距離にならないようにしてある。
FIG. 3 is a sectional view of another embodiment of the present invention. In this embodiment, the external leads 3 are bent in a J shape so that the soldering portions 8 and 7 are not at the same distance from the package body 1.

【0012】図4は本発明の他の実施例の断面図であ
る。本実施例では外部リード3はI字形に曲げられてい
る。
FIG. 4 is a sectional view of another embodiment of the present invention. In this embodiment, the outer lead 3 is bent into an I shape.

【0013】[0013]

【発明の効果】以上説明したように本発明によれば、隣
接した外部リードの曲げ形状を変えてハンダ付けする部
分の距離を実質的に遠く離す事により、ハンダ付け時の
ショートの危険性を低減させ、さらには表面実装型半導
体の多ピン化を促進させるという効果を有する。
As described above, according to the present invention, the risk of short circuit at the time of soldering is reduced by changing the bending shape of the adjacent external leads to substantially separate the distance between the soldered portions. This has the effect of reducing the number and further promoting the increase in the number of pins of the surface mount semiconductor.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)本発明の一実施例の斜視図である。 (b)本発明の一実施例の断面図である。FIG. 1A is a perspective view of an embodiment of the present invention. (B) It is sectional drawing of one Example of this invention.

【図2】本発明をハンダ付けするときのハンダ付けラン
ド配置図である。
FIG. 2 is a layout diagram of soldering lands when soldering the present invention.

【図3】本発明の他の実施例の断面図である。FIG. 3 is a sectional view of another embodiment of the present invention.

【図4】本発明の他の実施例の断面図である。FIG. 4 is a sectional view of another embodiment of the present invention.

【図5】従来の表面実装型半導体装置の実施例の斜視図
である。
FIG. 5 is a perspective view of an example of a conventional surface mount semiconductor device.

【図6】従来の表面実装型半導体装置をハンダ付けする
ときのハンダ付けランド配置図である。
FIG. 6 is a layout diagram of soldering lands when soldering a conventional surface mount semiconductor device.

【符号の説明】[Explanation of symbols]

1 パッケージ本体 2、3 外部リード 4 回路基板 5 ハンダ付けランド 6 第1曲げ部 7、8 ハンダ付け部 1 Package Body 2, 3 External Leads 4 Circuit Board 5 Soldering Land 6 First Bending Section 7, 8 Soldering Section

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】複数の電極が表面に形成された半導体チッ
プと、前記電極と細線で接続される内部リードと、これ
らを封止する樹脂と、外部と接続する為の外部リードか
らなる表面実装型半導体装置において、一辺内の隣接し
た前記外部リードの曲げ形状が異なり、そのハンダ付け
される部分が辺の一直線上に重ならない事を特徴とした
表面実装型半導体装置。
1. A surface mount comprising a semiconductor chip having a plurality of electrodes formed on its surface, internal leads connected to the electrodes by fine wires, a resin for sealing these, and external leads for connecting to the outside. In the semiconductor device, the surface mounting type semiconductor device is characterized in that the external leads adjacent to each other on one side have different bending shapes, and the soldered portions do not overlap the straight line of the side.
【請求項2】請求項1記載の表面実装型半導体装置にお
いて隣接した外部リードの曲げ形状をガルウイング形と
J字形の組み合わせにした事を特徴とした表面実装型半
導体装置。
2. A surface-mounting type semiconductor device according to claim 1, wherein the bent shape of the adjacent external lead is a combination of a gull wing type and a J-shape.
【請求項3】請求項1記載の表面実装型半導体装置にお
いて隣接した外部リードの曲げ形状をガルウイング形と
I字形の組み合わせにした事を特徴とした表面実装型半
導体装置。
3. A surface-mounting type semiconductor device according to claim 1, wherein adjacent external leads are bent in a combination of gull-wing type and I-type.
JP4175377A 1992-07-02 1992-07-02 Surface mounted semiconductor device Pending JPH0621310A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4175377A JPH0621310A (en) 1992-07-02 1992-07-02 Surface mounted semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4175377A JPH0621310A (en) 1992-07-02 1992-07-02 Surface mounted semiconductor device

Publications (1)

Publication Number Publication Date
JPH0621310A true JPH0621310A (en) 1994-01-28

Family

ID=15995046

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4175377A Pending JPH0621310A (en) 1992-07-02 1992-07-02 Surface mounted semiconductor device

Country Status (1)

Country Link
JP (1) JPH0621310A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001120501A (en) * 1999-10-28 2001-05-08 Olympus Optical Co Ltd Solid image pickup device
US6407446B2 (en) * 1999-12-30 2002-06-18 Samsung Electronics Co., Ltd. Leadframe and semiconductor chip package having cutout portions and increased lead count
WO2003039223A1 (en) * 2001-10-23 2003-05-08 Robert Bosch Gmbh Transistor pin geometries that are suitable for contacting

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001120501A (en) * 1999-10-28 2001-05-08 Olympus Optical Co Ltd Solid image pickup device
US6407446B2 (en) * 1999-12-30 2002-06-18 Samsung Electronics Co., Ltd. Leadframe and semiconductor chip package having cutout portions and increased lead count
WO2003039223A1 (en) * 2001-10-23 2003-05-08 Robert Bosch Gmbh Transistor pin geometries that are suitable for contacting

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