JPH09172129A - Semiconductor device and structure for mounting it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the number of outer leads while suppressing the increase of package area. SOLUTION: On each side plane of a resin-sealed body 3, a plurality of inserting type outer leads 10 and surface mounting type outer leads 20 are alternately arranged. A printed board 30 is composed of multilayers, and a plurality of through holes 40 and lands 50 are arranged in stagger. When the inserting type outer leads 10 are inserted into the through holes 40 and the terminal flat parts 22 of the surface mounting type outer lead 20 are mounted on the land 50, reflow soldering is performed, soldering parts are formed between the inserting type outer lead 10 and the through hole 40 and between the terminal flat part 22 of the surface mounting type outer lead 20 and the land 50, and a semiconductor device 1 is mounted on the printed board 30. Since the number of surface wires on a printed board 30 and a number of through holes 40 can be reduced, the number of outer leads can be increased while suppressing the increase of the package area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting technique of a semiconductor device, and more particularly to the shape and structure of an outer lead, for example, a semiconductor integrated circuit device (hereinafter referred to as an IC) provided with a package having a large number of pins and a narrow pitch. Related to effective technology.

[0002]

2. Description of the Related Art Semiconductor device packages can be classified into insertion type packages and surface mount type packages according to the method of connecting to a wiring board. The insert type package is mounted by being inserted into the through hole of the wiring board. The surface mount type package is mounted by soldering the outer leads to the surface of the wiring board.

Recently, with the demand for higher functionality of ICs, higher integration of packages is rapidly progressing. If the number of outer leads increases with the progress of high integration of the package, the area of the package becomes large. If the area of the package increases, the area occupied by the IC on the wiring board also increases, so it is desirable to keep the area of the package small. As a means for suppressing the increase in the area of the package, a method of narrowing the pitch of the outer leads is generally adopted.

Incidentally, as an example in which the classification according to the mounting form of the package of the semiconductor device is described, "Practical Course VLSI" issued on May 31, 1993 by Nikkei BP Co., Ltd.
Packaging technology (above) "P80 to P84.

[0005]

However, there is a limit to the means for narrowing the pitch of the outer leads and suppressing the increase of the package area in both the surface mounting type package and the insertion type package. That is, when the surface mount type package is mounted on the wiring board, the land to which each outer lead is electrically connected is arranged on the surface of the wiring board body on the mounting side, so that the pitch between adjacent lands is There is a limit to narrowing. On the other hand, when the insertion-type package is mounted on the wiring board, it is necessary to form a plurality of through holes in the wiring board main body side by side, and therefore there is a limit to narrowing the pitch between adjacent through holes. is there.

An object of the present invention is to provide a mounting technique of a semiconductor device which can reduce the pitch of outer leads.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The outline of a typical invention among the inventions disclosed in the present application is as follows. That is, the insertion type outer leads and the surface mount type outer leads are mixed in the outer lead group row.

According to the above-mentioned means, the inner insertion type outer lead group row and the outer surface mounting type outer lead group row are arranged inside and outside the two rows, so that the semiconductor device is inserted in the wiring board. The outer lead group can be relatively narrowed because it is possible to increase the distance between adjacent through-holes into which the outer leads are inserted and the adjacent land between surface-mounted outer leads. be able to.

[0010]

1 is a partially omitted exploded perspective view showing a mounting structure of a semiconductor device according to an embodiment of the present invention. FIG. 2 shows the assembled state, (a) is a plan view and (b) is an enlarged partial front sectional view.

In this embodiment, the semiconductor device mounting structure comprises a semiconductor device and a printed wiring board, and the semiconductor device 1 comprises a resin-sealed package 2. The resin-sealed package 2 is made of a resin having an insulating property, and a plurality of outer leads are projected from the side surface of the resin-sealed body 3 integrally molded by a transfer molding device. The resin encapsulation body 3 is formed in a flat plate shape having a substantially square plane, and the outer leads are provided so as to be arranged in a row in a row on each side surface in four directions. Although not shown, a semiconductor pellet in which an integrated circuit including each inner lead integrally connected to each outer lead and a semiconductor element is formed is resin-sealed inside the resin sealing body 3, and the semiconductor pellet is also formed. Each electrode pad and each inner lead are electrically connected to each other. Therefore, the integrated circuit including the semiconductor element of the semiconductor pellet is electrically drawn to each outer lead via each inner lead.

A plurality of insertion type outer leads 10 and surface mounting type outer leads 20 are mixed in the outer lead group arranged in a line on each side surface of the resin encapsulation body 3, and the insertion type outer leads 10 and the surface mounting type. The outer leads 20 are arranged alternately. Insert type outer lead 1
The insertion type outer lead group row 11 is configured by group 0,
The surface mount type outer lead group 20 constitutes a surface mount type outer lead group 21. Row interval 1 between a pair of insertion-type outer lead group 11, 11 facing each other
2 is set to be smaller than the row interval between the pair of surface-mounting outer lead group rows 21, 21 facing each other, and the square formed by the four inserting-type outer lead group rows 11 and the four surface-mounting type outer lead group rows 21. The outer lead group row 21 and the square formed by the outer lead group row 21 are concentric with each other and concentric with the resin sealing body 3. That is, each insertion-type outer lead group row 11 corresponds to each surface-mounting-type outer lead group row 21.
It is configured to come to the inside of the resin sealing body 3 in the radial direction.

The terminal width 13 which is the width of the tip end portion of the insertion type outer lead 10 is set to be equal to the maximum terminal width which is the width of the base end portion. That is, the insertion-type outer lead 10 is formed so that the width thereof is constant over the entire length thereof, and the seating plane in the usual insertion-type outer lead is not formed. The reason why the seating plane is not formed is that, as will be described later, the seating plane of the resin-sealed package 2 according to the present embodiment needs to be configured to be defined by the seating plane of the surface mount outer lead 20. Because there is. The terminal angle of the insertion type outer lead 10 is the insertion type outer lead group row 1
1 is set as small as possible so as to be closer to the inner side in the radial direction.

Each of the surface mount type outer leads 20 is bent and formed in a gull wing shape, and the sheeting plane 4 as the resin-sealed package 2 is formed by the plane formed by the terminal flat portions 22 of the surface mount type outer lead 20.
Is configured. Incidentally, an appropriate standoff height 5 is set between the seating plane 4 and the lower end surface of the resin sealing body 3. The terminal width 23 of each surface mount type outer lead 20 is set to be equal over the entire length, and the terminal width 13 of the insertion type outer lead 10 is set.
Is set equal to Surface mount outer lead 20
The total width 24, which is the distance from the tip of the outer lead 20 on the opposite side to the tip of the surface mount outer lead 20, is
Is set to be sufficiently larger than the column interval 12 which is the entire width of the terminal flat portion 22, and the length 25 of the terminal flat portion 22 is set so that the inner end side of the terminal flat portion 22 is located outside the insertion type outer lead 10. There is.

Since the insert type outer leads 10 and the surface mount type outer leads 20 are alternately arranged,
The pitch 16 which is the interval between the adjacent insertion type outer leads 10 and 10 in the insertion type outer lead group row 11 and the pitch 2 which is the interval between the adjacent surface mounting type outer leads 20 and 20 in the surface mount type outer lead group row 21.
6 is twice the pitch 6 between the insertion type outer lead 10 and the surface mounting type outer lead 20 which are adjacent to each other.

The printed wiring board 30 has a multi-layered wiring structure and includes a main body 31 formed in a flat plate shape using an insulating material. First of the main body 31
Insert type outer lead 1 on the main surface (hereinafter referred to as the upper surface)
A plurality of through holes 40 electrically connected to 0 and a plurality of lands 50 electrically connected to the surface mount type outer leads 20 are mixed, and the through holes 40 and the lands 50 are arranged in a staggered pattern. There is. Through hole 4
The through hole group row 41 is constituted by the 0 group, and the land group row 51 is constituted by the land 50 group. The pair of through hole group rows 41 facing each other, and the row spacing 42 between the 41 rows are the pair of land group rows 51, 5 facing each other.
The square formed by the four through-hole group rows 41 and the square formed by the four land group rows 51 are concentric with each other and are smaller than the row spacing 52 of one insert, and the insertion-type outer lead The group rows 11 and the surface mount type outer lead group rows 21 are configured to correspond respectively. That is, each through hole group row 41 is arranged to be radially inward of each land group row 51.

The through hole 40 is provided with through holes 43 each having a substantially rectangular cross-sectional shape which is substantially the same as the cross-sectional shape of the insertable outer lead 10. Each through hole 43 is arranged so as to correspond to each insertable outer lead 10. Has been established. Through hole conductors 44 are integrally attached to the side wall surface of the through hole 43 of the through hole 40 and the upper and lower opening edge portions.
A plurality of through-hole electrical wires 45 are formed on the lower surface and inside of the main body 31 of the printed wiring board 30 having a multilayer wiring structure. Each through-hole conductor 4 has an insulating gap appropriately set inside.
4 are electrically connected to each other.

The land 50 is a surface mount type outer lead 20.
Is formed in a rectangular flat plate shape that is slightly larger than the terminal flat portion 22, and the sheeting plane on the printed wiring board 30 side is formed by the plane formed by the upper surface group. Each land 50 is arranged and formed so as to correspond to each surface mount outer lead 20. The total width 54, which is the distance from the outer end of the land 50 to the outer end of the land 50 on the opposite side, is set to be sufficiently larger than the row interval 52 that is the total width of the through holes 40, and the length 55 of the land 50. Is set so that the inner edge of the land secures an appropriate insulating gap in the through-hole conductor 44.

Since the through holes 40 and the lands 50 are arranged in a zigzag pattern, the through hole group row 41 is formed.
The pitch 46, which is the distance between the adjacent through holes 40 and 40, and the pitch 56, which is the distance between the adjacent lands 50 and 50 in the land group row 51, are twice the distance 36 between the through holes 40 and the lands 50. Has become. Therefore, the pitch 58, which is the interval between adjacent ones of the land electrical wirings (hereinafter referred to as surface wirings) 57 connected to the respective lands 50 on the upper surface of the main body 31 of the printed wiring board 30, is defined by the through holes 40 and the lands 50. It is twice the pitch 36 with.

The semiconductor device 1 having the resin-sealed package 2 having the above-mentioned structure is mounted on the printed wiring board 30 having the above structure as shown in FIG. 2 to form a mounting structure. Has been done. Next, the mounting work will be described.

Before the semiconductor device 1 is mounted on the printed wiring board 30, each through hole 40 and each land 50 of the printed wiring board 30 is subjected to preliminary soldering such as application of solder paste. When mounting the semiconductor device 1 on the printed wiring board 30, the insertion type outer leads 10 of the resin-sealed package 2 are inserted into the through holes 40 of the printed wiring board 30, respectively, and the terminal flat portions 22 of the surface mounting type outer leads 20 are inserted. Are placed on each land 50. At this time, since the seating plane is not formed on the insertion-type outer lead 10, the terminal flat portion 22 of each surface-mount-type outer lead 20 is connected to each land 5.
The entire surface of the printed wiring board 30 is evenly contacted with 0.

Thereafter, the printed wiring board 30 on which the semiconductor device 1 is assembled is subjected to a reflow soldering process such as passing through a heating furnace. By this reflow soldering process, the terminal flat portion 2 between the insertion type outer lead 10 and the through hole 40 and the surface mounting type outer lead 20.
Since a soldering portion (not shown) is formed between the two and the land 50 by preliminary soldering, the semiconductor device 1 is in a state of being electrically and mechanically connected to the printed wiring board 30.

In the mounting structure 60 in which the semiconductor device 1 is mounted on the printed wiring board 30 as described above,
Since the pitch 58 between adjacent surface wirings 57, 57 arranged on the surface of the main body 31 of the printed wiring board 30 is twice the pitch 36 between the through holes 40 and the lands 50, a sufficient electrical insulation gap is provided. It has been secured in. In other words, the surface wiring 57, the pitch 58 of the 57
Can be reduced to the minimum value that can secure the insulation gap between the adjacent surface wirings 57, 57, and therefore the pitch 3 between the through hole 40 and the land 50 can be reduced.
6 can be narrowed. That is, the pitch 6 between the insertion type outer lead 10 and the surface mounting type outer lead 20 which is limited to the pitch 36 between the through hole 40 and the land 50.
Can be narrowed without being restricted by the pitch 58 of the surface wirings 57, 57. Therefore, the insertion-type outer leads 10 which are alternately arranged on one side surface of the resin sealing body 3.
Since the surface-mounted outer leads 20 can be arranged closely spaced, the arrangement density can be increased. This means that the number of outer leads can be increased while suppressing an increase in the area of the package.

On the other hand, since the through-hole electrical wiring 45 can be distributed and provided inside and on the lower surface of the main body 31 of the printed wiring board 30, the insulating gap between the adjacent through-hole electrical wirings 45, 45 is easy. Can be largely secured. That is, adjacent through holes 4
Since the pitch 46 between 0 and 40 depends on the pitch 16 between the adjacent insertion-type outer leads 10 and 10, the insertion-type outer leads 10 and the surface-mount-type outer leads that are alternately arranged on one side surface of the resin sealing body 3. By arranging 20 at intervals, the arrangement density can be increased. This means that the number of outer leads can be increased while suppressing an increase in the area of the package.

According to the above embodiment, the following effects can be obtained. (1) Compared with a conventional surface mount type package in which only surface mount type outer leads are arranged by alternately arranging insertion type outer leads and surface mount type outer leads in one outer lead group row of the package Because the number of surface wiring of can be reduced,
The number of outer leads can be increased while suppressing an increase in the area of the package.

(2) By arranging the insert type outer leads and the surface mount type outer leads alternately in one outer lead group row of the package, compared with the conventional insert type package in which only the insert type outer leads are arranged, a through hole is formed. Since it is possible to reduce the number of wires, it is possible to increase the wirable area on the lower surface and inside of the printed wiring board, and it is possible to increase the number of outer leads while suppressing an increase in the area of the package.

(3) According to (1) and (2) above,
Since the wiring density in the printed wiring board can be increased, the number of layers in the printed wiring board having a multilayer structure can be reduced, and the manufacturing cost of the printed wiring board can be reduced.

FIG. 3A is a partially omitted exploded perspective view showing a semiconductor device according to a second embodiment of the present invention, and FIG. 3B is an enlarged partial front sectional view showing a mounting structure thereof.

The second embodiment is different from the first embodiment in that the insertion type outer lead 10 and the surface mounting type outer lead 20 are arranged at the same position so as to be overlapped with each other.

In the second embodiment, since the insertion-type outer lead 10 and the surface-mounting-type outer lead 20 are arranged at the same position so as to overlap each other, the number of outer leads is doubled. However, in the second embodiment, the insertion-type outer lead 10 and the surface-mounting-type outer lead 20 that are overlapped at the same position are electrically equal to each other, so that the insertion-type outer lead 10 and the surface-mounting-type outer lead 20 have the same electrical signal. It will be used for special purposes such as handling.

FIG. 4A is a partially omitted exploded perspective view showing a semiconductor device according to a third embodiment of the present invention, and FIG. 4B is an enlarged partial front sectional view showing a mounting structure thereof.

The third embodiment is different from the first embodiment in that the insertion type outer lead 10 and the surface mounting type outer lead 20 are arranged at the same position, and the insertion type outer lead 10 and the surface mounting type outer lead 20 are stacked. The point is that the insulating layer 27 is interposed between the overlapping surfaces of and.

In the second embodiment, since the insertion type outer lead 10 and the surface mounting type outer lead 20 are arranged at the same position, the number of outer leads is doubled. Moreover, in the third embodiment, the insertion-type outer lead 10 and the surface-mounting-type outer lead 20 that overlap at the same position are electrically independent by the insulating layer 27. Therefore, the insertion-type outer lead 10 and the surface-mounting-type outer lead 20 are separated. It is possible to handle separate electrical signals from.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the size and shape of the resin encapsulant, the number of the insertion type outer leads and the number of the surface mounting type outer leads, etc. are not limited, and can be appropriately selected depending on the application and use conditions.

The sealing body is not limited to the resin sealing body,
You may comprise in an airtight sealed body.

In the above description, the case where the invention made by the present inventor is mainly applied to an IC which is a field of application which is the background of the invention has been described. It can be applied to all semiconductor devices. In particular, the present invention can be applied to a small package having a large number of outer leads to obtain excellent effects.

[0038]

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

By mixing the insertion type outer leads and the surface mounting type outer leads in one outer lead group row of the package, it is possible to increase the number of outer leads while suppressing an increase in the area of the package, and at the same time in the printed wiring board. The wiring density can be increased.

[Brief description of the drawings]

FIG. 1 is a partially omitted exploded perspective view showing a mounting structure of a semiconductor device according to an embodiment of the present invention.

2A and 2B show the assembled state, FIG. 2A is a plan view, and FIG. 2B is an enlarged partial front sectional view.

FIG. 3A is a partially omitted exploded perspective view showing a semiconductor device according to a second embodiment of the present invention, and FIG. 3B is an enlarged partial front sectional view showing a mounting structure thereof.

FIG. 4A is a partially omitted exploded perspective view showing a semiconductor device according to a third embodiment of the present invention, and FIG. 4B is an enlarged partial front sectional view showing a mounting structure thereof.

[Explanation of symbols]

1 ... Semiconductor device, 2 ... Resin-sealed package (package), 3 ... Resin-sealed body, 4 ... Sheeting plane,
5 ... Standoff height, 6 ... Pitch between insert type outer lead and surface mount type outer lead, 10 ... Insert type outer lead, 11 ... Insert type outer lead group row, 12 ... Insert type outer lead group row spacing, 13 ... Insert type Outer lead terminal width, 16 ... Insertion type outer lead pitch, 20 ... Surface mount type outer lead, 21 ... Surface mount type outer lead group row, 22 ... Terminal flat part, 23 ... Surface mount type outer lead terminal width, 24 ... Surface mount type Outer lead full width, 2
5 ... Length of flat portion of terminal of insert type outer lead, 26 ... Pitch of insert type outer lead, 27 ... Insulating layer, 30 ... Printed wiring board, 31 ... Main body, 36 ... Pitch between through hole and land, 40 ... Through hole , 41 ... Through hole group row, 42 ... Through hole group row row spacing, 43 ... Through hole, 44 ... Through hole conductor, 45 ... Through hole electrical wiring, 46 ... Through hole pitch, 50 ... Land,
51 ... Land group row, 52 ... Land group row spacing, 54 ...
Total width of land, 55 ... Land length, 56 ... Land pitch, 57 ... Land electrical wiring (surface wiring), 58 ... Surface wiring pitch, 60 ... Mounting structure.

Claims (5)

[Claims] 1. A semiconductor device having a plurality of outer leads arranged in a line on a side surface of a sealing body so as to project, wherein an insertion-type outer lead and a surface-mounting-type outer lead are mixed in the outer lead group row. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the insertion type outer leads and the surface mounting type outer leads are arranged alternately. 3. The semiconductor device according to claim 1, wherein the insertion-type outer lead and the surface-mounting-type outer lead are arranged so as to overlap each other at the same position. 4. The semiconductor device according to claim 3, wherein an insulating layer is interposed between the insertion type outer lead and the surface mounting type outer lead. 5. The mounting structure in which the semiconductor device according to claim 1 is mounted on a wiring board, wherein a plurality of through holes are formed in one main surface of the main body of the wiring board in each of the insertion-type outer leads. A plurality of lands are arranged correspondingly to each other and opened in the thickness direction, and a plurality of lands are arranged on the main surface of the main body of the wiring board so as to correspond to the respective surface mount outer leads. Shaped outer leads are inserted into the through holes, and the surface-mounted outer leads are electrically connected to each other while being in contact with each land.