JPH0621069A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a decrease of a cut-off frequency without varying a base transit distance even when a transistor becomes a high current operating state and a collector current is concentrated at a periphery of an emitter by forming a base region and a low concentration collector region shallow on the periphery of the emitter region. CONSTITUTION:The semiconductor device comprises a first conductivity type first region 4 provided in a semiconductor substrate 9, a second region 3 having a second conductivity type provided in the region 4, and a first conductivity type third region 2 provided in the region 3. The region 3 is formed thinly at a part which is not brought into contact with the region 2 as compared with the part in contact with the region 2, and a distant part from the region 2 of the region 4 is formed thinly as compared with a part near the region 2. For example, connecting surfaces of the region 3 to the region 4 and the region 4 to a high concentration collector region 8 are not flat, and depths of the regions 3, 4 are shallow at parts except a part directly under the emitter 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a bipolar transistor suitable for high speed operation.

[0002]

2. Description of the Related Art An example of the structure of a conventional bipolar transistor is shown in FIG. In FIG. 2, reference numeral 10 is an n-type polycrystalline silicon film, 11 is an n-type emitter region, 12 is a p-type base region, 13 is an n-type low-concentration collector region, 14 is a silicon oxide film, and 15 is a p-type polycrystalline silicon film. , 16 is a silicon oxide film, 17 is an n-type high concentration collector region, and 18 is a p-type silicon substrate.

In the conventional bipolar transistor having the above structure, the junction surface of the p-type base region 12, the n-type low-concentration collector region 13 and the n-type low-concentration collector region 13 and the high-concentration collector region 17 is flat, and n Compared to the p-type base region 12 immediately below the type emitter region 11, the p-type base region 12 other than immediately below the emitter region 11 was thicker. A bipolar transistor having such a structure is, for example, IEE transaction on electron devices 34D. Number 11 (198
7) 2246 to 2254 (IEEE, Tran
s. Electron Dev, ED-34, No11 (1987) pp22
46-2254).

[0004]

In the above prior art, since the peripheral portion of the emitter region 11 has a curved surface, the thickness of the base region 12 and the low-concentration collector region 13 is lower than that of the peripheral portion of the emitter. It is thicker than just below the center of the emitter. Therefore, the carriers passing through the periphery of the emitter and flowing to the collector have longer travel distances in the base and the low-concentration collector region as compared with the carriers passing through the center of the emitter and flowing to the collector. An increase in the travel distance of carriers causes a decrease in the cutoff frequency of the transistor.
When the transistor is operated at a high current density, the current concentrates on the peripheral portion of the emitter, which reduces the transistor operation speed.

An object of the present invention is to solve the above-mentioned conventional problems and provide a bipolar transistor which can operate at high speed.

[0006]

In order to achieve the above object, the present invention forms a shallow base region and low concentration collector region in the periphery of the emitter region.

[0007]

FIG. 1 shows an example of the present invention. In FIG. 1, 1 is an n-type polycrystalline silicon film, 2 is an n-type emitter region, and 3 is p.
Type base region, 4 a low concentration n type collector region, 5 a silicon oxide film, 6 a p type polycrystalline silicon film, 7 a silicon oxide film, 8 an n type high concentration collector region, and 9 a p type silicon substrate. , Respectively. As is clear from FIG.
The junction surfaces of the base region 3 and the low concentration collector region 4 and between the low concentration collector region 4 and the high concentration collector region 8 are not flat, and the depths of the base region 3 and the low concentration collector region 4 are shallow except for the portion directly below the emitter. did. Therefore, even when the transistor is in a high current operating state and the collector current is concentrated in the peripheral portion of the emitter region 2, the base travel distance does not change. As a result, the reduction of the cutoff frequency in the high current operation state is reduced.

[0008]

Embodiments FIGS. 3 to 6 are process drawings showing a first embodiment of the present invention. First, as shown in FIG. 3, a high-concentration n-type region 8 is diffused on the surface of a p-type silicon substrate 9 at 1200 ° C. for 45 minutes, or ion implantation of arsenic or antimony is performed, and then in a nitrogen atmosphere. It is formed by annealing, and the low-concentration epitaxial layer 4 is formed by a well-known epitaxial growth method.
A silicon oxide film 19 is formed on the surface of the epitaxial layer by a dry oxidation method at 1000 ° C. for 40 minutes, and S
Silicon nitride film 20 is formed by a mixed gas of iH ₄ and NH _3.
Then, the silicon oxide film 21 is deposited by subjecting SiH ₄ and O ₂ to high temperature treatment.

Then, unnecessary portions of the silicon oxide film 19, the silicon nitride film 20, and the silicon oxide film 21 are removed by using an anisotropic dry etching method. After depositing a silicon nitride film on the entire surface, anisotropic dry etching is performed to remove the silicon nitride film on the plane portion, and on the sidewalls of the silicon oxide film 19, silicon nitride film 20, and silicon oxide film 21. The silicon nitride film 22 is left. Then, the epitaxial layer 4 is removed by anisotropic dry etching to form a convex portion. Next, a silicon nitride film is deposited on the entire surface and anisotropic dry etching is performed to remove the silicon nitride film on the flat surface portion, leaving the silicon nitride film 23 on the sidewall of the convex portion.

Subsequently, as shown in FIG. 4, the exposed surface of the collector layer 8 is oxidized by a high pressure oxidation method at 7 atmospheres, 1000 ° C. for 15 minutes to form a silicon oxide film 7, and then 16
The silicon nitride film 22 and the silicon nitride film 23 are removed by hot phosphoric acid at 0 ° C. An n-type impurity is injected by the ion implantation method to increase the concentration of the peripheral portion of the low concentration epitaxial region 4.

Next, as shown in FIG. 5, a polycrystalline silicon film 6 is formed.
Is deposited on the entire surface, boron is introduced into the polycrystalline silicon film 6 by an ion implantation method to make it p-type. After removing the polycrystalline silicon film 6 on the convex portion, the polycrystalline silicon film 6 is formed. The silicon oxide film 24 is formed by oxidation. The silicon oxide film 19, the silicon nitride film 20, and the silicon oxide film 21 are removed to expose the surface of the low concentration epitaxial layer 4. The p-type base region 3 is shallowly formed on the surface of the low-concentration epitaxial layer 4 by ion implantation of boron. At this time, the depth of the base region 3 is made shallower than the depth of the emitter region described later.

Next, as shown in FIG. 6, a silicon oxide film 5 is formed.
Are deposited on the entire surface. Using anisotropic dry etching,
After forming an opening in the silicon oxide film 5, using the silicon oxide film 5 as a mask, only the central portion of the surface of the epitaxial layer 4 is ion-implanted with boron at a higher energy than the above-mentioned boron implantation, followed by thermal diffusion. Is performed to form the p-type base region 3 in which the central portion of the convex portion is deeply formed. Then, as shown in FIG. 1, an n-type polycrystalline silicon film doped with arsenic or phosphorus is deposited. Then, heat treatment is performed to form the high concentration n-type emitter region 2.

In this embodiment, the depth of the base region and the low concentration collector region is not uniform, and the portion other than below the emitter region is shallow. Even if you concentrate on the periphery,
Since the base transit time of the carrier is not increased, the deterioration of the cutoff frequency in the high current operation state is improved by 20% compared with the conventional case.

7 to 10 are process diagrams showing the second embodiment. First, as shown in FIG. 7, a high concentration collector region 26 is formed on the surface of the p-type silicon substrate 25 at 1200 ° C. 45.
Minute antimony diffusion, or arsenic or antimony ion implantation, and subsequent annealing in a nitrogen atmosphere, and a low-concentration epitaxial layer 27 is formed by a well-known epitaxial growth method. On the surface of the epitaxial layer, 1000 ° C., 40
A silicon oxide film 30 is formed by a dry oxidation method for a minute, and a silicon nitride film 31 is deposited by a mixed gas of SiH ₄ and NH ₃ . Next, unnecessary portions of the silicon oxide film 30, the silicon nitride film 31, and the low-concentration epitaxial layer 27 are removed by using an anisotropic dry etching method to form convex portions. Then, the exposed surface of the high-concentration collector layer 26 is exposed to a pressure of 7 atm.
Oxidation is performed by a high pressure oxidation method for 5 minutes to form a silicon oxide film 29. Next, a resist film 32 is formed in the center of the convex portion of the low-concentration epitaxial layer, and arsenic or antimony ion implantation and subsequent annealing are performed to increase the concentration of only the peripheral portion of the convex portion of the low-concentration epitaxial layer. Next, the p-type base region 28 is shallowly formed on the surface of the low-concentration epitaxial layer 27 by ion implantation of boron.

As shown in FIG. 8, a polycrystalline silicon film 33 is deposited on the entire surface, and boron is introduced into the polycrystalline silicon film 33 by an ion implantation method to make it p-type. Then, anisotropic dry etching is used to form an opening in the polycrystalline silicon film 33, followed by oxidation to form a silicon oxide film 34.

As shown in FIG. 9, the silicon nitride film 31 and the silicon oxide film 30 are removed by the wet etching method. Next, using the silicon oxide film 34 as a mask, boron ions are implanted only in the central portion of the surface of the epitaxial layer 27 at a higher energy than the ion implantation performed in FIG. A deeply formed p-type base region 28 is formed.

As shown in FIG. 10, n-type polycrystalline silicon 35 is deposited in the opening of oxide film 34. Then, heat treatment is performed to form the n-type emitter region 36.

The present embodiment is an example of a semiconductor device in which the base resistance is reduced as compared with the first embodiment, and the increase of the base traveling distance of carriers in the peripheral portion of the emitter is prevented.

11 to 14 are process diagrams showing a third embodiment. First, as shown in FIG. 11, a high-concentration n-type region 38 is formed on the surface of a p-type silicon substrate 37 by antimony diffusion at 1200 ° C. for 45 minutes, or ion implantation of arsenic or antimony, and subsequent annealing in a nitrogen atmosphere. Formed, further low concentration epitaxial layer 39
Are formed by a well-known epitaxial growth method. A silicon oxide film 40 is formed on the surface of the epitaxial layer by a dry oxidation method, and a silicon nitride film 41 is deposited by a mixed gas of SiH ₄ and NH ₃ .

Next, as shown in FIG. 12, unnecessary portions of the silicon nitride film 41, the silicon oxide film 40 and the low concentration epitaxial layer 39 are removed by a dry etching method, and then high pressure oxidation at 1000 ° C. is performed. 42 is formed.

As shown in FIG. 13, the silicon nitride film 41 is removed by hot phosphoric acid at 160 ° C. Next, ion implantation of arsenic or antimony and subsequent annealing are performed to increase the concentration of only the low-concentration epitaxial layer around the convex portion. Then, a p-type base region 44 is formed on the surface of the epitaxial layer 39 by boron ion implantation or BN diffusion method. PSG film 43 as C
After deposition by the VD method, an opening is formed in the PSG film by using anisotropic dry etching.

As shown in FIG. 14, using the PSG film 43 as a mask, ions are implanted into the epitaxial layer 39 below the opening, and then thermal diffusion is carried out to deeply form the p-type base region 44 just below the opening. To form. Ion implantation of arsenic or phosphorus is performed and heat treatment is performed to form a high concentration n-type emitter region 45. An opening is provided in the PSG film using anisotropic dry etching. After depositing aluminum on the entire surface, unnecessary portions are removed and the emitter electrode 46 and the base electrode 47 are formed.

In this embodiment, the formation of the base region and the low concentration collector region of a well-known isoplanar bipolar transistor is formed by using the formation method described in the first embodiment, and carriers travel around the emitter. Prevented increase in distance.

15 to 17 are process diagrams showing the fourth embodiment. The same steps as in Example 1 are performed to expose the epitaxial layer on the convex portion. Then, as shown in FIG. 15, boron ion implantation is performed on the surface of the low-concentration epitaxial layer. Next, after forming a resist film 53 in the central portion of the convex portion, p-type base region 51 is formed by performing ion implantation of boron in the peripheral portion of the convex portion with higher energy than the ion implantation described above. At this time, the depth of the base region 51 at the central portion of the protrusion is formed to be shallower than that of the emitter region described later.

Next, as shown in FIG. 16, a polycrystalline silicon film 54 is deposited on the entire surface, and arsenic or phosphorus is introduced into the polycrystalline silicon film 54 by the ion implantation method to make it n-type. Further, a polycrystalline silicon film 54 having an opening and a silicon oxide film 55 are formed by the same process as in the second embodiment. Next, ion implantation of arsenic or antimony and subsequent annealing are performed to increase the concentration of only the low concentration epitaxial layer in the central portion of the convex portion. At this time, the emitter region 56 is formed.

As shown in FIG. 17, the silicon oxide film 5 is formed.
A polycrystalline silicon film 58 is deposited in the opening 5 and boron is introduced into the polycrystalline silicon film 58 to make it p-type. Then, the graft base region 57 is formed by annealing at 900 ° C.

This embodiment is an example of a semiconductor device in which an increase in carrier travel distance in the peripheral portion of the emitter is prevented in a transistor having a double emitter structure, and the base resistance and the emitter resistance are reduced as compared with the first embodiment. .

[0028]

As described above, according to the present invention,
Even when the collector current of the transistor is concentrated on the periphery of the emitter, it is possible to effectively prevent an increase in the traveling distance of carriers in the base and the low concentration collector, so that the cutoff frequency is reduced and the operating speed is improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device showing a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a conventional bipolar transistor.

FIG. 3 is a cross-sectional view showing a process for explaining the first embodiment.

FIG. 4 is a cross-sectional view showing a process for explaining the first embodiment.

FIG. 5 is a cross-sectional view showing a process for explaining the first embodiment.

FIG. 6 is a cross-sectional view showing a process for explaining the first embodiment.

FIG. 7 is a cross-sectional view showing a step for explaining the second embodiment.

FIG. 8 is a cross-sectional view showing a step for explaining the second embodiment.

FIG. 9 is a sectional view showing a process for explaining the second embodiment.

FIG. 10 is a sectional view showing a process for explaining the second embodiment.

FIG. 11 is a sectional view showing a process for explaining the third embodiment.

FIG. 12 is a cross-sectional view showing a process for explaining a third embodiment.

FIG. 13 is a sectional view showing a process for explaining the third embodiment.

FIG. 14 is a sectional view showing a process for explaining the third embodiment.

FIG. 15 is a sectional view showing a process for explaining the fourth embodiment.

FIG. 16 is a sectional view showing a process for explaining the fourth embodiment.

FIG. 17 is a sectional view showing a process for explaining the fourth embodiment.

[Explanation of symbols]

1 ... Polycrystalline silicon film, 2 ... Emitter region, 3 ... Base region, 4 ... Low concentration collector region, 5 ... Silicon oxide film,
6 ... Polycrystalline silicon film, 7 ... Silicon oxide film, 8 ... High concentration collector region, 9 ... Silicon substrate, 10 ... Polycrystalline silicon film, 11 ... Emitter region, 12 ... Base region, 13
... low concentration collector region, 14 ... silicon oxide film, 15 ...
Polycrystalline silicon film, 16 ... Silicon oxide film, 17 ... High concentration collector region, 18 ... Silicon substrate, 19 ... Silicon oxide film, 20 ... Silicon nitride film, 21 ... Silicon oxide film, 22 ... Silicon nitride film, 23 ... Silicon Nitride film, 2
4 ... Silicon oxide film, 25 ... Silicon substrate, 26 ... High concentration collector region, 27 ... Low concentration epitaxial region, 2
8 ... Base region, 29 ... Silicon oxide film, 30 ... Silicon oxide film, 31 ... Silicon nitride film, 32 ... Resist film,
33 ... Polycrystalline silicon film, 34 ... Silicon oxide film, 35
... polycrystal silicon film, 36 ... emitter region, 37 ... silicon substrate, 38 ... high concentration collector region, 39 ... low concentration epitaxial region, 40 ... silicon oxide film, 41 ... silicon nitride film, 42 ... silicon oxide film, 43 ... PSG film,
44 ... Base region, 45 ... Emitter region, 46 ... Aluminum electrode, 47 ... Aluminum electrode, 48 ... Silicon substrate, 49 ...
High concentration collector region, 50 ... Low concentration epitaxial region, 51 ... Base region, 52 ... Silicon oxide film, 53 ...
Resist film, 54 ... Polycrystalline silicon film, 55 ... Silicon oxide film, 56 ... Emitter region, 57 ... Graft base region, 58 ... Polycrystalline silicon film.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshihiro Onouchi 1-280, Higashi Koigokubo, Kokubunji City, Tokyo Inside Central Research Laboratory, Hitachi, Ltd.

Claims (5)

[Claims] 1. A first region of a first conductivity type provided in a semiconductor substrate, a second region of a second conductivity type provided in the first region, and the first region provided in the second region. The second region has a third region of one conductivity type, and the second region is formed such that a portion not in contact with the third region is thinner than a portion in contact with the third region, and is further away from the third region in the first region. A semiconductor device, wherein a portion is formed thinner than a portion near the third region. 2. The semiconductor device according to claim 1, wherein the first region, the second region and the third region are a collector, a base and an emitter of a bipolar transistor, respectively. 3. The semiconductor device according to claim 1, wherein the distances between the thinned portions of the second region and the third region and the first region are substantially uniform. 4. The semiconductor device according to claim 1, wherein the first conductivity type and the second conductivity type are p type and n type, respectively. 5. The semiconductor device according to claim 1, wherein the first conductivity type and the second conductivity type are n type and p type, respectively.