JPH06208543A - Bus arbitrating method of multi-cpu system - Google Patents

Abstract

PURPOSE:To apply this method even to a real-time system by supplying an interruption signal of different level to another CPU in order by a CPU which receives an interruption signal as an access permission signal after external access is completed. CONSTITUTION:An AC input part 100 inputs an external AC input at a constant period and outputs an interruption signal at the constant period through an interruption request line 300 after A/D conversion. A CPU 201, once receiving the access right with this interruption signal, completes all external access within a certain time and passes the access right to a CPU 202 through the interruption request line 300. The CPU 202 which receives the access right completes all external access within a certain time and passes the access right to a next CPU in order with an interruption signal of different level. Consequently, process data are not lost, the processing times of respective CPUs are made nearly constant, and this method is applied to the real-time system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus arbitration method in a so-called multi-CPU system in which a plurality of processing units (hereinafter also abbreviated as CPU) share one bus.

[0002]

2. Description of the Related Art In a multi-system in which a plurality of CPUs share one bus, a dedicated hardware for bus arbitration is conventionally used as a bus arbitration method for avoiding a collision of bus access by a plurality of CPUs. Is generally provided. FIG. 5 shows a general example.
CPUs 201 to 20n, a bus arbitration circuit 400, and 50
1 is a bus use request line, 502 is a bus use permission line, 503
Is a bus busy display line.

When each CPU 200 makes a bus access, first, a bus use request signal is output to the bus arbitration circuit 400 through the bus use request line 501. The bus arbitration circuit 400 monitors the bus use request line 501 and the bus busy display line 503, and if it confirms that the other CPU 200 is not using the bus and outputs no bus use request, A bus use permission signal is given to the CPU 200 which issued the use request through the bus use permission line 502. Upon receiving the bus use permission signal, the CPU 200 outputs a bus busy signal to the bus busy display line 503 to start bus access.

If another CPU 200 is in use of the bus when a certain CPU 200 issues a bus use request, the bus arbitration circuit 400 indicates that the CPU 200 in use of the bus has finished accessing and is in use of the bus. Wait until the signal disappears, and then issue the bus usage request CP
A bus use permission signal is given to U200. When a plurality of CPUs 200 request the bus use permission at the same time, the bus arbitration circuit 400 sends a bus use permission signal to the CPU 200 having the highest priority among them in accordance with the predetermined priority of the CPU 200. And another C after the bus of the CPU 200 is used
The PU 200 is given a bus use permission. In the system shown in FIG. 5, the bus arbitration circuit 400 is used for each CPU.
It was set up independently for 200, but this is for each CP
It may be built in the U200. Since the bus arbitration circuit 400 must determine the priority of each CPU 200, a plurality of bus use request lines 501 are required.
For example, it is usually composed of a number of lines corresponding to the CPU 200.

[0005]

That is, in the conventional bus arbitration method, since the timing of bus access of each CPU is arbitrary, a plurality of CPUs may issue a bus use request at the same time. In order to avoid a bus access collision, the CPU determines the priority of the CPU and grants the bus permission, that is, the hardware, that is, the bus arbitration circuit 400 as shown in FIG. However, when such a method is applied to a high-speed real-time processing system, the following problems occur.

(1) Since the timing of bus access is arbitrary, if a large number of CPUs happen to have bus use requests, the CPU with the lower priority can access the bus until all the upper CPUs have completed the bus access. However, the processing time of the CPU including the bus access will be abnormally extended only at that time (when the bus use requests of many CPUs overlap), and in the case of a system that maximizes the processing time of each CPU, There is a risk that the processing data will be missed once because the processing is not in time, and in the worst case, the system may be down due to the processing time being over or the bus access time monitoring timer being timed up.

(2) Generally, in a multi-CPU system, a plurality of CPUs share different processing contents, and one processing is executed as a whole while exchanging processing data with each other. Since the exchange of processing data between each other depends on the use of the system bus, if the bus use is random as described above,
The timing of data transfer between the CPUs is also random, resulting in fluctuations in the processing time of the multi-CPU system as a whole, which is disadvantageous to the real-time system.

(3) Further, since the CPU arbitration circuit determines the CPU priority and generates the bus use permission signal, it takes about 20 to 40% of the time when the CPU purely performs the bus access. In many systems, processing time including bus access increases. Therefore,
An object of the present invention is to eliminate omission of processing data and to make the processing time between CPUs substantially constant so that it can be applied to a real-time system.

[0009]

In order to solve such a problem, in the first invention, an interrupt signal of a predetermined level is sent to an arbitrary interrupt line of a plurality of CPUs sharing a system bus. A signal generating means for providing an access permission signal to the bus is provided, and the first CPU receiving the access permission signal from this signal generating means completes all external accesses within a fixed time and assigns a level different from the above. The CPU receives the access signal as an access permission signal to the second CPU, completes all external accesses within a fixed time, and issues an interrupt signal of a different level to the third CPU. It is characterized in that the operations given as access permission signals are sequentially executed.

According to the present invention, the access permission signals are passed in a predetermined order, and each CPU can receive the access permission signal only once during the entire cycle of all CPUs. Depending on the case, the access permission signals may be passed in a predetermined order, and each CPU may receive the access permission signal a plurality of times during one round of all CPUs.

[0011]

[Function] Each CPU can access the bus only when it has an access right, and the access right is passed in a predetermined order (determined by the interrupt level) using a normal interrupt signal line. Bus access is arbitrated by each CPU receiving the access right only once or while the access right goes through all the CPUs. Therefore, each CP
When the access right is received by U, all required bus accesses are completed within a fixed time, the access right is transferred to another CPU, and then the internal processing is performed. Further, the internal processing time after the output of the interrupt signal (access right transfer signal) of each CPU is designed to be shorter than the time until the access right comes next.

[0012]

1 is a schematic diagram showing an embodiment of the present invention, FIG.
Is a detailed time chart for explaining the operation, FIG.
Is also a simplified time chart. Reference numeral 100 in FIG. 1 indicates an AC input unit, and reference numeral 300 indicates an interrupt request line. The AC input unit 100 takes in an AC input from the outside at a constant cycle and converts it into an analog / digital (A
/ D) conversion, and after the A / D conversion is completed, an interrupt signal is output via the interrupt request line 300 at a constant cycle. This interrupt signal gives the CPU 201 an access right. When the CPU 201 receives the access right by the interrupt signal from the AC input unit 100, it takes in the data from the AC input unit 100 and other input units (not shown) internally, and outputs the data processed by that time to the outside. Output to the common memory, which is shown in Figure 2.
This corresponds to access 1 in FIG.

Immediately after the access 1, the CPU 201 hands over the access right to the CPU 202 through the interrupt request line 300 shown in FIG. 1, and starts the internal processing of the fetched data. The situation is shown in FIGS. The CPU 202, which has received the access right, starts access 2 as shown in FIGS. 2 and 3, fetches the data from the input section inside, and outputs a series of bus accesses for outputting the data processed up to that point to the common memory. After that, the access right is handed over to the CPU 203. As a result, the CPU 203 fetches the data from the input section through access 3 in the same manner as above,
After outputting the processing data of yourself, the access right to the CPU
Hand over to 204. CPU204 access C by access 4
It takes in the data of the PUs 201 to 203 and outputs its own processed data to the outside.

Since the access time of each CPU is constant (this means, for example, that access times 1 and 5 of the CPU 201 are equal, that is, access 1 of the CPU 201 and access 2 of the CPU 202 are equal. However, if the total time of accesses 1 to 4 is designed in advance to be shorter than the access right round-trip time, the system bus accesses of the CPUs will not collide. It is also clear from FIG. 3 that the processing time of the entire system is constant. In FIG. 3, the processing time of the entire system is indicated by a symbol T.

In FIG. 3, the AC input unit 100 of FIG.
The data output at the point of time is taken into the CPUs 201 to 203 by the accesses 1, 2, 3 and internally processed, and then output to the external memory by the accesses 5, 6, 7. The data is fetched by the CPU 204 by the access 8 and internally processed, and then output by the access 12 to the external output unit. Therefore, the processing time from the input to the output of the entire system is the time T shown in FIG. That is, since the order and timing of this data flow are unchanged in each access right circulation, the final processing result of the AC input at the time of 18 is output to the outside by the access of 16. In this way, the processing time of the entire system is kept constant. The order and timing of the data flow are merely examples, and it goes without saying that the data flow can be designed to be most convenient for the applied system.

FIG. 4 is a time chart for explaining another embodiment of the present invention. That is, in the above example, one CPU obtains the access right only once during the entire cycle of all CPUs (this time is indicated by τ), but here it is set to twice. Is. It should be noted that the number of times may be three or more if necessary. Since the other points are the same as those in the case of FIG. 1, the details are omitted.

[0017]

According to the present invention, the bus access collision and its processing time are prevented from increasing, so that the bus relay and the bus relay protection digital relay requiring a large amount of processed data and high-speed real-time processing are required. With regard to the system, etc., it is possible to make full use of the original processing power of each CPU, and a smaller multi-CPU than before.
It has been confirmed that it will be realized by the system. Also, since the processing time of the entire system is constant, the basic performance as a real-time system (in the case of a digital relay, the relay operation time is constant and there is little variation).
It becomes possible to improve. Furthermore, since the order and timing of data exchange between each CPU and the input / output unit are fixed and there is no arbitrariness, even in a system including software, there are few uncertainties in terms of time. This brings the advantage of increased reliability.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an embodiment of the present invention.

FIG. 2 is a detailed time chart for explaining the operation of FIG.

FIG. 3 is a simplified time chart for explaining the operation of FIG.

FIG. 4 is a time chart for explaining another embodiment of the present invention.

FIG. 5 is a schematic diagram showing a conventional example.

[Explanation of symbols]

100 ... AC input unit, 200 (201 to 20n) ... Processing unit (CPU), 300 ... Interrupt signal line, 400 ... Bus arbitration circuit, 501 ... Bus use request line, 502 ... Bus use permission line, 503 ... Bus in use Display line.

Claims (3)

[Claims] 1. A signal generating means for giving an interrupt signal of a predetermined level as an access permission signal to the system bus is provided to any one interrupt line of a plurality of CPUs sharing a system bus, and access is made from this signal generating means. The first CPU, which has received the permission signal, completes all external accesses within a fixed time and gives an interrupt signal of a different level to the second CPU as an access permission signal to receive the access permission signal. The multi-CPU system completes all external accesses within a fixed time and sequentially executes an operation of giving an interrupt signal of a level different from the above to the third CPU as an access permission signal. Bus arbitration method in. 2. The access permission signals are passed in a predetermined order, and each CPU receives the access permission signal only once during a round of all CPUs. A bus arbitration method in the multi-CPU system according to Item 1. 3. The access permission signals are passed in a predetermined order, and each CPU receives the access permission signal at a plurality of times during one cycle of all CPUs. 2. A bus arbitration method in the multi-CPU system described in 1.