JPH06205481A - Time division exchange switch - Google Patents

Abstract

PURPOSE:To simply and immediately recover a fault caused in a time division channel memory. CONSTITUTION:A time division channel memory 1 has a channel memory 3 used for usual exchange and a standby memory 2 used on the occurrence of a fault, a fault detection section 7 detects a fault in the channel memory 3 based on input time slot data from an incoming highway 9 and output time slot data outputted from an outgoing highway 10 and when a fault is detected, the fault occurrence location is informed to a fault processing control section 8, which sets a relation converting an address of the channel memory 3 being a location of fault occurrence into an address of the standby memory 2 to an address conversion section 4. The address conversion section 4 converts a write or read address to/from the faulty channel memory 3 into an address of the standby memory 2 based on the setting and a fault occurrence location in the channel memory 3 is replaced into the standby memory 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-division speech channel memory for performing exchange processing by controlling input / output time slots by controlling a write address and a read address for the time-division speech channel memory. The present invention relates to a time division exchange switch capable of recovering from a failure that has occurred in the.

[0002]

2. Description of the Related Art Conventionally, in a time-division exchange switch for performing exchange processing by controlling a write address and a read address of a time-division communication path memory and exchanging input / output time slots, A method of detecting a failure that has occurred in the time division speech path memory is considered.

For example, as a method of detecting a failure that has occurred in this time division speech path memory, a method of detecting a failure by a parity check is known.

Further, in Japanese Patent Laid-Open No. 3-104492, the same data is written in a duplicated channel memory, and the same data is collated by an output collating means to detect a fault by time-division exchange. The switch is listed.

However, these prior arts merely detect a fault occurring in the speech path memory, and do not mention normal recovery of the time division switch from the detection of this fault.

Therefore, the conventional time division exchange switch is
It was not possible to recover from the failure that occurred immediately, and it was necessary to newly provide a failure recovery means for recovering the failure after the failure was detected.

[0007]

As described above, the conventional time-division switching switch only detects a failure and cannot immediately recover from the time-division channel memory failure that has occurred. However, there was a problem that it was necessary to provide special means for restoration.

Therefore, an object of the present invention is to provide a time-division exchange switch capable of eliminating such a problem and recovering a fault occurring in the time-division communication path memory immediately and easily.

[0009]

SUMMARY OF THE INVENTION The present invention provides a time-division exchange switch for performing an exchange process by exchanging input / output time slots by controlling a write address and a read address for a time-division speech path memory. The time-division speech path memory is composed of a normal storage area and a spare storage area, and detecting means for detecting a failure occurrence point of the time-division speech path memory, and an address of the normal storage area based on the detection result of the detection means. Failure processing control means for setting a correspondence relationship between the address of the normal storage area and the address of the spare storage area for converting into the address of the spare storage area; and an exchange instruction address for the time division speech path memory. And a conversion means for converting based on the correspondence relationship.

[0010]

According to the present invention, the time-division speech path memory has a normal storage area used at the time of normal exchange and a spare storage area used at the time of failure, and the detection means has the input exchanged data and the output exchange data. And the failure in the time-division speech path memory is detected, and when the failure is detected, this failure occurrence location is output to the failure processing control means, and the failure processing control means uses the normal storage area that is the failure occurrence location. In order to convert the address of 1 to the address of the spare memory area, the conversion means sets the correspondence between the address of the faulty normal memory area and the address of the spare memory area. And the conversion means is
Based on this setting, by converting the replacement instruction address to the faulty time-divisional channel memory to the address of the spare storage area, the fault occurrence point in the normal storage area is replaced with the spare storage area. By adding a small amount of spare storage area to the speech channel memory, it is possible to quickly and easily recover from the failure of the time division speech channel memory.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram of a time division exchange switch according to the present invention.

In FIG. 1, the time division exchange switch is used for exchanging a predetermined time slot on the input side input from the input highway 9 with a communication channel memory 3 for exchanging a predetermined time slot on the output side when a failure occurs. A time-division speech path memory 1 having a spare memory 2 which is a memory to be used, and a speech path control unit 6 for controlling address designation of the time-division speech path memory 1 for exchange control by the time-division speech path memory 1. An input time slot data from the input highway 9 and an address generation section 5 which generates a designated address under the control of the speech path control section 6, and output time slot data output from the output highway 10 corresponding to the input time slot data. Failure detection section 7 for detecting a failure occurrence point in the time division speech path memory 1 by comparing
If a failure occurs based on the failure detection result of, the failure processing control unit 8 performs control to replace the failed location with the spare memory 2, and the failure processing occurs under the control of the failure processing control unit 8. The address conversion unit 4 is configured to convert the address at the designated location into an address in the spare memory 2 and output the address to the time-division speech path memory 1.

Next, the general operation of this time division exchange switch will be described.

First, when the failure detecting section 7 does not detect a failure in the time division speech path memory 1, a signal indicating that no failure has occurred is output to the failure processing control section 8.
In this case, the failure processing control unit 8 does not control the address conversion with respect to the address conversion unit 4, and the address generated in the address generation unit 5 remains as it is in the time division speech path memory 1
Is output to.

That is, the communication path control unit 6 controls the address generation unit 5 based on the call control information by operating the read address generated by the address generation unit 5 to perform time slot replacement control. Then, by randomly replacing the read addresses with the sequential write addresses generated by the address generator 5 and output to the time-division speech path memory 1, the input highway 9 connected to the time-division speech path memory is replaced. Time slot exchange processing is performed between the upper input time slot and the output time slot on the output highway 10. This is the same operation as a normal time division speech path switch.

On the other hand, when the failure detection section 7 detects a failure in the time division speech path memory 1, it outputs the location of the failure to the failure processing control section 8, and the failure processing control section 8 causes the failure to occur. The setting for converting the address of the specified location into an address in the spare memory 2 that is not normally used is set by the address conversion unit 4
Do against. Then, the address conversion unit 4 converts the address into the address set by the failure processing control unit 8. That is, the address of the location where the failure has occurred is converted into the address of the spare memory 1. Then, this converted address is output to the time-divisional speech path memory 1, and when the address of the location in the speech path memory 3 where the failure occurs is used, the address in the spare memory 2 is saved without using this location. The exchange process will be performed using the location of the translated address.

As a result, when a failure occurs in the speech path memory 3 in the time division speech path memory 1, the spare memory 2
The backup storage area is used for quick recovery.

Further, the occurrence of a failure is notified from the failure detecting section 7 to the outside.

FIG. 2 is a detailed block diagram of the configuration of the time division exchange switch which is an embodiment of the present invention.

2, the time-division exchange switch of FIG. 2 has a parity generator 11 for generating parity check data from input time slot data input from the input highway 19, and a predetermined input from the input highway 19. A channel memory m2 for exchanging an input time slot with a predetermined output time slot, a spare memory m1 which is a memory used for exchange when a failure occurs, and parity check data input from the parity generator 11. A time division speech path memory m having a parity memory m3 for storing, a speech path memory management table Ta which manages an empty / occluded state of the speech path memory m2, and a speech path memory management table Ta with reference to this speech path memory management table Ta A call path control unit for controlling designation of an address of the call path memory m2 for exchange control by the memory m2 8, a holding memory 17 for holding the designation of an address by the speech path control unit 18, an address generation unit 16 which circulates and generates an address corresponding to an input time slot, and a writing generated by the address generation unit 16. An address conversion unit 15 that converts the read address output from the address and holding memory 17 and outputs the converted address to the time-division communication channel memory m, and read corresponding to the write address of the parity check data written in the parity memory m3. Failure from the parity checker 12 and the parity checker 12 that performs a parity check from the parity check data output at the timing of the output time slot of the address and the output time slot data output from the communication path memory m2 at the same timing. To temporarily store the read address when the detection of Less temporary storage unit 1
3, the spare memory management table Tb for managing the empty / occluded state of the spare memory m1, and the faulty writing temporarily stored in the address temporary storage unit 13 when the detection of the fault is notified from the parity checker 12. The address conversion unit 15 controls the address and the spare memory stored in the spare memory management table Tb to set the address of the communication path memory m2 in which the failure is detected to the address of the spare memory m1 based on the empty state of the spare memory. It is composed of a failure processing control unit 14 for performing.

Here, the time division speech path memory m will be described.

FIG. 3 is a diagram showing the address space of the time division speech path memory m.

In FIG. 3, the time division speech path memory m is
The address space of the speech path memory m2 and the parity memory m3 and the address space of the spare memory m1 are divided so that the address space of the speech path memory m2 and the parity memory m3 and the address space of the spare memory m1 do not overlap each other. Has been done.

As shown in FIG. 3, the addresses of the speech path memory m2 and the parity memory m3 have N + 1 addresses from the address "0" to the address "N", and the address of the spare memory m1 is Address "N +
It has M addresses from 1 "to address" N + M ".

Next, the operation of this time division exchange switch will be described.

First, the case where no trouble has occurred in the speech path memory m2 will be described.

That is, the input time slot data input from the input highway 19 is time-divisionally transmitted in time slot units according to the sequential write address generated by the address generation unit 16 for each 125 μs (256 bit) frame. Channel memory m in channel memory m
Written to 2. At this time, the address conversion unit 15 outputs the write address generated by the address generation unit 16 as it is to the time division speech path memory m as parallel data.

On the other hand, the input time slot data input from the input highway 19 is also input to the parity generator 11, and the parity generator 11 generates parity check data for each time slot and corresponds to the input time slot. The address is written in the parity memory m3.

The call path control unit 18 also determines the output time slot of the input time slot data based on the call control information, searches the call path memory management table Ta, and finds that the corresponding output time slot is unused. After confirming that it exists, if it is not used, the read address corresponding to the determined output time slot position is written in the holding memory 17.

On the other hand, the holding memory 17 generates a read address based on the sequential write address generated by the address generator. Then, the address conversion unit 15 outputs the read address as it is as parallel data to the time division speech path memory m without performing address conversion.

Then, at the desired output time slot position, the input time slot data stored in the speech path memory m2 is read in time slot units by this read address, and is output to the output highway 20 as output time slot data. By doing so, the exchange process in units of time slots is executed.

When this output time slot data is output to the output highway 20, the parity check data stored in the parity memory m3 of the same read address is output to the parity checker 12 at the read timing of this read address. To be done.

The parity checker 12 performs a parity check from the input parity check data and the output time slot data corresponding thereto.

Then, the inspection result is output to the address temporary storage unit 13 and the failure processing control unit 14.

Next, a case where the parity checker 12 detects a failure will be described.

First, when the parity checker 12 detects that a failure has occurred in the speech path memory as a result of the parity check, the address temporary storage unit 13 temporarily stores the read address at the time of failure detection.

The failure processing control unit 14 notified of the occurrence of the failure retrieves the read address of the communication path memory in which the failure is detected from the address temporary storage unit 13 and registers the usage status of the spare memory m1. With reference to the spare memory management table Tb, the unused address of the spare memory m1 is searched, and the unused address of the spare memory m1 is extracted. Further, the failure processing control unit 14 replaces the setting for replacing the read address in which the failure is detected with the searched address of the unused spare memory m1 and the write address corresponding to the read address with the address of the unused spare memory m1. The setting is performed on the address conversion unit 15.

That is, the addresses corresponding to the read address and the write address where the failure is detected are set to the unused spare memory m1.

As a result, when the write address input from the address generation unit 16 or the read address input from the holding memory 17 is the address in which the fault is detected, the address conversion unit 15 controls the respective faults. It is converted into an address of the unused spare memory m1 set by the unit 14 and output to the time division exchange switch m.

The address conversion unit 15 is a rewritable lookup table composed of a high-speed memory or the like, and can be set so that different data is output for each input data. That is, it is converted into a write address and a read address input from the address generator 16 and the holding memory 17.

FIG. 4 is a diagram for explaining the address conversion of the address conversion unit 15.

In FIG. 4, in the initial state where no failure has occurred, the input address "n" is output as it is as the address "n". Meanwhile, the address "
If a failure occurs in n ″, the failure processing control unit 14
By searching the spare memory management table Tb, the spare memory m
It is searched that the address "N + k" of 1 is not used, and the value "N + k" of this address "N + k" is changed to the address "
Since it is replaced with the address value of n ", the address"
When n "is input, it is converted into the address" N + k "and output. That is, the memory area of the address" N + k "of the spare memory m1 is used for the exchange.

As a result, the memory at the location where the failure has occurred is replaced with the normal spare memory, and the failure recovery of the time division switch is performed.

In the above embodiment, the case where the failure detecting means detects the failure by the parity check has been described, but the failure detecting means is not limited to this.

In the above embodiment, the time-division exchange switch for replacing the memory address with respect to one time-division speech path memory has been described. However, when the exchange processing is performed using a plurality of time-division speech path memories, The unit to be replaced may be a memory element, that is, a plurality of time division channel memory units.

In this case, the replacement operation by the address conversion unit may replace only the chip select signals of the memory elements of the plurality of time division communication channel memories, instead of all the addresses of the plurality of time division communication channel switches. Further, this makes it possible to simplify the configurations of the address temporary storage unit and the address conversion unit.

[0048]

As described above, according to the present invention, the time division speech path memory has the normal storage area used at the time of normal exchange and the spare storage area used at the time of failure, and the detecting means receives the input target data. A fault in the time division speech path memory is detected from the exchange data and the output exchange data, and when the fault is detected, this fault occurrence point is output to the fault processing control means, and the fault processing control means In order to convert the address of the normal storage area, which is the location of the failure, into the address of the auxiliary storage area, the conversion means sets a correspondence relationship between the address of the failed normal storage area and the address of the auxiliary storage area. Then, the conversion means, based on this setting,
By converting the replacement instruction address to the faulty time-division speech path memory into the address of the spare storage area, the fault occurrence point in the normal storage area is replaced with the spare storage area. By adding a small amount of spare storage area to the memory, there is an advantage that the failure of the time division speech path memory can be quickly and easily recovered.

Moreover, since the failure is automatically recovered at the same time as the notification of the occurrence of the failure, there is an advantage that continuous communication can be maintained.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a time division exchange switch according to the present invention.

FIG. 2 is a detailed configuration block diagram of a time division exchange switch that is an embodiment of the present invention.

FIG. 3 is a diagram showing an address space of a time division speech path memory m.

FIG. 4 is a diagram illustrating address conversion by an address conversion unit 15.

[Explanation of symbols]

1 time division speech path memory 2 spare memory 3 speech path memory 4 address conversion unit 5 address generation unit 6 speech path control unit 7 failure detection unit 8 failure processing control unit 9 incoming highway 10 outgoing highway

Claims (1)

[Claims] 1. A time-division exchange switch that performs exchange processing by controlling a write address and a read address for the time-division speech path memory and exchanging input / output time slots, wherein the time-division speech path memory is normally stored. An area and a spare storage area, and detecting means for detecting a failure occurrence point in the time division speech path memory; and converting an address of the normal storage area into an address of the spare storage area based on a detection result of the detecting means. And a failure processing control means for setting a correspondence relationship between the address of the normal storage area and the address of the spare storage area, and a conversion for converting an exchange instruction address to the time division speech path memory based on the correspondence relationship. A time division exchange switch comprising: