JPH06204477A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which has a static electricity protective diode on an Si substrate by drawing wiring from a contact hole which is over the surface of a first conductivity type semiconductor substrate and the surface of a second conductivity type impurity diffused layer. CONSTITUTION:For an N-type substrate 100, LOCOS element isolation 101 is used, the thickness of a gate film 102 is permitted to be 10nm and the channel size of a polysilicon gate electrode 103 is permitted to be 0.3mum. After forming a layer insulating film 104, etching is performed so as to form a contact hole. The contact hole is formed on a drain 105 or source 106 permitting the contact hole to be over the surface of the drain or the source and the surface of the substrate adjacent to the drain or the source, then, an aluminum wiring layer is formed. Therefore, the device can be used as a protective diode for the thin gate insulating film manufactured for the semiconductor device high integration and miniaturization by forming a Schottky junction at the contact part.

Description

Detailed Description of the Invention

[0001]

The present invention relates to the structure of semiconductor devices.

[0002]

2. Description of the Related Art A structure of a conventional MIS type semiconductor device near a gate electrode is shown in FIG. The following methods have been used for protecting the gate insulating film of a conventional MIS semiconductor device from static electricity. Basically, when electrostatic stress is applied to the input / output terminals of the semiconductor integrated circuit, the protection circuit turns on when the voltage applied to the gate exceeds a certain voltage to release the electric charge, thereby protecting the gate insulating film from the electrostatic stress. Take the way. Therefore, a method has been used in which a P-N junction diode between a drain and a silicon substrate of a transistor formed in a MIS type semiconductor integrated circuit is used as a Zener diode and a certain voltage or more is not applied to a gate insulating film.

By the way, in order to achieve higher speed and finer structure, the gate insulating film should be thinned in order to advance the finer structure, higher integration, higher density and higher speed required for the MIS type semiconductor integrated circuit. Need to go. As a result, the MIS type semiconductor integrated circuit becomes weak against electrostatic stress. Therefore, in that case, it becomes necessary to reduce the off-break voltage between the drain and the silicon substrate, which has been used as a Zener diode for protecting the gate insulating film.

By the way, in order to lower the off-break voltage of the diode utilizing the drain-silicon substrate in the MIS type semiconductor, a method has been used in which the concentration of the substrate impurity in contact with the drain is increased to lower the breakdown voltage of this junction. .

Whether this method can be used to reduce the thickness of the gate insulating film is considered. The gate insulating film is a silicon oxide film and its thickness is 15 nm. In this case, if the Fowler-Nordheim current jumps into the gate film and the gate film is destroyed, the voltage that can be applied to the gate electrode is usually 10 to 11 V, though it depends on the quality of the gate film. On the other hand, regarding the breakdown voltage between the drain and the silicon substrate, the impurity concentration in the vicinity of the surface of the substrate is set to 5 by considering only the substrate concentration from the order difference between the drain and the silicon substrate.
× 10 ¹⁶ cm ^-3 . In addition, the breakdown electric field of silicon is set to 0.
When the voltage is 3 MV / cm, the breakdown voltage between the drain and silicon is about 12 to 13V. Since this value adopts the lowest value of the breakdown field of silicon, it may actually be a higher value. Further, increasing the substrate concentration more than this causes an increase in junction leak, which makes high integration difficult. Therefore, a method other than using the diode between the drain and the silicon substrate is desired.

[0006]

In the MIS type semiconductor integrated circuit, the thinning of the gate insulating film is an absolute condition for the progress of speeding up and miniaturization. As a result, the gate insulating film is electrostatically stressed. Therefore, it is necessary to lower the breakdown voltage between the drain and silicon substrate used as a Zener diode that protects the gate insulating film. As a method of lowering the breakdown voltage between the drain and the silicon substrate,
Generally, there is a method of increasing the substrate concentration. However, if the substrate concentration is increased to meet the requirement of lowering the break voltage in order to maintain the resistance of the gate insulating film against electrostatic stress, the junction capacitance of the drain increases, impeding speedup, and further flowing in the junction. Since the junction leak current cannot be suppressed, high integration is becoming difficult.

Therefore, there is a trade-off relationship between resistance to electrostatic stress and power consumption, and it is practically impossible to produce an integrated circuit using a device having a gate insulating film thickness of 10 nm or less and a design rule of submicron rule or less. there is a possibility.

Therefore, by protecting the gate insulating film, it is conceivable to separately form a protection diode region without using a transistor as in the conventional case. However, increasing only the substrate concentration in the protection diode region means that the conventional method requires partial control of the conductivity type impurity concentration, which not only increases the number of manufacturing steps but also requires the protection diode region. It goes against the miniaturization. Further, as miniaturization progresses, the film thickness between layers becomes thinner and the diffusion layer becomes thinner, and the influence of the electric field from the wiring layer running on the upper layer also increases. It has the problem of being lost.

Therefore, in response to the thinning of the gate insulating film accompanying the higher integration and miniaturization of the semiconductor device, the withstand voltage is lower than the drain-silicon substrate withstand voltage used in the Zener diode for protecting the gate insulating film, and the semiconductor device It is an object of the present invention to provide a semiconductor device having an electrostatic protection diode on a Si substrate without increasing the area and in the same manufacturing process as the conventional one.

[0010]

A semiconductor device of the present invention is a MIS type semiconductor device using a first conductivity type semiconductor substrate, and a second conductivity type impurity diffusion layer formed on the surface of the semiconductor substrate on both sides of a gate electrode. A surface of the first conductivity type substrate adjacent to at least one surface of the second conductivity type impurity diffusion layer, and a contact hole extending over the surface of the first conductivity type semiconductor substrate and the surface of the second conductivity type impurity diffusion layer. It is characterized in that it consists of wiring.

The semiconductor device of the present invention is a MIS type semiconductor device using a first conductivity type substrate, wherein the surface of the second conductivity type impurity diffusion layer formed on the surface of the semiconductor substrate on both sides of the gate electrode and at least one of the first conductivity type substrate. A first-conductivity-type impurity diffusion layer surface adjacent to the second-conductivity-type impurity diffusion layer surface, and a refractory metal silicide film extending over the first-conductivity-type semiconductor substrate surface and the second-conductivity-type impurity diffusion layer surface, It is characterized in that it consists of a part of wiring.

[0012]

As an embodiment of the present invention, FIG. 1 shows a cross-sectional structure of a MIS type semiconductor device having a metal lead wiring over a drain surface and a substrate surface. FIG. 2 shows a MIS type semiconductor device having a drain surface and a substrate. A cross-sectional structure of a structure having a refractory metal silicide over the surface and having metal wiring drawn out from a part thereof will be described.

FIG. 1 shows a MIS transistor having a P-channel structure formed on an N-type substrate 100. In this embodiment, the LOCOS element isolation 101 is used for element isolation, and the thickness of the gate film 102 is 10 nm. The channel size of the polysilicon gate electrode 103 is 0.3μ
m. After forming the interlayer insulating film 104, contact
Etching is performed to form holes. This contact hole is a hole for forming a contact portion between the drain and the source and aluminum, but unlike the conventional structure, in one of the drain 105 and the source 106, the drain or the source surface and the substrate adjacent to the drain or the source are formed. A contact hole is formed so as to extend over the surface. Then, an aluminum wiring layer is formed.

In the semiconductor device having the above structure, the Schottky diode on the aluminum-silicon substrate adjacent to the drain or source in the contact hole is used as a leak circuit for protecting the gate insulating film. In the case of this embodiment, the voltage that can be applied to the gate insulating film is 7 to 8V. The breakdown voltage of a Schottky junction on an aluminum-N-type silicon substrate is 4 V when the breakdown electric field of silicon is 0.3 MV / cm and the concentration of N-type impurities near the surface of the silicon substrate is 5 × 10 ¹⁶ cm ^-3. Becomes
Further, when the concentration of the N-type impurity is set to 1 × 10 ¹⁷ cm ⁻³ or more, a leak current flows from a low voltage due to the influence of the tunnel current, which makes it difficult to use as a protection circuit. Since this calculated value is the theoretical minimum value, it is considered that when this junction is actually formed, it is increased by about 2 to 3 V due to the influence of the crystallinity of silicon and the impurity level at the junction interface. This withstand voltage value is a withstand voltage value that can further reduce the thickness of the gate insulating film to 10 nm or less.

In this embodiment, aluminum is used for the metal wiring, but other wiring metals such as gold, silver, copper,
It goes without saying that molybdenum, tungsten, titanium and compounds of these metals with other substances can be applied as a metal-silicon bond.

FIG. 2 shows a P-channel structure MIS transistor formed on an N-type substrate 200. In this embodiment, the LOCOS device isolation 201 is used for device isolation, and the thickness of the gate film 202 is 10 n in this embodiment.
m.

The polysilicon gate electrode 203 has a thickness of 0.3 μm.
m. After forming the polysilicon gate, a refractory metal silicide is formed by self-alignment over the drain or the source and the drain or the substrate adjacent to the source.

When the semiconductor device having the above structure is used, the breakdown voltage of the Schottky diode between the refractory metal silicide and the silicon substrate is such that the breakdown electric field of silicon is 0.
If the N-type impurity concentration in the vicinity of the surface of the silicon substrate is 3 MV / cm and 5 × 10 ¹⁶ cm ⁻³ , the refractory metals used are molybdenum, tungsten, nickel, titanium, zirconium, hafnium, chromium, cobalt, platinum, etc. By doing so, it is possible to obtain a desired breakdown voltage of 4 to 7 V by utilizing the work function value unique to each. Also, the N-type impurity concentration near the surface of the silicon substrate is set to 1 × 10 ¹⁷ cm
^When it is set to ^-3 or more, the leakage current flows from a low voltage due to the influence of the tunnel current, making it difficult to use as a protection circuit. This makes it possible to cope with the gate insulating film having a thickness of 10 nm or less.

It goes without saying that the same applies to the P-type transistors having the two structures described so far even for N-type transistors.

[0020]

According to the present invention described above, in the MIS type semiconductor device, the semiconductor device is formed by forming the metal-semiconductor Schottky junction in a part of the contact portion between the wiring layer and the drain or the source. It can be used as a diode for protecting the gate insulating film against thinning of the gate insulating film due to higher integration and miniaturization. In addition, the gate insulating film 10
It can be used as a protection diode against thinning to m or less.

In the case of using a refractory metal,
By replacing the refractory metal used, it becomes possible to provide a gate protection Schottky diode having a desired breakdown voltage.

Further, the semiconductor device of the present invention can be provided with the same steps and the same number of steps as the conventional one, only by changing the mask position in order to change the contact or silicide formation position from the conventional semiconductor device. it can.

[Brief description of drawings]

FIG. 1 is a main cross-sectional view showing a semiconductor device of the present invention.

FIG. 2 is a main sectional view showing a semiconductor device of the present invention.

FIG. 3 is a main cross-sectional view showing a conventional MIS type semiconductor device.

[Explanation of symbols]

 100 ... N-type substrate 101 ... LOCOS element isolation film 102 ... Gate insulating film 103 ... Polysilicon gate electrode 104 ... Interlayer insulating film 105 ... Drain diffusion layer 106 ... Source diffusion Layer 107 ... Aluminum wiring layer 200 ... N-type substrate 201 ... LOCOS element isolation film 202 ... Gate insulating film 203 ... Polysilicon gate electrode 204 ... Interlayer insulating film 205 ... Drain Diffusion layer 206 ... Source diffusion layer 207 ... Aluminum wiring layer 208 ... Refractory metal silicide 300 ... N-type substrate 301 ... LOCOS element isolation film 302 ... Gate insulating film 303 ... Polysilicon gate electrode 304 ... Interlayer insulating film 305 ... Drain diffusion layer 306 ... Source diffusion layer 307. - aluminum wiring layer

Claims (4)

[Claims] 1. In a MIS type semiconductor device using a first conductivity type semiconductor substrate, a surface of a second conductivity type impurity diffusion layer formed on the surface of the semiconductor substrate on both sides of a gate electrode, and at least one of the second conductivity types. A contact surface of the first conductivity type substrate adjacent to the surface of the second conductivity type impurity diffusion layer, the surface of the first conductivity type semiconductor substrate, and the surface of the second conductivity type impurity diffusion layer.
A semiconductor device characterized in that wiring is pulled out from a hole. 2. The semiconductor device according to claim 1, wherein the concentration of the first conductivity type impurity diffusion layer near the surface of the semiconductor substrate is 1 × 10 ¹⁷ cm ⁻³ or less. 3. A MIS type semiconductor device using a first conductivity type semiconductor substrate, wherein a surface of a second conductivity type impurity diffusion layer formed on the surface of the semiconductor substrate on both sides of a gate electrode, and at least one of the second conductivity types. A first-conductivity-type substrate surface adjacent to the second-conductivity-type impurity diffusion layer surface, a film containing a high-melting-point metal as a main component that extends over the first-conductivity-type semiconductor substrate surface and the second-conductivity-type impurity diffusion layer surface, and the high-melting point A semiconductor device, wherein wiring is drawn from a part of a film containing metal as a main component. 4. The semiconductor device according to claim 3, wherein the concentration of the first conductivity type impurity diffusion layer near the surface of the semiconductor substrate is 1 × 10 ¹⁷ cm ⁻³ or less.