JPH06204161A - Method for forming source/drain on semiconductor element - Google Patents
Method for forming source/drain on semiconductor elementInfo
- Publication number
- JPH06204161A JPH06204161A JP5261227A JP26122793A JPH06204161A JP H06204161 A JPH06204161 A JP H06204161A JP 5261227 A JP5261227 A JP 5261227A JP 26122793 A JP26122793 A JP 26122793A JP H06204161 A JPH06204161 A JP H06204161A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- ions
- source
- implanted
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 150000002500 ions Chemical class 0.000 claims abstract description 29
- 238000010438 heat treatment Methods 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910052796 boron Inorganic materials 0.000 abstract description 8
- 238000002513 implantation Methods 0.000 abstract description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 7
- -1 argon ion Chemical class 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000035515 penetration Effects 0.000 description 2
- XUKUURHRXDUEBC-SXOMAYOGSA-N (3s,5r)-7-[2-(4-fluorophenyl)-3-phenyl-4-(phenylcarbamoyl)-5-propan-2-ylpyrrol-1-yl]-3,5-dihydroxyheptanoic acid Chemical compound C=1C=CC=CC=1C1=C(C=2C=CC(F)=CC=2)N(CC[C@@H](O)C[C@H](O)CC(O)=O)C(C(C)C)=C1C(=O)NC1=CC=CC=C1 XUKUURHRXDUEBC-SXOMAYOGSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はアルゴンイオン(A
r+)の注入により浅い結合(shallow junction)のソー
ス/ドレインを半導体素子に形成する方法に関する。BACKGROUND OF THE INVENTION The present invention relates to an argon ion (A
A method of forming a shallow junction source / drain in a semiconductor device by implantation of r + ).
【0002】[0002]
【従来の技術】一般的に、ミクロン単位以下の大きさに
おいて工程が進行される半導体素子においては、側面の
大きさに応じて垂直の大きさもバランスを取って形成し
なければならず、そのためソース/ドレイン接合の深さ
も浅くしなければならない。2. Description of the Related Art Generally, in a semiconductor device in which a process is performed in a size of a micron or less, a vertical size must be formed in balance according to a size of a side surface. The depth of the / drain junction must also be shallow.
【0003】従来の半導体素子のソース/ドレイン形成
は、図1に示すように、不純物B11イオン又はBF2イ
オンの注入後に熱処理により深い接合(deep junctio
n)が形成されるので浅い接合が要求されるミクロン級
以下の素子には適用し難い。即ち、上記のB11イオンを
注入する場合、浅い接合を形成するためには20KeV
以下の低いエネルギーでB11イオンを注入しなければな
らないが、かかる1015原子/cm2以上の高濃度不純
物を注入するとき、30KeV以下の低いエネルギービ
ーム電流セッティング等の問題によって、事実上低エネ
ルギーで高濃度不純物を注入することは不可能である。
更に、BF2イオンを注入する場合は、上記B11イオン
の短所を補完するために用いられるもので、BF2イオ
ンが注入された直後の状態で浅い浸透深さを有すること
により接合を形成するもので、この場合には熱処理を経
た後に0.15〜0.18μm程の浅い接合を形成する
には限界があった。As shown in FIG. 1, the conventional source / drain formation of a semiconductor device is a deep junction (deep junction) by heat treatment after implantation of impurity B 11 ions or BF 2 ions.
Since n) is formed, it is difficult to apply it to a micron-class or smaller device that requires a shallow junction. That is, when implanting the above B 11 ions, 20 KeV is required to form a shallow junction.
B 11 ions must be implanted at a low energy below, but when such a high-concentration impurity of 10 15 atoms / cm 2 or more is implanted, due to problems such as low energy beam current setting of 30 KeV or less, the energy is actually low. Therefore, it is impossible to implant high-concentration impurities.
Further, in the case of implanting BF 2 ions, it is used to complement the disadvantages of the above B 11 ions, and a junction is formed by having a shallow penetration depth immediately after the implantation of BF 2 ions. However, in this case, there was a limit to forming a shallow junction of about 0.15 to 0.18 μm after heat treatment.
【0004】また、図2に示すように、半導体基板にA
s,Si,Geイオンを予め注入して単結晶層上に非晶
質層を形成した後に、図3に示すように非晶質層にp+
型ソース/ドレイン形成のためのB11又はBF2イオン
を注入した後、熱処理を行ってソース/ドレインを形成
する方法がある。Further, as shown in FIG.
After the s, Si, and Ge ions are implanted in advance to form the amorphous layer on the single crystal layer, p + is added to the amorphous layer as shown in FIG.
There is a method of implanting B 11 or BF 2 ions for forming a mold source / drain and then performing heat treatment to form a source / drain.
【0005】しかし、この方法も予め形成されている非
晶質層にB11、BF2イオンを注入するとき、基板への
浸透深さを調節し難く、図3のグラフに示すとおり注入
されたボロンイオンの熱処理時に非晶質層と単結晶層に
おけるボロン拡散差異によって熱処理後に深い結合が形
成される。この場合、ボロンは空孔(vacancy)におけ
る拡散より間隙(interstitial)における拡散度が大き
いため、空孔(vacancy)が豊富な非晶質層においては
拡散が小さくなり、間隙(interstitial)が豊富な単結
晶層においては拡散が大きくなって、結果的に深い接合
が形成される。更に、As(5族)、Si(4族)、G
e(4族)イオンを注入することにより、基板の物性自
体が変化してしまうという問題があった。However, this method also makes it difficult to control the depth of penetration into the substrate when implanting B 11 and BF 2 ions into a preformed amorphous layer, and the implantation was performed as shown in the graph of FIG. During the heat treatment of boron ions, a deep bond is formed after the heat treatment due to the difference in boron diffusion between the amorphous layer and the single crystal layer. In this case, since boron has a higher diffusivity in the interstitial than that in the vacancy, the diffusion becomes smaller in the amorphous layer rich in the vacancy, and the rich interstitial is generated. In the single crystal layer, the diffusion becomes large, resulting in the formation of a deep junction. Furthermore, As (group 5), Si (group 4), G
There is a problem that the physical properties of the substrate itself are changed by implanting e (group 4) ions.
【0006】[0006]
【発明が解決しようとする課題】本発明は、上記問題点
を解決するためイオン注入する際にアルゴンイオン(A
r+)を追加して空孔(vacancy)が豊富な層の厚さを調
節することにより、熱処理後にも浅い接合を実現するこ
とができるアルゴンイオン(Ar+)注入によるポスト
アモルファイズ(post amorphize)方法により浅い結合
のソース/ドレインを形成する方法を提供することを目
的とする。SUMMARY OF THE INVENTION In order to solve the above problems, the present invention is directed to argon ion (A
By adding r + ) to control the thickness of the layer rich in vacancy, a shallow junction can be realized even after the heat treatment by post-amorphize by implantation of argon ions (Ar + ). ) Method of forming shallow coupled source / drain by the method.
【0007】[0007]
【課題を解決するための手段】本発明は上記目的を達成
するため、半導体基板にソース/ドレインを形成する不
純物イオンを注入した後に該不純物イオン注入層下にA
r+イオンを注入して非晶質層を形成し、その後に熱処
理をすることを特徴とする半導体素子のソース/ドレイ
ンを形成する方法を提供する。In order to achieve the above-mentioned object, the present invention achieves the above object by implanting impurity ions for forming source / drain into a semiconductor substrate, and then forming A under the impurity ion-implanted layer.
Provided is a method for forming a source / drain of a semiconductor device, which comprises implanting r + ions to form an amorphous layer and then performing heat treatment.
【0008】[0008]
【実施例】以下、図4を参照して本発明の実施例を詳細
に説明する。Embodiments of the present invention will be described in detail below with reference to FIG.
【0009】半導体基板にP+型ソース/ドレインを形
成する不純物B11又はBF2イオンを注入した後に該p+
型不純物イオン注入層下にAr+イオンを注入して非晶
質層を形成し、熱処理を施して浅い接合を得る。このよ
うにAr+イオンを注入して非晶質層を形成すれば、こ
の層で空孔(vacancy)が豊富に形成されて、熱処理中
に基板内へのボロンの拡散程度が低くなるため、浅い接
合が形成される。即ち、Ar+イオンの注入により形成
された非晶質層が基板内へのボロン拡散を防止し浅い結
合が形成されるのである。After implanting impurities B 11 or BF 2 ions for forming P + type source / drain into the semiconductor substrate, the p +
Ar + ions are implanted below the type impurity ion-implanted layer to form an amorphous layer, and heat treatment is performed to obtain a shallow junction. When the amorphous layer is formed by implanting Ar + ions in this manner, vacancy is abundantly formed in this layer, and the degree of diffusion of boron into the substrate during the heat treatment is reduced. A shallow junction is formed. That is, the amorphous layer formed by the implantation of Ar + ions prevents boron diffusion into the substrate and forms a shallow bond.
【0010】上記本発明の実施例においてはp+型を中
心に説明したが、n+型のソース/ドレイン形成におい
ても同一の工程により浅い接合を得ることができる。In the above-described embodiments of the present invention, the p + type was mainly described, but a shallow junction can be obtained by the same steps in forming the n + type source / drain.
【0011】[0011]
【発明の作用・効果】上記のとおり、本発明による浅い
接合のソース/ドレインを形成する方法は、ボロンの活
性化のための熱処理に高温熱処理を適用できるため、不
純物注入による基板の損傷を補償することができ、ミク
ロン級単位以下の素子に要求される漏れ電流を減少させ
る効果がある。As described above, in the method of forming the source / drain of the shallow junction according to the present invention, since the high temperature heat treatment can be applied to the heat treatment for activating boron, the damage of the substrate due to the impurity implantation is compensated. It is possible to reduce the leakage current required for a device of micron class or less.
【図1】 従来技術によるp+型ソース/ドレイン形成
方法を示す図。FIG. 1 is a diagram showing a conventional p + type source / drain forming method.
【図2】 従来技術による他のp+型ソース/ドレイン
形成方法の第1工程を示す図。FIG. 2 is a diagram showing a first step of another p + type source / drain forming method according to the prior art.
【図3】 上記p+型ソース/ドレイン形成方法の第2
工程を示す図。FIG. 3 is a second method of forming the p + type source / drain.
The figure which shows a process.
【図4】 本発明によるp+型ソース/ドレイン形成方
法を示す図である。FIG. 4 is a diagram showing a p + type source / drain formation method according to the present invention.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 サン キ ホン 大韓民国 キョウンキド イチヨンクン ブバリュブ アミ−リ サン 136−1 (72)発明者 ユン アーム ヤン 大韓民国 ソウル ソンパク バンギドン オリンピック サンスチョン アパート 107−903 (72)発明者 ヤエ ウォアン コー 大韓民国 キョウンキド ションナム−シ ヨンウォンク ユンハエン 1 ドン ヒュンダイ アパート 101−907 (72)発明者 イル スン ヒュン 大韓民国 ソウル カンドンク サンギル ドン ユーコン アパート 301−405 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor San Ki Hong Republic of Korea Kyung Kydo Kyung Kun Buvalub Amy Risan 136-1 (72) Inventor Yun Arm Yang South Korea Seoul Sung Pak Bangui Don Olympic Sancheon Apartment 107-903 (72) Inventor Yae Wankok Republic of Korea Kyungkidonnam-Shyeonwonk Yunhaen 1 Dong Hyundai Apartment 101-907 (72) Inventor Ilsung Hyun Korea Seoul Kangdong Sangyil Dong Yukon Apartment 301-405
Claims (2)
る不純物イオンを注入した後に該不純物イオン注入層下
にAr+イオンを注入して非晶質層を形成し、その後に
熱処理をすることを特徴とする半導体素子のソース/ド
レイン形成方法。1. A method of implanting impurity ions for forming a source / drain into a semiconductor substrate, implanting Ar + ions under the impurity ion-implanted layer to form an amorphous layer, and then performing heat treatment. And method for forming source / drain of semiconductor device.
物イオンがB11イオン又はBF2イオンのいずれかであ
ることを特徴とする請求項1に記載のソース/ドレイン
形成方法。2. The method of forming a source / drain according to claim 1, wherein the impurity ions forming the source / drain are either B 11 ions or BF 2 ions.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1992-19166 | 1992-10-19 | ||
KR1019920019166A KR950013432B1 (en) | 1992-10-19 | 1992-10-19 | P-type source/drain making method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06204161A true JPH06204161A (en) | 1994-07-22 |
JP3084684B2 JP3084684B2 (en) | 2000-09-04 |
Family
ID=19341351
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP05261227A Expired - Fee Related JP3084684B2 (en) | 1992-10-19 | 1993-10-19 | Method for forming source / drain of semiconductor device |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP3084684B2 (en) |
KR (1) | KR950013432B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08181085A (en) * | 1994-12-21 | 1996-07-12 | Nec Corp | Manufacture of semiconductor device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100112788A1 (en) * | 2008-10-31 | 2010-05-06 | Deepak Ramappa | Method to reduce surface damage and defects |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0485926A (en) * | 1990-07-30 | 1992-03-18 | Matsushita Electric Ind Co Ltd | Manufacturing method of semiconductor device |
-
1992
- 1992-10-19 KR KR1019920019166A patent/KR950013432B1/en not_active IP Right Cessation
-
1993
- 1993-10-19 JP JP05261227A patent/JP3084684B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0485926A (en) * | 1990-07-30 | 1992-03-18 | Matsushita Electric Ind Co Ltd | Manufacturing method of semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08181085A (en) * | 1994-12-21 | 1996-07-12 | Nec Corp | Manufacture of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
KR950013432B1 (en) | 1995-11-08 |
KR940010188A (en) | 1994-05-24 |
JP3084684B2 (en) | 2000-09-04 |
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