JPH06204101A - Semiconductor wafer - Google Patents

Abstract

PURPOSE:To obtain a semiconductor wafer, in which a probe test can be easily conducted in a short time, by forming marks in the vicinity of the intersecting parts of scribe lines separating respective chip patterns. CONSTITUTION:Index marks 16, in which lines each having a width of about 50mum intersect crosswise, are formed in the intersecting parts of scribe lines 15 dividing respective chip patterns 11-14. These index marks 16 are composed of aluminum, polysilicon, etc., and formed in the wiring process of respective chip patterns 11-14 when respective materials vapor-deposited or accumulated on an insulating film are patterned simultaneously with wiring. Consequently, the index marks 16 are maintained at certain easily visible sizes so as to be readily confirmed through a microscope at the time of a probe test. Also, the position for forming each chip pattern can be easily confirmed when the index mark is used as a clue.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer having a matrix of chip patterns having a plurality of sub chip patterns.

[0002]

2. Description of the Related Art Conventionally, as this type of chip pattern,
For example, there is a configuration shown in FIG. This chip pattern 1 includes nine sub chip patterns SUB1 to SUB1.
It is composed of SUB 9 and is patterned at one time by one reticle. Each sub chip pattern SU
Each of B1 to SUB9 constitutes one unit of an integrated circuit, and is arranged in a matrix form with scribe lines 2 having substantially the same width. The chip patterns 1 are further arranged in a matrix on the semiconductor wafer with scribe lines having substantially the same width. This semiconductor wafer is diced along each scribe line 2,
Each of the sub chip patterns SUB1 to SUB9 is divided into pellets.

For such a semiconductor wafer, a probe test is carried out before each sub-chip is divided into pellets to judge the quality of the wafer process. Each sub-chip pattern SUB1 to SUB9 has a sub-chip name for identifying mutual sub-chips. For example,
As shown in FIG. 2B, the sub chip pattern SUB1 has a sub chip name "SUB1" in the lower right corner. By observing such a sub-chip name with a microscope during a probe test, the formation position of one chip pattern 1 can be identified. For example, the sub chip patterns SUB9, S located at the corners of each chip pattern 1
If the formation positions of UB3, SUB1 and SUB7 are distinguished, the section of each chip pattern 1 is discriminated. The probe test is performed in units of this one chip pattern 1.

[0004]

However, in the above conventional semiconductor wafer, there are cases where a sufficiently large subchip name cannot be entered due to the layout of each subchip. Therefore, in such a case, it becomes difficult to read the sub-chip name during the probe test, and the probe test takes time.

On the other hand, the type of sub chip can be judged from the layout of the chip pattern without looking at the name of the sub chip, but such judgment can be made only by a person who has a good understanding of the layout of the chip pattern. Therefore, when entrusting the probe test to another person, it was difficult to give a work instruction.

[0006]

The present invention has been made to solve such a problem, and is a chip pattern composed of a plurality of sub-chip patterns arranged in a matrix with scribe lines having substantially the same width. Is formed,
Further, in a semiconductor wafer formed by arranging the chip patterns in a matrix shape with scribe lines having substantially the same width as the scribe lines formed, marks are formed in the vicinity of the intersections of the scribe lines separating the chip patterns. It is characterized by that.

[0007]

[Effect] Regardless of the layout pattern in each sub-chip, the scribe line that divides each chip pattern has a blank area with a certain size, and the mark formed in this area has a certain size. To be kept. Therefore, the mark is easily visible. Further, the formation position of each chip pattern can be easily identified by using this mark as a clue.

[0008]

FIG. 1 shows a part of a chip pattern formed in a matrix on the surface of a semiconductor wafer according to an embodiment of the present invention.

Each of the chip patterns 11 to 14 is 9
Each of the sub chip patterns SUB1 to SUB9 is formed, and one sub chip pattern SUB is formed within a 5 mm square frame. Each of these nine sub chip patterns SUB1 to SUB9 is patterned at once by one reticle, and the inside of each chip pattern 11 to 14 has the same sub chip configuration.

In each of the chip patterns 11 to 14, the sub chip patterns SUB1 to SUB9 are arranged in a matrix form with the scribe lines 15 separated from each other, and the chip patterns 11 to 14 in which these sub chips are assembled are also arranged. The scribe lines 15 are arranged in a matrix form. The scribe line 15 has a width of about 100 μm, and each sub chip pattern SUB1 to S
The UBs 9 and the chip patterns 11 to 14 are kept at a substantially constant interval with a distance of about 100 μm.

At the intersection of the scribe lines 15 that partition the chip patterns 11 to 14, the width is about 50 μm.
An index mark 16 in which the line of m intersects in a cross shape is formed. The index mark 16 is made of aluminum Al, polysilicon or the like, and is formed by patterning each material vapor-deposited or deposited on the insulating film at the same time as the wiring in the wiring process of the chip patterns 11 to 14.

Sub-chip patterns SUB1 to SUB9
Regardless of the internal layout pattern, the scribe line 15 that divides the chip patterns 11 to 14 has a blank area of 100 μm width. Therefore,
In this embodiment, the index mark 16 formed on the scribe line 15 can be always drawn with a line having a width of 50 μm. For this reason, the index mark 16 is kept in a certain size that is easily visible, and can be easily viewed with a microscope during a probe test. Therefore, it is not necessary to change the layout in the sub-chip pattern in order to secure the area for inserting the sub-chip name as in the conventional case. If the index mark 16 is found, each index pattern 16 is used as a clue.
The formation positions of 1 to 14 are easily determined. As a result, in the probe test, it is no longer necessary to read the sub-chip name, and the probe test can be easily performed in a short time. Further, even when the probe test is given to a person who is not familiar with the layout of the chip pattern, the test work can be easily instructed by explaining the index mark 16 formed on the scribe line 15.

The position where the index mark 16 is formed is determined by the device TEG (Test El) on the scribe line 15.
ment group), any location may be used in the vicinity of the intersection of the scribe lines 15 that partition each chip pattern. Further, although the index mark 16 is made of a wiring metal or the like formed on the insulating film in the above-mentioned embodiment,
A hole may be formed in the insulating film and this hole may be used as an index mark. Even with such a mark, the same effect as that of the above embodiment can be obtained.

[0014]

As described above, according to the present invention, the scribe line for partitioning each chip pattern is formed with a blank area having a certain size regardless of the layout pattern in each sub-chip. The mark formed in this area is kept at a constant size. Therefore, the mark is easily visible. Further, the formation position of each chip pattern can be easily identified by using this mark as a clue.

Therefore, according to the present invention, the probe test can be easily performed in a short time.

[Brief description of drawings]

FIG. 1 is a plan view showing a part of a chip pattern formed on a semiconductor wafer according to an embodiment of the present invention.

FIG. 2 is a plan view showing a part of a chip pattern formed on a conventional semiconductor wafer.

[Explanation of symbols]

11 to 14 ... Chip pattern, 15 ... Scribe line, 16 ... Index mark, SUB1 to SUB9 ...
Sub-chip pattern.

Claims (2)

[Claims] 1. A chip pattern formed of a plurality of sub-chip patterns arranged in a matrix with scribe lines having substantially the same width is formed, and the chip pattern further comprises scribe lines having substantially the same width as the scribe line. A semiconductor wafer, which is formed by arranging in a matrix in a spaced manner, wherein marks are formed in the vicinity of intersections of scribe lines that separate the chip patterns. 2. The semiconductor wafer according to claim 1, wherein the mark is made of a wiring metal patterned in a chip pattern wiring process.