JPH0619833A - Bus controller - Google Patents

Abstract

PURPOSE:To transfer data between bus masters different in transfer modes without contradiction by automatically concealing a bus transfer state signal transmitted to the bus master in a slave state for an arbitrary period different in the transfer mode. CONSTITUTION:A bus arbiter 5 arbitrates the bus right of a system data bus 4 between the first bus master 1 and the second bus master 2. A transfer mode mask mechanism 6 masks the transfer of the second bus master 2 to the first bus master 1 in bus transfer which the second bus master 2 executes as a master. When the second bus master 2 becoming a master state by the bus arbiter 5, for example, starts transfer through the system data bus 4, the transfer mask mechanism 6 functioning as a concealing means analyzes the transfer mode of the second bus master 2 and automatically conceals the bus transfer state signal transmitted to the first bus master 1 in the slave state for the arbitrary period different in the transfer mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus system in which a plurality of bus masters and memories are connected via a system bus, and more particularly to a bus controller for controlling data transfer on each system bus by each bus master. Is.

[0002]

2. Description of the Related Art Conventionally, in a device of this type, for example, in a system having tightly coupled bus masters (CPU, DMAC, etc.) and a memory shared by these bus masters, one or more bus masters have a temporary storage area ( Cache) and the cache may be used in write-back mode. At this time, when a bus master having a cache (hereinafter referred to as a bus master 1) accesses the shared memory, if the data exists in the cache (cache hit), the bus master 1 cannot access the memory and is cached. Exchange data between.

If the access at this time is a write, only the cache is updated because the write-back mode is set, and the contents of the memory are not updated to be in a dirty state. In this state, if another bus master (hereinafter referred to as bus master 2) becomes the master and tries to read dirty data, the data must be output from the bus master 1 in the slave state, not from the memory. Therefore, after the bus master 1 transfers the bus right to the bus master 2 and enters the slave state, when the dirty data is read by monitoring the bus, the dirty data owned by the bus master 1 is replaced with the memory. It must have the ability to output.

At this time, the data transfer monitored by the bus master 1 must be in a transfer mode which can be recognized by the bus master 1. Here, the transfer mode is the size of transfer or the like. This is because, if the bus master 1 holds the data requested by this transfer, the data must be internally output instead of the memory, and the transfer mode asserted on the bus can be performed by itself. It is necessary. Therefore, this transfer mode is required to completely match between the bus masters.

[0005]

As described above, in the conventional device, if the bus masters having different transfer modes are attempted to perform the transfer without any contradiction, the transfer mode which can be recognized by the bus master in the slave state monitoring the bus is recognized. It becomes necessary to convert the data to a signal or to make an error response, that is, the bus master in the slave state monitoring the bus exchanges data on behalf of the memory for the access made by the bus master currently in the master state. Even if it is not necessary, there is a problem that the control is complicated because it needs to be performed as long as the bus is monitored.

The present invention has been made in order to solve the above-mentioned problems, and when a bus master cannot recognize some or all modes of the transfer performed by another bus master, the other bus master is transferring the same during transfer. It is an object of the present invention to provide a bus control device capable of consistently executing transfer between bus masters having different transfer modes by apparently masking the transfer cycle.

[0007]

A bus controller according to the present invention analyzes a bus arbiter that arbitrates a bus request of each bus master and a transfer mode of a bus master that is brought into a master state by the bus arbiter, and determines a bus master in a slave state. And a concealment means for automatically concealing a bus transfer status signal sent to the device for an arbitrary period in which the transfer mode is different.

[0008]

According to the present invention, when a bus master placed in the master state by the bus arbiter starts the transfer via the system data bus, the concealment means analyzes the transfer mode of the bus master and sends it to the bus master in the slave state. By automatically hiding the transfer status signal for an arbitrary period in which the transfer modes are different, it is possible to perform transfer between bus masters in different transfer modes without contradiction.

[0009]

FIG. 1 is a block diagram showing an example of a bus controller showing an embodiment of the present invention.

In the figure, 1 is a first bus master, 2 is a second bus master, and 3 is a memory.
Data can be transferred to each other via the data bus 4. A bus arbiter 5 arbitrates the bus right of the system data bus 4 between the first bus master 1 and the second bus master 2. The transfer mode masking mechanism 6 masks the transfer of the second bus master 2 from the first bus master 1 among the bus transfers performed by the second bus master 2 as a master.

In the thus configured bus control device, when the second bus master 2, which is in the master state by the bus arbiter 5, starts a transfer via the system data bus 4, a transfer mask functioning as a concealment means. The mechanism 6 analyzes the transfer mode of the second bus master 2 and automatically conceals the bus transfer status signal sent to the first bus master 1 in the slave state, so that the transfer mode of the transfer mode is changed. Performs transfers between different bus masters consistently.

Hereinafter, referring to FIGS. 2 and 3, the second bus master 2 performs a bus transfer which cannot be recognized by the first bus master 1 from a state in which no one holds the bus right, and then the first bus master 1
An operation of masking the transfer of the second bus master 2 by the first bus master 1 when the bus master 1 performs the transfer will be described. 2 and 3, F1 to F5 indicate the shift phases, and the broken line in FIG. 3 indicates the state in which the bus request is not issued.

In phase F1 shown in FIGS. 2 and 3, bus arbitration is performed as described later.

First, the second bus request 9 from the second bus master 2 is sent to the bus arbiter 5. At this time, since the bus request from the first bus master 1 has not been issued, the bus right is given to the second bus master 2. This is transmitted when the bus permission signal 10 from the bus arbiter 5 to the second bus master 2 becomes valid and the bus permission signal 8 from the bus arbiter 5 to the first bus master 1 becomes invalid.

In the phase F2 shown in FIGS. 2 and 3, the second bus master 2 starts the transfer as described later.

The second bus master, which has obtained the bus right, stops sending the bus request 9 and issues the bus transfer in-progress signal 13 to start the bus transfer. This means that the memory 3 and the transfer mask mechanism 6
Be transmitted to. The transfer mask mechanism 6 judges whether this transfer is in a mode that can be recognized by the first bus master 1, and if it cannot be recognized, masks the transferring signal 12 to the first bus master 1 (issues the transferring signal 12). Do not)

As a result, the first bus master 1 is in phase F.
It enters the slave state from 2 and starts the bus monitoring.
Bus master 2 transfers are masked and not identified. Therefore, the first bus master 1 does not wait for the transfer of the second bus master 2 to be completed, and not to request the bus right,
Requesting bus rights can occur.

On the other hand, when the transfer of the second bus master 2 can be recognized by the first bus master 1, the in-bus transfer signal 13 of the second bus master 2 is not masked and is given as it is to the first bus master 1 as the in-bus transfer signal 12. . In this case, since the first bus master 1 waits for the transfer of the second bus master 2 to be completed and then requests the bus right, no problem occurs.

In the phase F3 shown in FIGS. 2 and 3, the transfer of the second bus master 2 is not completed and the first transfer is completed as described later.
The transfer request of the bus master 1 is output and held.

By the way, the memory 3 indicates in the phase F2 that it is a transfer request to itself by the bus transfer signal 13
Then, the transfer response signal 15 is issued. This is recognized by the current bus master (second bus master 2),
At the time when the predetermined transfer mode is completed (when the transfer is performed three times in the present embodiment: the end of the phase F3), the second bus master 2 finishes the bus transfer, and notifies the bus transfer signal 13 to that effect. By invalidating, the transfer mask mechanism 6 and the bus arbiter 5 are notified. During this phase F3, the bus right is given to the second bus master 2, and the request is reserved by the bus arbiter 5 for the first bus master 1 which issued the bus request.

In the phase F4 shown in FIGS. 2 and 3, the bus right is abandoned as will be described later. Therefore, the bus right is given to the first bus master 1 during this arbitration period, which means that the bus arbiter 5 causes the first bus master 1 to do so. Bus permission signal 8 to
Is valid, and the bus permission signal 10 from the bus arbiter 5 to the second bus master 2 is invalidated.

In the phase F5 shown in FIGS. 2 and 3, the first bus master 1 starts the transfer as will be described later.

After entering the phase F5, the first bus master 1 can start the transfer for the first time, and the bus transferring signal 11 at this time is directly transmitted not only to the bus arbiter 5 and the memory 3 but also to the second bus master 2. This is because the present embodiment assumes that the transfer mode of the first bus master 1 can be completely recognized by the second bus master 2.

As described above, even if the second bus master 2 carries out a transfer which the first bus master 1 cannot recognize,
The transfer-in-progress signal 13 from the second bus master 2 is not directly connected to the transfer-in-progress signal 12 to the first bus master 1, and the transfer mask mechanism 6 is interposed therebetween so that it can be performed consistently. Further, as can be seen from the above description, the transfer mask mechanism 6 may have an extremely simple structure, so that the control configuration of the system is greatly simplified.

In the above embodiment, the first bus master 1
Is a bus transfer that cannot be recognized among the bus transfers performed by the second bus master 2, but the second bus master 2 is set so that it can recognize all the bus transfers performed by the first bus master 1. It can be said that the CPU and the first bus master 1 are assumed to be bus masters having different roles from the DMAC and the like. However, as shown in FIG. Even if there is, since each unrecognized transfer can be masked with respect to the other party, it is possible to support connection between different types of CPUs.

In the above embodiment, the transfer mask mechanism 6 is used.
However, as shown in FIG. 1, the case where they exist as independent blocks has been described. However, a configuration that does not exist as an independent block, for example, a bus control device in which the transfer mask mechanism 6 is incorporated into the bus arbiter 5 as a function is also present. The invention can be easily applied.

[0027]

As described above, according to the present invention, when a bus master placed in the master state by the bus arbiter starts a transfer via the system data bus, the concealment means analyzes the transfer mode of the bus master and determines that the bus master is in the slave state. Since the bus transfer status signal sent to the device is configured to be automatically hidden during an arbitrary period of different transfer modes,
Transfers between bus masters with different transfer modes can be executed without contradiction.

Therefore, it is excellent in that the bus system can be freely expanded or designed with a simple and inexpensive control circuit configuration without being affected by the differences between the plurality of bus masters having different transfer modes. Produce an effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a bus control device showing an embodiment of the present invention.

FIG. 2 is a timing chart explaining the bus arbitration operation of FIG.

3 is a chart illustrating the bus arbitration operation of FIG.

FIG. 4 is a block diagram showing an example of a bus control device showing another embodiment of the present invention.

[Explanation of symbols]

 1 First Bus Master 2 Second Bus Master 3 Memory 4 System Data Bus 5 Bus Arbiter 6 Transfer Mask Mechanism

Claims (1)

[Claims] 1. In a bus system in which a plurality of bus masters having different transfer modes access a memory via a system data bus, a bus arbiter that arbitrates bus requests of each bus master and a transfer mode of a bus master that is in a master state by the bus arbiter. And a concealment means for automatically concealing a bus transfer state signal sent to a bus master in a slave state during an arbitrary period of different transfer modes.