JPH06197378A - Block interleave control system and its circuit - Google Patents

Abstract

PURPOSE:To reduce the number of line memories and the number of control circuits and to facilitate the circuit design when block interleave depending on the picture compression standards such as the JPEG is executed. CONSTITUTION:When picture element data of an original picture element comprising plural color components are subjected to block interleave by using a block comprising the prescribed member of mXn picture elements as one unit, n-sets of picture element data per one line in a prescribed color component order sequentially are read from frame memories 12R, 12G, 12B of each color component in which picture element data of an original picture are written for each color component, n-sets of read picture element data are written in the same line memory 16 sequentially, after the write to the line memory 16 is finished for m-lines, the arrangement of the block formed in a prescribed color component order in the line memory 16 is read as picture element data sequentially in the unit of blocks and transferred as features.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to block interleaving for compressing and coding image data having a plurality of color components, and more particularly to JPEG (Joint Photographic Expent Grou).
p), etc., to a block interleave control system and a circuit for performing block interleaving defined by image data compression coding standards.

[0002]

2. Description of the Related Art In recent years, image media handling color images have become widespread. However, the information amount of a color image is extremely large, and a color image of a predetermined size is color-separated and pixel-separated to obtain three primary colors, for example, R (red), G (green),
If the pixel data is B (blue), all pixel data will be enormous. When pixel data of such a huge amount of data is converted into an image signal, it takes a long time to transmit or store this image signal.

For this reason, image data compression coding (hereinafter simply referred to as "reduction of data to be transmitted" by utilizing the redundancy of image data without reducing the image quality at all or with a slight deterioration that is not visible). Image coding) is performed. At present, various versatile image coding methods capable of highly efficient compression of color images have been proposed. For example, there is a JPEG algorithm as one of the color still image encoding methods.

On the other hand, when the color image data is encoded, the image data of each color component is encoded in a predetermined encoding order. The encoding order in image encoding includes non-interleave for encoding the entire image for each color and pixel interleave and block interleave in which encoding of one pixel and one block for one color component is repeated in a predetermined color component order. Here, in the JPEG encoding method, block interleaving is performed in which one block has 8 × 8 pixels.

By the way, as described above, the color image is
Color separation and pixel separation are performed by a CCD or the like to obtain pixel data of, for example, three primary colors of R, G, and B. These pixel data are once written in the frame memory for each color and then as shown in FIG. By using the conventional block interleave circuit 30, the frame memories 12R, 12 for each color component
Block interleaving of G and 12B pixel data is performed, and a predetermined pixel (typically described as 8 × 8 pixels in the following description) is defined as one block and a JPEG chip (encoding circuit) in a predetermined color component order. 20 and is encoded by a predetermined JPEG algorithm.

In the conventional block interleave circuit 30 shown in FIG. 6, frame memories 12R, 12G and 12 which store pixel data of the entire image of each color component.
From B, the pixel data of the address selected by the frame memory controllers 34R, 34G, and 34B provided for each frame memory are read out, and the line memories 36R, 36G, and 36B for each color are provided with the scans provided for each line memory. Write to the address designated by the conversion circuit (block interleave controller) 38R, 38G, 38B. Thus, as shown in FIG.
In the line memory 36R, 64 blocks of lines are formed with 8 × 8 pixels as one block.

Thereafter, scan conversion circuits 38R, 38G, 3
8B is a line memory 36R, 36G, which is to be read, according to the timing signal from the timing control circuit 40.
By selecting the address of the block in 36B, one block from each of the line memories 36R, 36G, and 36B in a predetermined color component order, for example, R, G, and B in the illustrated example, as shown in FIG.
In this order, data of 64 pixels (= 8 × 8 pixels) is read out and sent to the JPEG chip 20.

[0008]

In the block interleave circuit 30 shown in FIG. 6, line memories 36R, 36G and 36B are provided for each color, and scan conversion circuits 38R, 38G and 38B are provided for each line memory. Since it is provided, there is a problem that the physical quantity of the line memory and the scan conversion circuit (for example, the number of memory chips) increases. Therefore, there is a problem in that the degree of freedom in the physical layout of the circuit design is low.

Further, the line memories 36R, 36G, 36
When the pixel data is transferred from B to JPEG 20, block interleaving must be realized by controlling the read address of the scan conversion circuits 38R, 38G, and 38B, which causes a problem that the circuit becomes complicated.

An object of the present invention is to solve the above-mentioned problems of the prior art and to execute a line of pixel data (R, G, B) in a frame memory in the process of performing block interleaving defined by an image compression standard such as JPEG. (EN) Provided is a block interleave control system and a circuit thereof which can reduce the number of line memories and the number of control circuits and facilitate circuit design by controlling write and read addresses.

[0011]

In order to achieve the above object, the first aspect of the present invention is to set pixel data of an original pixel composed of a plurality of color components into a block of a predetermined number of m × n pixels. When performing block interleaving as a unit, n pieces of pixel data per line are sequentially read out from the frame memory of each color component in which the pixel data of the original image is written for each color component, and read out. N
Write each pixel data to the same line memory sequentially,
After the writing to the line memory is completed for m rows, the pixel data is sequentially read and transferred in block units in the array of blocks formed in the line memory in the predetermined color component order. A block interleave control method is provided. Here, it is preferable that the line memory is composed of two line memories, and while the pixel data is being written in one line memory, the pixel data is read from the other line memory. Further, according to a second aspect of the present invention, pixel data of an original pixel composed of a plurality of color components is converted into a predetermined m ×
A block interleave control circuit for performing block interleaving with a block of n pixels as one unit, and a predetermined read timing in a predetermined color component order from a frame memory of each color component in which pixel data of the original image is written for each color component. And a frame memory controller provided for each frame memory of each color component in order to sequentially control the address of n pixel data per line,
A line memory capable of arranging blocks of m × n pixels in a predetermined number of one row, and n pieces of data read from the frame memory sequentially written in the line memory at a predetermined write timing in the predetermined color component order. Scan conversion for controlling an address of pixel data and an address which is sequentially read out at a predetermined read timing in a block unit in an array of blocks formed in the line memory in the predetermined color component order by this writing and is transferred. And a timing control circuit for controlling the predetermined read timing of the frame memory controller and the predetermined write timing and predetermined read timing of the scan conversion circuit for each color component. It is provided. It is preferable that the line memory is a toggle memory including two line memories and reading the pixel data from the other line memory while writing the pixel data into one line memory.

[0012]

According to the block interleave control method of the present invention, the number of pixels constituting one row of one block is determined in a predetermined color component order from the frame memory of each color component in which pixel data of the entire image of each color component is written. Reading pixel data and writing the same in the same line memory having the number of lines forming one block in the same order is repeated for all the lines forming the block, and the pixel data conforming to the block interleave in the line memory. After the row of the block is formed, it is read and transferred in block units.

In addition, the block interleave control circuit of the present invention is provided with one line memory and one scan conversion circuit for three frame memories in order to realize the above control method. Therefore, the system of the present invention and the circuit of the present invention can simplify the circuit design by reducing the number of line memories and scan conversion circuits.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The block interleave control system and its circuit according to the present invention will be described in detail with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram showing the overall configuration of a block interleave control circuit for implementing the block interleave control system of the present invention. As shown in the figure, the control circuit 10 of the present invention includes a frame memory controller 14R, 14G provided for the frame memories 12R, 12G, 12B, respectively.
And 14B, the line memory 16 to which the outputs of the frame memories 12R, 12G and 12B are connected, the scan conversion circuit 18 provided for the line memory 16, and the frame memory controllers 14R, 14G, 14B and the scan conversion circuit 18. Timing control circuit 2 connected
Has 0 and.

Frame memories 12R, 12G, 12B
For storing the pixel data of the entire image of the three primary colors of red (R), green (G) and blue (B), respectively. In the following description, the frame memories 12R, 12
G and 12B are both memories that store pixel data of 512 × 512 pixels, and a case where one block is composed of 8 × 8 pixels will be described as a representative example, but the present invention is not limited to this. is not.

Frame memory controllers 14R, 14
G and 14B are the frame memories 12R and 1R, respectively.
The address of pixel data to be read out of the pixel data stored in 2G and 12B is controlled. The pixel data of the addresses selected by the controllers 14R, 14G and 14B are read from the frame memories 12R, 12G and 12B at the respective read timings controlled by the timing control circuit 20. As shown in FIG. 2, the line memory 16 is 64 × 3 in units of 8 pixels per line.
(= 192) units, that is, 512 × 3 (= 8 × 64 ×
3 = 1536) pixel data for 8 lines (153
This is a memory that can store 6 × 8 = 12288 pixels). Therefore, the line memory 16 can store pixel data of 8 × 8 pixels in one block of 64 × 3 blocks, that is, 64 blocks of three primary colors (R, G, B). The line memory 16 is a frame memory 12
One line memory common to R, 12G and 12B, or 8 × 15 of the same configuration as shown in FIG.
It may be any of toggle memories including two line memories 16a and 16b capable of storing 36 pixels (8 lines 8 × 64 × 3 pixels, that is, a block of 1 line 8 × 8 pixels is 64 × 3 blocks).

Even if the line memory 16 is a toggle memory, one line memory 16a or 16b is always connected to the frame memories 12R, 12G and 12B, and for three primary colors (R, G, B). Have been standardized. By using the line memory 16 as a toggle memory, only one line memory, 16a in the illustrated example, is used.
When only the pixel data at a predetermined address of the frame memories 12R, 12G and 12B is read out and written in the line memory 16a by connecting only the frame memories 12R, 12G and 12B to the other line memory 16b.
From the JPEG chip (encoding circuit: encoder)
20 and can perform block interleaving. When the writing of 16a to one line memory and the reading of the line memory 16b to the other end, the one line memory 16a to which the writing ends
From the line memory 16b, and writing to the other line memory 16b for which reading has been completed. Thus, efficient block interleaving can be performed.

The scan conversion circuit 18 includes a frame memory 12
The pixel data read from the R, 12G, and 12B are selected and controlled in order to write the pixel data to the line memory 16 in a predetermined color component order, and the pixel data written from the line memory 16 is selected and controlled. The address of the line memory to be read in order to read out the block is controlled and selected.

The relationship between the address of the pixel data written to the line memory 16 controlled by the scan conversion device 18 and the address of the pixel data read from the frame memories 12R, 12G, 12B, and the line memory 16
FIG. 3 shows the addresses of the pixel data read from and transferred. As described above, the line memory 1 shown in FIG.
Reference numeral 6 includes two line memories 16a and 16b. Pixel data is written to the line memory 16a, for example, pixel data is read from the write line memory 16b in the order of color components of R, G, and B in the illustrated example. .

As shown in FIG. 3, first, the frame memory 1 is set in the first block of the first row of the line memory 16a.
Pixel data of 8 pixels in the first row, first block of 2R is written. Next, in the 1st row 2nd block of the line memory 16a, 8 of the 1st row 1st block of the frame memory 12G is provided.
The pixel data of the pixel is stored in the first row, third block of the line memory in the first row, first block of the frame memory 12B.
The pixel data of the pixel is written. After this, the frame memory 12 is again stored in the first row, fourth block of the line memory 16a.
Pixel data of 8 pixels in the first row, second block of R is written.

The frame memories 12R and 12 in this case
FIG. 4 shows the timing of writing pixel data from the G and 12B to the line memory 16a. In this way, R,
G, B, R, G, B ..., R, G, B and pixel data of 64 blocks in the first row of each frame memory 12R, 12G, 12B in the predetermined color component order are stored in the first line memory 16a.
The entire 64 × 3 block of rows is written, completing the first row. Thereafter, each block in the second row of each frame memory 12R, 12G, 12B is written in each block in the second row of the line memory 16a. When the writing of the pixel data up to the eighth row of the line memory 16a is completed in this way, the line memory 16a is formed with a block unit line of the pixel data of the color component as shown in FIG.

Next, as shown in FIG. 2, the line memory 1 in which the pixel data is written in all the memories by the above-mentioned method.
To read pixel data from 6b, first, pixel data of 8 pixels in the first row of the first block of the line memory 16b,
Next, 8 pixels in the second row of the first block, 8 pixels in the third row, and 8 pixels in the third row are completed. After this, the first block 8
The pixel data of x8 pixels is transferred to JPEG22. In the next second block, the data of each 8 pixels from the first row to the eighth row is read out, and the pixel data of the second block of all 8 × 8 pixels is transferred to the JPEG 20. Thus
From the line memory 16b as shown in FIG.
The block interleaving in block units is performed up to the last block of the line memory 16b at the timing of reading the pixel data to and from.

The timing control circuit 20 controls the writing timing of the pixel data from the selected address of the frame memories 12R, 12G, 12B as shown in FIG. 4 to the selected address of the line memory 16 (16a). Together with the line memory 16 as shown in FIG.
This is for controlling the read timing of the pixel data from the selected address of (16b) to the JPEG 22, and the write timing signal to the line memory 16 is used as the frame memory controllers 14R, 14 for each color component.
G, 14B (readout timing) and the scan conversion circuit 18 are input as a drive clock, and the read timing from the line memory 16 is input to the scan conversion circuit 18 as a drive clock.

Here, when the line memory 16 is composed of the toggle memories of the two line memories 16a and 16b, the write timing of the line memory 16a and the read timing of the line memory 16b can be performed at the same timing. , Can perform efficient block interleaving.

The circuit for implementing the block interleave control method of the present invention is basically configured as described above, but the present invention is not limited to the above embodiment, and the size (number of pixels) of the frame memory. , The number of pixels (the number of color components), the number of pixels in one block, the size of the line memory (the number of pixels), etc. can be appropriately selected, and the transfer destination of the block interleave is not limited to the JPEG chip or circuit, and the image encoding can be performed. Any encoding circuit (encoder) that performs the above may be used.

[0027]

As described above in detail, according to the method and circuit of the present invention, in the process of performing block interleaving from the frame memory using the line memory, the physical number of line memories and the scan conversion circuit ( The number of control circuits can be reduced, and as a result, the circuit design can be facilitated.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a circuit that implements a block interleave control method according to the present invention.

FIG. 2 is an explanatory diagram of an embodiment of a line memory used in the present invention.

FIG. 3 is an explanatory diagram illustrating one step of the block interleave control method of the present invention.

FIG. 4 is a time chart showing an example of the writing timing of pixel data from the frame memory to the line memory in the block interleave control system of the present invention.

FIG. 5 is a time chart showing an example of the timing of reading pixel data from a line memory to JPEG in the block interleave control method of the present invention.

FIG. 6 is a configuration block diagram of a conventional block interleave circuit.

FIG. 7 is an explanatory diagram of a line memory used in a conventional block interleave circuit.

FIG. 8 is a time chart showing a timing of reading data from a line memory to JPEG in a conventional block interleave circuit.

[Explanation of symbols]

 10 block interleave control circuit 12R, 12G, 12B frame memory 14R, 14G, 14B frame memory controller 16 line memory 18 scan conversion circuit 20 JPEG chip (encoding circuit)

Claims (4)

[Claims] 1. When performing block interleaving on pixel data of original pixels composed of a plurality of color components in units of a block of a predetermined number of m × n pixels, the pixel data of the original image is written for each color component. From the frame memory of each color component, n pieces of pixel data are sequentially read for one line in a predetermined color component order, the read n pieces of pixel data are sequentially written to the same line memory, and written to this line memory. After completing the above for m rows, the block interleave control method is characterized in that the pixel data is sequentially read and transferred in block units in the array of blocks formed in the line memory in the predetermined color component order. 2. The block according to claim 1, wherein the line memory comprises two line memories, and while the pixel data is being written in one line memory, the pixel data is read from the other line memory. Interleave control method. 3. A block interleave control circuit for performing block interleaving of pixel data of an original pixel composed of a plurality of color components in units of a block of a predetermined number of m × n pixels, wherein the pixel data of the original image is From the frame memory of each color component written for each color component, a frame provided for each frame memory of each color component in order to control the address of n pixel data per line sequentially in a predetermined color component order at a predetermined read timing. Memory controller, mx
A line memory capable of arranging blocks of n pixels in a predetermined number of one row, and n pixel data read from the frame memory sequentially written in the line memory at a predetermined write timing in the predetermined color component order. And a scan conversion circuit for controlling the addresses to be sequentially read and transferred in block units at predetermined read timing in the array of blocks formed in the line memory in the predetermined color component order by this writing. ,
A block interleave control circuit comprising: a timing control circuit for controlling the predetermined read timing of the frame memory controller and the predetermined write timing and predetermined read timing of the scan conversion circuit for each color component. 4. The line memory is a toggle memory including two line memories and reading the pixel data from the other line memory while writing the pixel data into one line memory. The block interleave control circuit described in.