JP2665387B2 - Image data storage device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image data storage device, and more particularly, to an image data storage device using a DRAM as a frame memory for temporarily storing image data of a scene image to be recorded.

2. Description of the Related Art For example, a digital electronic still camera is an image capturing apparatus that captures an image of an object scene using a solid-state imaging device such as a CCD, and finally stores an image signal representing the captured image in a memory in the form of digital data. As a memory, for example, a memory card in the form of a memory card mounted with a RAM, such as a semiconductor memory, is often used. In that case, data compression such as orthogonal transform coding is often performed in order to efficiently use the storage area of the memory.

In particular, two-dimensional orthogonal transform coding is widely used because it can perform coding at a large compression rate and can suppress image distortion due to coding.

By the way, in a digital electronic still camera, it is wise to use a DRAM (Dynamic RAM) when cost is important as a memory (frame memory) for temporarily storing image data indicating an object scene to be recorded. It is.

However, when accessing the DRAM in connection with the image data processing, the image data required for setting the row (ROW) address, precharging the electric charge to the capacitor of each memory cell performed in a predetermined cycle, etc. due to the configuration of the DRAM. Actually cannot be output.

On the other hand, in a digital electronic still camera, for the sake of image processing (such as two-dimensional orthogonal transformation) performed after image data is read from a frame memory, image data is transmitted from the frame memory to a subsequent image processing circuit. It is desirable to output continuously in units of blocks constituting the conversion.

Object The present invention has been made in view of such circumstances, and image data can be continuously read from a memory in which image data for one screen of a scene to be recorded is temporarily stored. It is an object to provide an image data storage device.

DISCLOSURE OF THE INVENTION According to the present invention, an image data storage device comprises: a first storage unit for storing image data corresponding to pixels in an even column of a pixel group forming one screen of an object scene; A second storage unit for storing image data corresponding to the odd-numbered pixels of the pixel group forming one screen, and a timing for reading image data stored in the first and second storage units; Control means for simultaneously reading image data corresponding to two adjacent pixel rows on the screen from the first and second storage means, and transferring image data corresponding to one pixel row to the other. These image data are successively read out by shifting the readout timing by the readout time of the image data corresponding to the number of pixels with respect to the image data corresponding to the pixel column.

DESCRIPTION OF THE EMBODIMENTS Next, an embodiment of an image data storage device according to the present invention will be described in detail with reference to the accompanying drawings.

In the digital electronic still camera to which the image data storage device according to the present invention is applied, a screen (corresponding to an imaging surface of an imaging device) 50 showing a scene image to be recorded as shown in FIG. From the frame memory in which image data for one screen is stored in advance.
Image data is read out in units of 52. This block 52
Consists of, for example, eight pixels in the horizontal (H) direction and eight pixels in the vertical (V) direction, for a total of 64 pixels. Pixel row that constitutes screen 50
Even-numbered pixel columns (l ₀ , l ₂ , ...) among l ₀ , l ₁ , l ₂ , ...
Is written to the memory A (FIG. 8A).

Further, image data corresponding to each pixel belonging to an odd-numbered pixel column (l ₁ , l ₃ ,...) Among the above-mentioned pixel columns constituting the screen 50 is written to the memory B (FIG. 8B). As described above, in the present invention, a frame memory is configured by the memories A and B in which image data is written. And, for example, pixel rows l ₀ and l ₁
The image data memory A that belongs, the number of image data to be output than the image data belonging to the pixel row l ₁ to the image data belonging to a pixel row l ₀ via the read buffer memory at the same time as the B (for each pixel column) , The image data belonging to the pixel rows l ₀ and l ₁ are continuously read. Similarly, by sequentially reading the image data of two adjacent pixel columns on the screen from the memories A and B, the image data can be continuously output in units of blocks 52.

Next, a specific operation example of reading image data from the memories A and B constituting the frame memory in units of blocks 52 will be described with reference to FIGS. 9 and 10. FIG. It is assumed that the memory map of the frame memory matches the pixel arrangement of the imaging device (for example, CCD) as shown in FIG. In the figure, the X direction indicates a row (ROW) address, and the Y direction indicates a column (COLUMN) address.

On the other hand, the memory A has row addresses of 0, 2, 4,.
Image data belonging to address 2n (corresponding to an even-numbered pixel column on the screen), and a low address in memory B is 1,3,5, ... 2n + 1 (corresponding to an odd-numbered pixel column on the screen) Has been written.

Control signals ▲ falling at times t ₀ and t ₁ respectively
▼ (ROW ADDRESS STROBE) (A), ▲ ▼
When (B) is input to the memories A and B, the row addresses R ₀ and R ₁ are latched in the memories A and B by these control signals (FIGS. 10 (b), (c) and (a). )). Next, the control signal ▲ falling at time t ₂ , t ₃ ,..., T ₉
▼ (COLUMN ADDRESS STROBE), the column addresses C ₀ , C ₁ ,..., C ₇ are latched in the memories A and B.
FIG. 10 (d)). As a result, the image data D ₀₀ ,
D ₀₁ , D ₀₂ ,..., D ₀₇ are image data D ₁₀ , D
_{11, D 12, ......, D} 17 are read out simultaneously, respectively (10
Figures (e) and (f)). Further, the image data D ₁₀ read from the memory B of the image data read out from the frame _{memory, D 11, D 12, ......} , D 17 is the memory A by the memory controller including a buffer memory (not shown) image data D ₀₀ to be read _{from, D 01, D 02, ......} , is delayed by the time required to read the D ₀₇ image data _{D 00, D 01, D 02} , ...
.., And are continuously output following _D07 . Therefore, the subsequent image processing circuits such as the two-dimensional orthogonal transform unit from the memory controller,
Image data D ₀₀ , D ₀₁ ,..., D ₀₇ , D of two adjacent pixel columns
_10, D _11, ......, so that the D ₁₇ is continuously output. The results followed the same output as the image data as described above also row address R ₂ to R ₇ are performed, the image data of one block (64 pixels) is continuously output.

In this way, image data is continuously output from the frame memory via the memory controller in block units.

 What has been described above is the basic concept of the present invention.

FIG. 1 shows the configuration of an embodiment of a digital electronic still camera to which the present invention is applied. In this figure, the camera has an image pickup device 12, which picks up an image of an object scene and compresses and encodes an image signal representing the image in the form of digital data by an orthogonal transform unit 28 and an encoding unit 26. ,
This is a device that stores data in the memory card 40.

For the imaging device 12, for example, a solid-state imaging device such as a CCD is advantageously applied, and an imaging field is photographed by the imaging lens 10,
A color image signal representing the object scene is, for example, red (R),
The imaging device outputs green (G) and blue (B) color component signals. This color component signal is output in the same raster scanning format as the TV signal. Other functional units such as an exposure mechanism and a focusing mechanism required for photographing are not directly related to the understanding of the present invention, and thus description thereof is omitted. The memory card 40 is, for example, RA
This is a storage device in which a semiconductor memory device such as M is carried on a card-shaped base, and is detachably mounted on the device.

The output of the imaging device 12 is connected to an analog-to-digital converter (AD) 14, which is a signal conversion circuit that converts an input analog image signal into corresponding digital data and outputs it. This digital data is quantized to, for example, 8 bits for each of the color component signals RGB. This digital data output is sent to the signal processing unit 16
It is connected to the.

In this embodiment, the signal processing unit 16 converts pre-processing such as white balance adjustment and gradation correction, and converts color component signal data into a luminance signal (Y) and a two-phase color difference signal (RY, BY). And a signal processing for applying the luminance and color difference processing to the image data.

The output of the signal processing unit 16 is connected to the memory controller 18. The memory controller 18 is connected to the frame memory 24, and outputs the frame memory 24 from the signal processing unit 16.
And reading from the frame memory 24 is controlled. The image signal output from the imaging device 12 is in the form of a normal raster scanning sequential signal. The memory controller 18 blocks image data. That is, as shown in FIG. 2, a screen 50 of one frame represented by an image signal is divided into a plurality of regions of a predetermined size, that is, blocks 52, and image data is read out for each block 52.

Each block 52 may have a size of, for example, 8 pixels in the horizontal scanning (H) direction and 8 pixels in the vertical scanning (V) direction, or may have a different number of pixels in the vertical and horizontal directions. The image data read in units of the blocks 52 is sent from its output to the encoding unit 26 and the orthogonal transform encoding unit 28.

The image data of each block read from the frame memory 24 by the memory controller 18 is sent to the encoding unit 26, and the activity is calculated. After that, the data is again sent to the orthogonal transform unit 28 for each block and subjected to orthogonal transform, and then sent to the encoding unit 26 and encoded.

The orthogonal transformation unit 28 has a function of performing orthogonal transformation on image data input from the memory controller 18 in units of blocks and outputting the result. As the orthogonal transform, for example, a two-dimensional discrete cosine transform (DCT) is advantageously applied.
As a result, the image data of each block 52 is
Is converted into data in the frequency domain every time, and the data is arranged from the lower frequency in the horizontal (H) direction and the vertical (V) direction of the screen 50.

The image data for each block subjected to the two-dimensional orthogonal transformation in the orthogonal transformation unit 28 is arranged vertically and horizontally, low-order data is arranged in the upper left part, and becomes higher-order data in the lower right direction. DC component data is arranged at the upper left. The output of the orthogonal transform unit 28 is sent to the encoding unit 26.

The encoding unit 26 normalizes the image data subjected to the two-dimensional orthogonal transformation, that is, the transform coefficients, in the orthogonal transformation unit 28, after performing coefficient truncation. The coefficient truncation is to compare the orthogonally transformed transform coefficient with a predetermined threshold value and to cut off a portion below the threshold value. In the normalization, the transform coefficient after the coefficient truncation is divided by a predetermined quantization step value, that is, a normalization coefficient α, and quantization is performed using the normalization coefficient α.

The normalization coefficient α is set according to the total activity of the image data, that is, the total value of the activities. The setting of the normalization coefficient α is performed using the equation α = K1 · (total activity) + K2. However, K1 and K2 are fixed length parameters.

The encoding unit 26 encodes a DC component of data for each block input from the memory controller 18 and an AC component of data for each block input from the orthogonal transform unit 28. The amount of encoded data output from the encoding unit 26 is
Limited by activity of each block. That is, the output of the encoded data of each block is limited according to the ratio of the activity of each block to the total activity obtained by summing the activities of each block,
Perform fixed length.

The orthogonal transform unit 28 and the encoding unit 26 perform various types of compression encoding by inputting various parameters from the control unit 20, and are formed by, for example, one IC chip.

The output of the encoding unit 26 is sent to the memory card 40 via a connector (not shown). Memory card 40 is, for example, SRA
A storage device in which a semiconductor memory device such as an M or an EEPROM is carried on a card-shaped base, and is detachably mounted on the device. The parameter setting unit 30 outputs a luminance signal Y, a color difference signal Cr (RY), and a color difference signal Cb (B-B) for color image data.
The parameters necessary for the compression encoding for each Y) are set and output to the encoding unit 26.

An input operation unit 22 is connected to the parameter setting unit 30, and an instruction for setting various parameters used for compression coding is input from the input operation unit 22. The parameter setting unit 30 selects a desired parameter from parameters stored in a storage unit (not shown) according to an instruction from the input operation unit 22, and outputs the selected parameter to the encoding unit 26.

The control unit 20 is a control unit that controls the entire apparatus, and outputs a standby signal or an active signal to the orthogonal transform unit 28 and the encoding unit 26, in particular. Also frame memory
A control signal for controlling the reading of the image data from 24 is output to the memory controller 18.

Next, the configurations of the memory controller 18 and the frame memory 24 in FIG. 1 are shown in FIGS. 3 and 4, respectively.
In FIG. 3, the memory controller 18 includes a control unit 60,
It has a data selector 62, a delay circuit 64, and a selector 66.

The control unit 60 stores ▲ ▼, ▲ in the frame memory 24.
▼, ▲ ▼ (WRITE ENABLE), ▲ ▼ (OUTPUT E
NABLE) and address data.

The data selector 62 selectively outputs image data of a plurality of types, for example, three types of image data A, B, and C read from the frame memory 24. Data selector 62 is 2
One of the two image data is output directly to the selector 66, and the other is output to the selector 66 via the delay circuit 64. Here, the data A, B, and C are a luminance signal Y or a chrominance signal Cr (or a chrominance signal Cr) read from three memories A, B, and C constituting a frame memory 24 in which image data for one screen is stored as described later. Cb) shows the image data.

The two types of image data output from the data selector 62 relate to the same type of video signal of mutually adjacent pixel columns in a pixel group forming one screen of the object scene.

The delay circuit 64 delays the output of the image data by the time required to read the image data of eight pixels.

The selector 66 alternately switches image data output from the data selector 62 directly or via the delay circuit 64 for every eight pixels, and outputs the image data to the encoding unit 26 and the orthogonal transformation unit 28.

As shown in FIG. 4, the frame memory 24 includes a memory A including a memory A (I) 70 and a memory A (II) 72, a memory B including a memory B (I) 74, a memory B (II) 76, and a memory B. The memory C includes a C (I) 78 and a memory C (II) 80.

As the imaging device 12, for example, the height and width of the imaging surface are 48
In order to store image data for one screen of a color image in capturing an object scene using a CCD having 8 × 768 pixels, the data amount is a luminance signal (Y) and a color difference signal (Cr, Cb). Cr: Cb
= 4: 2: 2, so if the DRAM has a storage capacity of 1 Mbit, 6
Required. Therefore, in this embodiment, the frame memory
24 is a memory A (I) 70, A (II) 72, B (I) 74, B
(II) 76, C (I) 78 and C (II) 80, each of which comprises six DRAMs (the memory capacity of each memory is 1 Mbit).

Next, the contents of the image data stored in the memories A and C are shown in FIGS. 5A and 5B, respectively. In these figures, data Yij and Cij represent image data of a luminance signal and a chrominance signal of an i-th row and a j-th column which constitute one screen, respectively.
The image data Cij whose j is an even number outputs the color difference signal Cr,
Odd numbers indicate the color difference signals Cb.

Now, in FIG. 3, the operation of reading image data from the frame memory 24 by the memory controller 18 is described in FIG.
This will be described with reference to the drawings. Here, as an example of the operation, a case where the image data stored in the memories A and C is output from the data selector 62 will be described. In FIG. 6, the control signal ▲ ▼ falling at times t ₀ and t ₁ .
When (A) and (C) are input to the frame memory 24 from the control unit 60 in the memory controller 18, these control signals (A) and (C) cause the memories A and C respectively. The row addresses R ₀ and R ₁ input from the control unit 60 are latched (FIG. 6A,
(B), (c)). Then the time t _2, t ₃ ......, falls control signal at t ₉ ▲ ▼ by the memory A, the column address C ₀ which is input from the control unit 60 in _{C, C 1, ......, C} 7
Are latched (FIGS. 6D and 6C). As a result,
From memory A, image data Y ₀₀ , Y ₀₁ ,..., Y ₀₇ of the luminance signal in the pixel row of the 0th row on the screen, and from memory C, image data of the luminance signal in the pixel row of the 1st row on the screen Y
_{10, Y 11, ......, Y} 17 , respectively, are read simultaneously (FIG. 6 (e), (f)) .

On the other hand, of the image data read from the frame memory, the image data Y of the luminance signal read from the memory A
_{00, Y 01, ......, Y} 07 is directly from the data selector 62, the selector 66, also the image data Y _10, Y ₁₁ of the brightness signals read out from the memory C, ......, Y ₁₇ by the delay circuit 64 The data is output to the selector 66 after being delayed by the reading time of the image data for eight pixels. Therefore, the image data read simultaneously from the memories A and C from the selector 66 is Y ₀₀ , Y ₀₁ ,.
.., Y ₀₇ , Y ₁₀ , Y ₁₁ ,..., Y ₁₇
6. Output to the orthogonal transform unit 28. Similarly, for the row addresses 2 to 7, the image data of the luminance signal is read from the memories A and C, and the image data of one block is read. By performing such operations continuously, image data is read in block units.

Next, when the image data of the color difference signal is read, the control signals falling to the frame memories C and A from the control unit 60 at times t ₀ and t ₁ respectively are control signals ▲ ▼ (C) and ▲ ▼.
(A) is output (not shown). Further control signal ▲
▼ (FIG. 6 (d)), the column addresses C ₀ , C ₁ ,..., C ₇ are latched in the memories C, A. As a result, the memory C
Image data C _00, C _01, from ......, C ₀₇ is the image data C ₁₀ from the memory _{A, C 11, ......, C} 17 are read out at the same time, respectively. In this way, the image data C ₀₀ , C
_{01, ......, C 07, C} 10, C 11, ......, C 17 is continuously output.
In this way, similarly to the case of the image data of the luminance signal, the image data of the color difference signal is finally
26, output to the orthogonal transform unit 28.

In the present embodiment, for convenience of explanation, the frame memory 24
Although only the case where image data is read from the memories A and C has been described, the same applies to other cases.

Effect As described above, according to the present invention, a DRAM is used as a frame memory for temporarily storing image data for one screen of a scene to be recorded, and this frame memory is accessed multiple times to make it seem apparently. , The image data is read at twice the ratio, so that the image data can be continuously output even though there is a time when the image data cannot be actually output due to the configuration of the DRAM. .

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of a digital electronic still camera to which an image data storage device according to the present invention is applied, and FIG. 2 is an explanation showing an example of a block configuration of a screen in the embodiment shown in FIG. FIG. 3, FIG. 3 is a block diagram showing a configuration of a memory controller in FIG. 1, FIG. 4 is a block diagram showing a configuration of a frame memory in FIG. 1, and FIGS. 5A and 5B are memories constituting a frame memory.
FIG. 6 is an explanatory diagram showing storage contents of image data in A and C. FIG. 6 is a timing chart showing an image data reading operation of a memory controller. FIG. 7 is a block diagram showing a screen showing an object scene image to be stored. FIGS. 8A and 8B are explanatory diagrams showing a state in which image data of a block screen area is stored in two memories, and FIG. 9 is a diagram showing image data stored in a frame memory. FIG. 10 is a timing chart showing an operation state of each unit when reading image data from the frame memory. Explanation of Signs of Main Parts 12 Imaging Device 18 Memory Controller 24 Frame Memory 26 Encoding Unit 28 Orthogonal Transformation Unit 30 Parameter Setting Unit 40 Memory Card 26 Encoding Unit 60 ... Control unit 62 ... Data selector 64 ... Delay circuit 66 ... Selector

Claims (1)

(57) [Claims] 1. A first storage means for storing image data corresponding to pixels in an even column of a pixel group forming one screen, and a pixel in an odd column of the pixel group forming one screen. A screen is divided into a plurality of blocks, and the blocks are defined by a plurality of predetermined pixels in a horizontal direction and a predetermined number of pixels in a vertical direction of the one screen. And a third storage unit that stores image data of a pixel row of a block from the first or second storage unit; and the first, second, and third storage units. And control means for controlling the read timing of the image data stored in the block. The control means corresponds to two adjacent pixel columns of a block on a screen from the first and second storage means. Reading the image data simultaneously, The image data corresponding to one of the pixel rows stored in the storage means is read out at a read timing shifted from the image data corresponding to the other pixel row by the read time of the image data corresponding to the number of pixels. Image data storage device.