JPH06196547A - Metal film deposition device and metal film deposition method - Google Patents

Abstract

PURPOSE:To eliminate a process which etches and thereby exposes a specified alignment film used to form a mask pattern on a metal film out of alignment marks. CONSTITUTION:An exclusively designed alignment chip C2 is formed on a semiconductor board S or in an area which is partially lacking of the peripheral edge of a production chip C1 and the semiconductor board S. Contact holes 50A and 50B and alignment marks 52A and 52B are formed on the product chip C1 and the exclusively designed alignment chip C2. A metal wiring material is deposited on the semiconductor board S in the state that the exclusively designed alignment chip C1 is covered with an alignment mark covering part of a board holder, thereby forming a metal film 60 on the semiconductor board S. A mask pattern is formed on the metal film 60 with the alignment mark 52B of the exclusively designed alignment chip C1 where no metal film 60 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal film deposition method and a metal film deposition apparatus used in the method, and more particularly to depositing a metal film over a semiconductor substrate having contact holes and alignment marks. The present invention relates to a metal film deposition method and apparatus.

[0002]

2. Description of the Related Art In a semiconductor device in which a lower layer metal wiring is formed on a semiconductor substrate via an insulating film or in a semiconductor device in which an upper layer metal wiring is formed on a lower layer metal wiring via an interlayer insulating film, The active region on the semiconductor substrate and the lower metal wiring or the lower metal wiring and the upper metal wiring are connected by the metal material deposited in the contact hole formed in the insulating film or the interlayer insulating film. . Then, when the metal film is formed into a metal wiring by etching using the metal wiring forming mask, the alignment mark formed at the same time as the contact hole in the insulating film or the interlayer insulating film and the metal wiring forming mask are aligned. By doing so, the positional accuracy of the contact hole and the metal wiring is secured.

The alignment mark formed on the insulating film or the interlayer insulating film is optically recognized because the unevenness of the alignment mark remains even if the metal wiring material is deposited in the contact hole by the usual sputtering method. It is possible to do so.

By the way, since the aspect ratio of the contact hole is increasing with the progress of higher integration and higher density of the semiconductor device, when the metal wiring material is deposited in the contact hole by the usual sputtering method, the contact is reduced. The thickness of the metal film at the bottom of the hole becomes very thin. Therefore, there is a problem that the contact resistance varies greatly and the reliability of the contact decreases.

Therefore, recently, as shown in JP-A-63-24054 and JP-A-64-11966, the temperature of the semiconductor substrate is kept high when the metal wiring material is deposited by sputtering. A high temperature sputtering method has been proposed in which a metal wiring material deposited on a semiconductor substrate is caused to flow into the contact hole to reliably fill the contact hole with the metal wiring material.

[0006]

The above-mentioned high temperature sputtering method has an advantage that the metal wiring material is surely buried in the contact hole and the metal film is flattened. Since the metal wiring material is also embedded in the alignment mark formed on the film and the unevenness of the alignment mark is flattened, it becomes impossible to optically recognize the alignment mark. Therefore, when forming the wiring forming mask on the metal film, there is a problem that the alignment mark formed on the insulating film or the interlayer insulating film cannot be aligned with the wiring forming mask.

Therefore, by partially etching the metal film formed on the insulating film or the interlayer insulating film, a predetermined alignment mark used when forming a mask for forming a metal wiring is selected from the alignment marks. A step of exposing is required.

In view of the above, the present invention employs a metal film deposition method such as a high temperature sputtering method in which an alignment mark is filled with a metal wiring material, but the alignment mark is placed on the metal film. It is an object of the present invention to eliminate the step of exposing a predetermined alignment mark used for forming a mask pattern by etching.

[0009]

In order to achieve the above-mentioned object, the invention of claim 1 is a predetermined one used for forming a mask pattern on a metal film among alignment marks formed on a semiconductor substrate. The alignment mark is covered in advance.

Specifically, a solution means taken by the invention of claim 1 is a substrate holding means for holding a semiconductor substrate, and a peripheral edge covering means for covering a peripheral edge of the semiconductor substrate held by the substrate holding means, Metal film forming means for forming a metal film on the semiconductor substrate by depositing a metal wiring material on the semiconductor substrate which is held by the substrate holding means and whose peripheral portion is covered by the peripheral portion covering means. Based on the above metal film deposition apparatus, the peripheral edge covering means is covered with a predetermined alignment mark, which is used when forming a mask pattern on the metal film, among the alignment marks formed on the semiconductor substrate. The alignment mark covering means is provided.

According to a second aspect of the invention, in the structure of the first aspect, the position of the orientation flat formed on the semiconductor substrate is detected, and the position of the predetermined alignment mark is determined based on the detected position of the orientation flat. The configuration further includes a substrate position control unit that moves the semiconductor substrate so as to correspond to the position of the alignment mark covering unit.

According to the invention of claim 3, in addition to the structure of claim 1 or 2, the peripheral edge covering means is provided integrally with the substrate holding means.

The invention of claim 4 adds the structure of the metal film forming means to a sputtering means to the structure of claims 1 to 3, and the invention of claim 5 relates to the invention of claim 1.
To the configuration of the above-mentioned metal film forming means is a CVD means, and the invention of claim 6 is such that the metal wiring material is an aluminum-based metal. is there.

The invention of claim 7 is the same solution principle as the invention of claim 1, and specifically, the solution means taken by the invention of claim 7 is to form an alignment mark on a semiconductor substrate at the same time as a contact hole. The metal film deposition method is premised on a metal film deposition method including an alignment mark formation step and a metal film formation step of forming a metal film on the semiconductor substrate by depositing a metal wiring material on the semiconductor substrate. Includes a step of forming the metal film in a state where a predetermined alignment mark used in forming a mask pattern on the metal film among the alignment marks on the semiconductor substrate is covered by an alignment mark covering means. It is a structure that.

According to an eighth aspect of the present invention, in the structure of the seventh aspect, the metal film forming step is formed on the semiconductor substrate before the step of covering the predetermined alignment mark with an alignment mark covering means. The position of the orientation flat is detected, and the semiconductor substrate is moved so that the position of the predetermined alignment mark corresponds to the position of the alignment mark covering means based on the detected position of the orientation flat. Is added.

According to a ninth aspect of the present invention, in the structure according to the seventh or eighth aspect, a part of the semiconductor film is formed in the metal film forming step before the step of covering the predetermined alignment mark with an alignment mark covering means. In addition, a configuration is added in which there is a step of setting an alignment mark formed on the chip missing from the peripheral edge of the above-mentioned predetermined alignment mark.

According to a tenth aspect of the present invention, the metal film forming step is a step of forming a metal film on the semiconductor substrate by a sputtering method in addition to the structures of the seventh to ninth aspects. The invention of claim 11 is,
In addition to the constitution of 9, the metal film forming step is a step of forming a metal film on the semiconductor substrate by a CVD method.
In addition to the constitution of 11, the constitution that the metal wiring material is an aluminum-based metal is added.

[0018]

According to the structure of claim 1, the peripheral edge covering means includes:
Among the alignment marks formed on the semiconductor substrate, alignment mark covering means for covering a predetermined alignment mark used when forming the mask pattern on the metal film is provided, and therefore the alignment mark covering means is used to When a metal wiring material is deposited on a semiconductor substrate to form a metal film on the semiconductor substrate with a predetermined alignment mark covered, the metal wiring material is embedded in the contact hole on the semiconductor substrate. No metal wiring material is embedded in the alignment mark.

According to the structure of claim 2, the position of the orientation flat formed on the semiconductor substrate is detected, and the position of the predetermined alignment mark corresponds to the position of the alignment mark covering means based on the detected position of the orientation flat. As described above, since the substrate position control means for moving the semiconductor substrate is provided, the position of the alignment mark covering means and the position of the predetermined alignment mark can be reliably aligned.

According to the structure of claim 3, since the peripheral edge covering means is integrally provided with the substrate holding means, the work of holding the semiconductor substrate and coating the peripheral edge of the semiconductor substrate can be easily performed. .

According to the structure of claim 4, when the metal film is formed on the semiconductor substrate by the sputtering means, the metal wiring material is not embedded in the predetermined alignment mark.

According to the structure of claim 5, when the metal film is formed on the semiconductor substrate by the CVD means, the metal wiring material is not embedded in the predetermined alignment mark.

According to the structure of claim 6, even when the aluminum-based metal having excellent fluidity is used as the metal wiring material, the metal wiring material is not embedded in the predetermined alignment mark.

According to the structure of claim 7, in the metal film forming step of forming a metal film on a semiconductor substrate, a predetermined alignment mark used for forming a mask pattern on the metal film among the alignment marks on the semiconductor substrate. Is covered with the alignment mark covering means, and the metal wiring material is deposited on the semiconductor substrate in a state where the predetermined alignment marks are covered by the alignment mark covering means. The metal wiring material is embedded, but the metal wiring material is not embedded in the predetermined alignment mark.

According to the structure of claim 8, in the metal film forming step of forming a metal film on the semiconductor substrate, the position of the orientation flat formed on the semiconductor substrate is detected,
Since there is a step of moving the semiconductor substrate so that the position of the predetermined alignment mark corresponds to the position of the alignment mark covering means based on the detected position of the orientation flat, the position of the alignment mark covering means and the predetermined position The position of the alignment mark can be surely aligned.

According to the structure of claim 9, in the metal film forming step of forming a metal film on a semiconductor substrate, an alignment mark formed on a chip, a part of which is missing from a peripheral portion of the semiconductor substrate, is used for the predetermined alignment. A chip, which has a step of setting a mark and cannot be used as a product because a part thereof is cut off from the peripheral portion of the semiconductor substrate, can be used for alignment.

According to the structure of the tenth aspect, when the metal film is formed on the semiconductor substrate by the sputtering means, the metal wiring material is not embedded in the predetermined alignment mark.

According to the eleventh aspect, when the metal film is formed on the semiconductor substrate by the CVD means, the metal wiring material is not embedded in the predetermined alignment mark.

According to the structure of claim 12, even when an aluminum-based metal having excellent fluidity is used as the metal wiring material, the metal wiring material is not embedded in the predetermined alignment mark.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall structure of a metal film deposition apparatus according to an embodiment of the present invention. The semiconductor substrate S stored in the cassette box 10 is taken out from the cassette box 10 by the first robot 12, and then the substrate position is controlled by the substrate position control means 14. The control of the substrate position performed by the substrate position control means 14 will be described later.

The semiconductor substrate S whose substrate position is controlled by the substrate position control means 14 is transferred to the load lock chamber 16 by the first robot 12. The semiconductor substrate S transferred to the load-lock chamber 16 is cooled down in the load-lock chamber 16 if it has already been heated, and the load-lock chamber 16 if heat-treated in the next step.
Is preheated at. The semiconductor substrate S that has been cooled down or preheated in the load lock chamber 16 is
The second robot 18 transfers the load lock chamber 16 to a process module 20 in which sputtering or CVD is performed.

FIG. 2 shows a sputtering apparatus for performing sputtering in the process module 20. A heater element 26 is held in the apparatus main body 22 via an insulator 24, a heater block 28 is provided in the heater element 26, and the heater element 26 and the heater block 28 constitute a substrate holding means. The semiconductor substrate S has a spring clip 30 integrally provided on the heater element 26 as a peripheral edge covering means and the heater block 28.
It is grasped by. In FIG. 2, 32 is a cathode as a target and 34 is an anode. The argon gas as the discharge gas introduced into the vacuum is turned into plasma by the cathode 32 and the anode 34, and the argon ions 34 in the plasma collide with the target surface on the cathode 32, so that the target atoms are repelled. The cathode 32, the anode 34, and the introduced discharge gas described above constitute a metal film forming means.

FIG. 3 shows a modification of the sputtering apparatus. A support base 36 is provided on the apparatus main body 22, and a pin member 38 is provided on the support base 36 so as to be movable back and forth. The support base 36 and the pin member 38 constitute a substrate holding means. The pin member 38 is normally housed in the support base 36, and the semiconductor substrate S is mounted on the support base 36.
When mounting the semiconductor substrate or removing the semiconductor substrate S from the support base 36, a robot (not shown) moves the semiconductor substrate S
The semiconductor substrate S is pushed up by advancing from the support base 36 so that it can be easily gripped. A ring-shaped substrate holder 40 as a peripheral portion covering means is provided in the apparatus main body 22 so as to be movable up and down. When the substrate holder 40 moves downward, the semiconductor substrate S is gripped by the substrate holder 40 and the support base 36. At the same time, the peripheral portion of the semiconductor substrate S is covered by the substrate holder 40.

FIG. 4 shows a CVD apparatus for performing CVD in the process module 20. Device body 2
2 is provided with a support base 3 as a holding means via a heat insulator 42.
6 is provided and the support 36 is heated by the heater element 26. The peripheral edge of the semiconductor substrate S mounted and supported on the support base 36 is covered by a ring-shaped substrate holder 40 as peripheral edge covering means. A vacuum passage 44 is provided in the central portion of the apparatus main body 22 and the support base 36, and the inside of the chamber is brought into a vacuum state by drawing a vacuum through the vacuum passage 44. Support base 36
A shower head 46 is provided above the above, and the reaction gas is supplied from the shower head 46 to the surface of the semiconductor substrate S. In this case, in order to prevent the reaction gas from reaching the peripheral portion of the semiconductor substrate S, the inert gas supplied from the inert gas passage 48 provided in the support base 36 is used as the support base 3.
It is supplied to the peripheral portion of the semiconductor substrate S from between 6 and the substrate holder 40.

FIG. 5 is an exposure map showing the arrangement of the product chip C1 and the alignment-specific chip C2 formed on the semiconductor substrate S, and FIG. 6 is an enlarged schematic view of a part thereof. In the conventional alignment method, since the alignment mark is not invisible, several chips of the product chip C1 are used for alignment, but in the present embodiment, four chips in the peripheral portion of the semiconductor substrate S are used. Four chips arranged in places and a part of which is cut off from the peripheral portion are set as the alignment dedicated chip C2. That is, since the semiconductor substrate S has a circular shape and the chip has a quadrangular shape, the peripheral portion of the semiconductor substrate S has a function of the product chip C1 because a part of the chip is missing even when exposed. Since a chip that cannot be fulfilled is generated, the chip is used as the alignment dedicated chip C2. To reduce the exposure time,
In many cases, the chip lacking a portion in this way is not exposed, but in the present embodiment, exposure is performed in order to use such a chip as the alignment dedicated chip C2.

For exposure in the recent photo process, a method of exposing each chip as shown in the exposure map of FIG. 5 by using an exposure apparatus having a positioning function is adopted. At this time, all the chips C1 and C2 have the same pattern, and the contact holes 50A and 5 are formed in the same pattern.
0B and alignment marks 52A and 52B are provided. The size of the contact holes 50A, 50B is usually about 1 μm, and the alignment marks 52A, 5B
The size of 2B is about 10 μm, but the reduced scale is ignored in FIG. 6 for convenience of illustration.

The alignment of the pattern in the photo step is performed using the alignment marks provided on each chip, but normally, the alignment marks of all the chips on the semiconductor substrate S are not used, but the X and Y directions are used. The alignment of all the chips can be performed using the exposure apparatus based on some alignment marks for determining the position of, and when the alignment marks are the smallest, four alignment marks. The present invention utilizes the fact that the alignment marks of all the chips on the semiconductor substrate S are not used for alignment in the photo process, and uses only the alignment marks 52B of the alignment-specific chip C2.

FIG. 7 shows a planar structure of an example of the substrate holder 40 used in the above-described metal film deposition apparatus.
As shown in FIG. 7, the substrate holder 40 includes a semiconductor substrate S
In addition to having a shape for covering the peripheral edge of the semiconductor substrate S, it also has an alignment mark covering portion 54 protruding toward the central portion of the semiconductor substrate S so as to cover the alignment-specific chip C2. The alignment mark covering portion 54 of the substrate holder 40 should have a slight allowance in consideration of the wraparound of a metal film such as an aluminum film formed on the semiconductor substrate S and the positional deviation between the substrate holder 40 and the alignment mark 52. Keep it.

Here, the control of the substrate position performed by the above-mentioned substrate position control means 16 will be described. The substrate position control unit 16 detects the position of the orientation flat 56 (see FIG. 5) formed on the semiconductor substrate S, and based on the detected position of the orientation flat 56, the alignment mark of the alignment-specific chip C2. The semiconductor substrate S is rotationally moved so that the position of 52 corresponds to the position of the alignment mark covering portion 54.

A method of depositing a metal film on the semiconductor substrate S using the above metal film deposition apparatus will be described below.

8 (a) to 8 (c) are cross-sectional views showing respective steps in the metal film deposition method, and FIGS. 8 (a) to 8 (c).
In FIG. 6, the cross-sectional structure taken along the line II and II- in FIG.
The cross-sectional structure along line II is shown for comparison.

First, as shown in FIG. 8A, the product chip C1 and the alignment-specific chip C2 on the semiconductor substrate S.
The contact hole 50A, 50B and the alignment mark 52A, 52B are formed on the insulating film 58 formed on the
Are formed at the same time.

Next, as shown in FIG. 8B, with the alignment mark covering portion 54 of the substrate holder 40 covering the alignment-dedicated chip C2, a well-known metal film deposition such as a high temperature sputtering method or a CVD method is performed. By depositing a metal wiring material such as aluminum on the semiconductor substrate S using the method, as shown in FIG.
A flattened metal film 60 made of aluminum is formed thereon.

Next, although not shown, the metal film 60
After a resist is applied on the above to form a resist film, a mask pattern for wiring the metal film 60 is formed on the resist film. In this case, the alignment-specific chip C2
The wiring mask is aligned using the alignment mark 52B. It is not necessary to form a mask pattern on the alignment-specific chip C2. Next, the metal film 60 is etched using the above mask pattern to form metal wiring.

With the above arrangement, the contact hole 50A and the alignment mark 50A of the product chip C1.
A metal wiring material is embedded in the contact hole 50B and the alignment mark 52B of the alignment-specific chip C2, but the metal wiring material is not embedded therein. Therefore, the step of exposing the alignment mark for aligning the wiring mask is not necessary, and the number of steps can be reduced, and the flattened metal wiring material is used for the contact hole 52A of the product chip C1. Since the contact can be surely buried, there is little variation and a highly reliable contact can be obtained.

In the above embodiment, the alignment mark coating portion 54 of the substrate holder 40 covers the entire alignment-dedicated chip C2, but the shape of the alignment mark coating portion 54 is aligned with the alignment-dedicated chip C2. Only the alignment mark 52B to be used may be covered. Further, in the above-mentioned embodiment, the alignment mark is provided inside the chip, but the position where the alignment mark is provided is not limited and is usually 100.
It may be provided on a scribe line having a width of about μm. In this case, as a matter of course, the alignment mark covering portion 54 provided on the substrate holder 40 does not cover the chip but covers the scribe line provided with the alignment mark.

Further, in the above embodiment, the dedicated alignment chips C2 are provided at four locations on the peripheral edge of the semiconductor substrate S. However, when the diameter of the semiconductor chip is large, the dedicated alignment chips C2 are provided on the semiconductor substrate S. The peripheral portion may be provided at 6 or 8 places. Further, in the above embodiment, the alignment mark covering portion 54 covers the alignment-dedicated chip C2, but instead of this, the product chip C1 is wasted, but the alignment mark covering portion 54 is the product chip C2.
1 may be coated.

Further, in the above embodiment, the alignment mark is provided on the insulating film on the semiconductor substrate, but when forming the wiring pattern of the upper layer wiring, the alignment mark is formed between the lower layer wiring and the upper layer wiring layer. It is provided in the interlayer insulating film between them.

Further, the metal wiring material is not limited to aluminum, but may be tungsten or titanium.

[0051]

As described above, according to the metal film deposition apparatus of the first aspect of the present invention, the masking pattern is formed on the metal film of the alignment marks formed on the semiconductor substrate in the peripheral edge covering means. Since the alignment mark covering means for covering the predetermined alignment mark used when forming is provided, the metal wiring material is deposited on the semiconductor substrate while the predetermined alignment mark is covered by the alignment mark covering means. When the metal film is formed on the semiconductor substrate, the metal wiring material is not embedded in the predetermined alignment mark. Therefore, even if the metal film forming method that surely fills the contact hole is adopted, the predetermined alignment An etching process for exposing the mark is unnecessary.

Therefore, according to the first aspect of the present invention, it is possible to obtain a highly reliable contact that does not vary and does not complicate the process.

According to the second aspect of the present invention, the position of the orientation flat formed on the semiconductor substrate is detected, and the position of the predetermined alignment mark is aligned based on the detected position of the orientation flat. Since the substrate position control means for moving the semiconductor substrate corresponding to the position of the mark covering means is provided, the position of the alignment mark covering means can be reliably aligned with the position of the predetermined alignment mark.

According to the metal film depositing apparatus of the third aspect of the present invention, since the peripheral edge covering means is provided integrally with the substrate holding means, the work of holding the semiconductor substrate and covering the peripheral edge of the semiconductor substrate is performed. Can be performed easily.

According to the metal film deposition apparatus of the fourth aspect of the present invention, since the metal film forming means is the sputtering means, the predetermined alignment mark is etched when the metal film is formed on the semiconductor substrate by the sputtering means. The step of exposing can be omitted.

According to the metal film deposition apparatus of the fifth aspect of the present invention, the metal film forming means is the CVD means.
When the metal film is formed on the semiconductor substrate by the means, the step of exposing the predetermined alignment mark by etching can be omitted.

According to the metal film deposition apparatus of the sixth aspect of the present invention, since the metal wiring material is an aluminum-based metal,
Even when an aluminum-based metal having excellent fluidity is used as the metal wiring material, the step of exposing the predetermined alignment mark by etching can be omitted.

According to the metal film depositing method of the present invention, in the metal film forming step, a predetermined alignment mark used for forming the mask pattern on the metal film is aligned among the alignment marks on the semiconductor substrate. There is a step of covering with the mark covering means, and the metal wiring material is deposited on the semiconductor substrate in a state where the predetermined alignment mark is covered with the alignment mark covering means. However, since the metal wiring material is not embedded in the predetermined alignment mark, even if a metal film forming method that surely fills the contact hole is adopted, the predetermined alignment mark is exposed. Eliminating the etching process.

Therefore, according to the invention of claim 7, it is possible to obtain a highly reliable contact with no variations without inviting a complicated process.

According to the metal film depositing method of the eighth aspect of the present invention, the metal film forming step detects the position of the orientation flat formed on the semiconductor substrate, and based on the detected position of the orientation flat, the above predetermined position is detected. Since there is a step of moving the semiconductor substrate so that the position of the alignment mark corresponds to the position of the alignment mark covering means, the position of the alignment mark covering means can be reliably aligned with the position of the predetermined alignment mark. .

According to the metal film depositing method of the ninth aspect of the present invention, the metal film forming step of forming the metal film on the semiconductor substrate is performed on a chip, a portion of which is missing from the peripheral edge of the semiconductor substrate. There is a step of setting the alignment mark to the above-mentioned predetermined alignment mark, and a chip that cannot be used as a product because a part is missing from the peripheral portion of the semiconductor substrate can be used for alignment. A chip in which the predetermined alignment mark is covered by the alignment mark covering means cannot be commercialized because a metal film is not formed, but the alignment chip is used as a product because a part thereof is missing from the peripheral portion of the semiconductor substrate. Since it is a chip that cannot be done, the chip is not wasted.

According to the metal film deposition method of the tenth aspect of the present invention, since the metal film forming step is a step of forming a metal film on the semiconductor substrate by the sputtering method, the metal film is formed on the semiconductor substrate by the sputtering method. In this case, the step of exposing the predetermined alignment mark by etching can be omitted.

According to the metal film deposition method of the eleventh aspect of the present invention, since the metal film forming step is a step of forming a metal film on the semiconductor substrate by the CVD method, the metal film is formed on the semiconductor substrate by the CVD method. In this case, the step of exposing the predetermined alignment mark by etching can be omitted.

According to the metal film depositing method of the eleventh aspect of the present invention, the metal wiring material is not embedded in the predetermined alignment mark when the metal film is formed on the semiconductor substrate by the CVD means.

According to the metal film deposition method of the twelfth aspect of the present invention, since the metal wiring material is an aluminum-based metal, even when an aluminum-based metal having excellent fluidity is used as the metal wiring material, the above-mentioned predetermined alignment mark It is possible to omit the step of exposing the film by etching.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing the overall configuration of a metal film deposition apparatus according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a sputtering device as the metal film deposition device.

FIG. 3 is a cross-sectional view showing a modified example of the substrate holding means and the peripheral edge covering means in the sputtering apparatus.

FIG. 4 is a sectional view showing a CVD apparatus as the metal film deposition apparatus.

FIG. 5 is an exposure map showing the arrangement of product chips and alignment-specific chips formed on a semiconductor substrate.

FIG. 6 is a schematic partial enlarged view of the exposure map.

FIG. 7 is a plan view of a substrate holder used in the metal film deposition apparatus.

8 is a cross-sectional view taken along line I-I and line II-II in FIG.

[Description of Symbols] S Semiconductor Chip C1 Chip for Product C2 Chip for Positioning 14 Board Control Means 20 Process Module 22 Device Main Body 26 Heater Element 28 Heater Block 30 Spring Clip 32 Cathode 34 Anode 36 Support Base 38 Pin Member 40 Substrate Holder 46 Shower head 50A, 50B Contact hole 52A, 52B Alignment mark 54 Alignment mark covering part 56 Orientation flat 58 Insulating film 60 Metal film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhiko Hashimoto 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (12)

[Claims] 1. A substrate holding means for holding a semiconductor substrate,
Peripheral portion covering means for covering the peripheral portion of the semiconductor substrate held by the substrate holding means, and metal wiring on the semiconductor substrate held by the substrate holding means and covered by the peripheral edge covering means. A metal film deposition apparatus comprising: a metal film forming means for depositing a material to form a metal film on the semiconductor substrate, wherein the peripheral edge covering means is provided with an alignment mark formed on the semiconductor substrate. An apparatus for depositing a metal film, characterized in that an alignment mark coating means for coating a predetermined alignment mark used when forming a mask pattern on the metal film is provided. 2. The position of an orientation flat formed on a semiconductor substrate is detected, and the position of the predetermined alignment mark corresponds to the position of the alignment mark covering means based on the detected position of the orientation flat. The metal film deposition apparatus according to claim 1, further comprising substrate position control means for moving the substrate. 3. The metal film deposition apparatus according to claim 1, wherein the peripheral edge coating means is provided integrally with the substrate holding means. 4. The metal film depositing apparatus according to claim 1, wherein the metal film forming means is a sputtering means. 5. The metal film depositing apparatus according to claim 1, wherein the metal film forming means is a CVD means. 6. The metal film deposition apparatus according to claim 1, wherein the metal wiring material is an aluminum-based metal. 7. An alignment mark forming step of forming an alignment mark at the same time as a contact hole on a semiconductor substrate, and a metal film forming process of forming a metal film on the semiconductor substrate by depositing a metal wiring material on the semiconductor substrate. A metal film deposition method comprising: a step of forming a predetermined alignment mark used when forming a mask pattern on the metal film among the alignment marks on the semiconductor substrate. A method of depositing a metal film, comprising a step of forming the metal film in a state of being covered by a covering means. 8. The metal film forming step detects a position of an orientation flat formed on the semiconductor substrate and detects the detected orientation flat before the step of covering the predetermined alignment mark with an alignment mark covering means. 8. The metal according to claim 7, further comprising a step of moving the semiconductor substrate so that the position of the predetermined alignment mark corresponds to the position of the alignment mark covering means based on the position of the station flat. Film deposition method. 9. The metal film forming step is formed on a chip, a portion of which is missing from the peripheral edge of the semiconductor substrate, before the step of covering the predetermined alignment mark with an alignment mark covering means. 9. The metal film deposition method according to claim 7, further comprising a step of setting an alignment mark to the predetermined alignment mark. 10. The metal film deposition method according to claim 7, wherein the metal film formation step is a step of forming a metal film on the semiconductor substrate by a sputtering method. . 11. The metal film depositing apparatus according to claim 7, wherein the metal film forming step is a step of forming a metal film on the semiconductor substrate by a CVD method. . 12. The metal wiring material according to claim 7, wherein the metal wiring material is an aluminum-based metal.
Item 7. The method for depositing a metal film according to item. A method of manufacturing a semiconductor, comprising: