JPH0619429A - Active matrix type liquid crystal display device - Google Patents

Abstract

PURPOSE:To suppress a drop in the voltage of an image signal held in a liquid crystal pixel. CONSTITUTION:The active matrix type liquid crystal display device is equipped with liquid crystal pixels LC which are arrayed in a matrix shape, transistors(TR) for driving the individual liquid crystal pixels LC, and signal lines 2 which supply image signals to the liquid crystal pixels LC through the TRs. A gate pulse VG which places the TR in a selected state is varied in height according to the potential of the image signal supplied to the signal line 2. In concrete, the image signal is inverted in polarity on the basis of a counter electrode potential to make the height of the gate pulse VG lower when the image signal which is lower in level than the counter electrode potential is written in the liquid crystal pixel LC than when the image signal which is higher in level is written.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device in which liquid crystal pixels arranged in a matrix and thin film transistors for driving the individual liquid crystal pixels are integrally formed. More specifically, the present invention relates to a gate pulse application method for line-sequentially selecting drive transistors.

[0002]

2. Description of the Related Art To clarify the background of the present invention, FIG.
The circuit configuration of the conventional active matrix type liquid crystal display device will be briefly described with reference to FIG. The active matrix type liquid crystal display device includes a plurality of gate lines 10 which are orthogonal to each other.
One and a plurality of signal lines 102 are provided. Liquid crystal pixels LC and drive transistors Tr are arranged in a matrix at each intersection. Further, an auxiliary capacitance Cs is also connected in parallel with the liquid crystal pixel LC. The gate electrode of the drive transistor Tr is connected to the corresponding gate line 101,
The drain electrode is connected to the corresponding signal line 102, and the source electrode is connected to the pixel electrode forming one end of the liquid crystal pixel LC. The other end of the pixel electrode LC is commonly connected to the counter electrode.

A plurality of gate lines 101 are connected to a vertical shift register 103 and supply a gate pulse V _G in a line sequential manner. On the other hand, the plurality of signal lines 102 are supplied with image signals corresponding to the three primary colors of R, G, and B via the switching transistor SW. Each switching transistor SW is driven by the horizontal shift register 104.

The image signal supplied to the signal line 102 is 1
The charges are sequentially written into each liquid crystal pixel LC according to the gate pulse V _G that is generated one by one in each horizontal period (1H). The charges written in the liquid crystal pixels are held for one field period until the same gate pulse is generated in the next field and the next signal charges are written. The image signal supplied in the next field is inverted with respect to the potential of the counter electrode in order to AC drive the liquid crystal pixel LC. This AC drive is generally performed in order to suppress deterioration of the life of the liquid crystal.

[0005]

The signal potential actually held in the liquid crystal pixel LC is different from the potential of the image signal supplied to the signal line 102 due to various factors, and includes an error. . One of the major error factors is the drive transistor Tr that occurs when the gate pulse falls.
Is a voltage drop due to capacitive coupling or coupling between the gate region and the channel region. The amount of voltage drop due to this coupling largely depends on the amount of change in the gate pulse under the condition where the channel region of the drive transistor is in the conductive state. This dependency will be briefly described with reference to FIG. The signal line potential is inverted with respect to the counter electrode potential for each field, and is at high level VsigA in a certain field and low level VsigA in the next field.
in sigB. Focusing on one liquid crystal pixel, the gate pulse V _G is applied at time A, and the high-level image signal VsigA with respect to the counter electrode potential is written to the liquid crystal pixel. When the gate pulse V _G falls, the drive transistor becomes non-conductive only when the pulse drops to a level higher than the signal line potential VsigA by the threshold voltage Vth of the drive transistor. Thus, the pixel potential under the channel conduction state of the driving transistor, (V _G -
VsigA-Vth) with a coupling according to Δ
The voltage drops by V _G (A).

On the other hand, at the time point B after one field period, the low-level image signal Vs with respect to the potential of the counter electrode.
Write igB. When the gate pulse V _G falls,
The pixel potential in the field (V _G -VsigB-V
The voltage drop by ΔV _G (B) with a coupling according to th).

The difference between the potential of the signal line and the height of the gate pulse greatly differs between field inversion and non-inversion. Therefore, if V _G is constant, the voltage drop amount of the pixel potential due to the coupling becomes large in the field where the image signal has a negative polarity, resulting in imbalance. At the same time, the variation in the amount of pixel potential drop between individual liquid crystal pixels also increases, and as a result, the variation in pixel potential between pixels also increases. Such a pixel-to-pixel variation in pixel potential appears as subtle luminance unevenness when the liquid crystal display device is displayed in halftone, and there is a problem that display quality is significantly impaired.

[0008]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, an object of the present invention is to suppress the voltage drop of the pixel potential, which becomes particularly remarkable when the polarity of the image signal is inverted, to prevent the uneven brightness. To do. The following measures have been taken in order to achieve this object. That is, the present invention includes, as basic components, liquid crystal pixels arranged in a matrix, transistors for driving the individual liquid crystal pixels, and signal lines for supplying image signals to the liquid crystal pixels via the transistors. The present invention is applied to an active matrix type liquid crystal display device provided. As a feature of the present invention, the height of the gate pulse for selecting the drive transistor is changed according to the potential of the image signal supplied to the signal line. Specifically, when alternating-current driving of the liquid crystal pixel is performed and the polarity of the image signal is inverted with the counter electrode potential as a reference, the high level of the gate pulse when the low level image signal is supplied to the liquid crystal pixel with respect to the counter electrode potential Is set lower than when a high level image signal is supplied. For example, when 1-field inversion is performed, the height of the gate pulse is made different between the first field in which a positive potential is applied and the second field in which a negative potential is applied in one frame of the image signal. Alternatively,
When one horizontal cycle inversion is performed, the height of the gate pulse is made different in correspondence with the polarity inversion of the image signal for each horizontal scanning.

[0009]

According to the present invention, the height of the gate pulse is set to a relatively small value when the image signal that is at a low level with respect to the potential of the counter electrode is written in the liquid crystal pixel, and the coupling is performed at the falling edge of the gate pulse. The amount of pixel potential drop is reduced to suppress variations in pixel potential.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic circuit diagram showing one embodiment of an active matrix type liquid crystal display device according to the present invention, and particularly relates to a one-field inversion drive system. As shown in the figure, this device includes a plurality of gate lines 1 and a plurality of signal lines 2 which are orthogonal to each other. At each intersection, liquid crystal pixels LC and drive transistors Tr are arranged in a matrix. An auxiliary capacitance Cs is connected in parallel with the liquid crystal pixel LC. The gate electrode of the driving transistor Tr is connected to the corresponding gate line 1, the drain electrode is connected to the corresponding signal line 2, and the source electrode is connected to the pixel electrode forming one end of the corresponding liquid crystal pixel LC. ing. The other end of the liquid crystal pixel LC is commonly connected to the counter electrode.

The plurality of gate lines 1 are connected to the vertical shift register 3 and are line-sequentially applied with a gate pulse V _G. On the other hand, the plurality of signal lines 2 are switching elements S
The image signals of the three primary colors of R, G and B are supplied via W. The conduction of the switching element SW is controlled by the horizontal shift register 4.

In the present embodiment, so-called 1-field inversion driving is performed, and the image signal has a high-level polarity with respect to the potential of the counter electrode in the n-field, and the next n + 1.
In the field, it has a low level polarity with respect to the counter electrode potential. On the other hand, the height of the gate pulse output from the vertical shift register 3 is controlled according to the polarity inversion of the image signal for each field. For example, the gate pulse V _G is set to be relatively high in the n field to which the positive image signal is supplied, and the gate pulse having a relatively low height in the next n + 1 field to which the negative image signal is supplied. V _G is supplied.

The operation of the active matrix type liquid crystal display device shown in FIG. 1 will be described in detail with reference to FIG. As described above, the signal line potential is field-inverted, for example, n
In the field, Vsig has a positive polarity with respect to the counter electrode potential.
In the next n + 1 field, the voltage becomes VsigB, which has a negative polarity with respect to the counter electrode potential. Focusing on one liquid crystal pixel, a relatively high gate pulse V _G (A) is applied at a specific time point A in the n field, and the positive image signal VsigA is sampled. When this gate pulse V _G (A) falls, a voltage drop ΔV _G (A) is generated by attaching a coupling of V _G (A) -VsigA-Vth as in the conventional case. Although the amount of voltage drop is about the same as the conventional voltage drop, the amount of change is small when driving in the positive polarity, so that it does not actually cause uneven brightness.

On the other hand, at time B after one field period, the gate pulse V _G (B) is applied to the same liquid crystal pixel, and the negative image signal VsigB is sampled. When the gate pulse V _G (B) falls, V _G
(B) -VsigB-Vth coupling is added to cause a voltage drop ΔV _G (B). As is clear from comparison with the conventional example shown in FIG. 8, the gate pulse V _G (B) is set to be low, and the difference from the pixel potential held in the liquid crystal pixel is small. Therefore, the voltage drop amount based on the coupling capacitance generated between the gate region and the channel region of the drive transistor is remarkably reduced as compared with the conventional case.

FIG. 3 shows the vertical shift register 3 shown in FIG.
Represents a specific configuration example of As illustrated, the vertical shift register 3 has a structure in which D-type flip-flops 14 are connected in multiple stages. Individual flip-flop 14
Includes a pair of inverters 15 and 16 whose outputs are commonly connected. Each inverter is connected to the power supply line VVDD side via a P-type MIS transistor 17 and connected to the ground side GND via an N-type MIS transistor 18. These transistors 17,
Reference numeral 18 operates in response to the vertical clock signals VCK1 and VCK2 and their inverted clock signals to form a so-called clocked inverter. The input terminal of the third inverter 19 is connected to the commonly connected output terminals of the pair of inverters 15 and 16. The output terminal of the third inverter 19 is connected to one input terminal of the NAND gate circuit 20 and also to the input terminal of the flip-flop of the next stage. The output terminal of the preceding flip-flop is connected to the other input terminal of the NAND gate circuit 20. An inverter 21 is connected to the output terminal of the NAND gate circuit 20. When the start signal VST is input to the first-stage flip-flop of the vertical shift register 3, the gate pulse V _G is sequentially output for each horizontal period (1H) for each stage.

A pair of dividing resistors R1 and R2 connected in series between the power supply line VVDD and the ground line GND are added to the vertical shift register 3. A transistor 24 for switching the power supply level is inserted between the resistor connected in series and the ground line GND. A control signal CTL synchronized with polarity reversal for each field is applied to the gate electrode of the transistor 24. In the field of positive polarity driving, the switching transistor 24 is in the non-conducting state, the power supply voltage VVDD is directly applied to the vertical shift register 3, and the gate pulse V
_G is a high level pulse corresponding to the power supply voltage. On the other hand, in the field that drives negative polarity,
The switching transistor 24 becomes conductive and the resistor R
A power supply voltage divided by the ratio of 1 and R2 is applied to the vertical shift register 3. In response to this, the height of the gate pulse V _G also decreases.

FIG. 4 is a schematic circuit diagram showing a second embodiment of an active matrix type liquid crystal display device according to the present invention, which is a so-called 1H inversion drive system. In addition,
Basically, it has the same configuration as the embodiment shown in FIG.
Corresponding parts are designated by corresponding reference numerals to facilitate understanding. In this example, the image signal is inverted every horizontal period. For example, in the n field, the image signal assigned to the first gate line during one horizontal period becomes high level, and the image signal assigned to the next second gate line during horizontal period becomes low level with respect to the counter electrode potential. .
In this way, the image signal is inverted every horizontal period. Similarly, in the (n + 1) th field, it is inverted every horizontal period. However, unlike the n field, in the (n + 1) th field, the image signal is held in the negative polarity during the horizontal period assigned to the first gate line. On the contrary, the image signal becomes high level during the horizontal period assigned to the second gate line. In this way, polarity reversal is performed for each field. The 1-horizontal period inversion drive has an advantage in that flicker can be suppressed as compared with the 1-field inversion drive described above.

On the other hand, the vertical shift register 3 adjusts the height of the gate pulse V _G in response to the one horizontal period inversion drive described above. For example, in the n field, a high level gate pulse is applied to the first gate line, a low level gate pulse is applied to the second gate line, and a high level gate pulse is applied to the third gate line. Apply. In this way, the height of the gate pulse is changed line by line. In the next n + 1 fields, the height of the gate pulse is similarly changed for each gate line. However, focusing on one gate line, for example, the first gate line,
A high level gate pulse is applied in the n field, and a low level gate pulse is applied in the n + 1 field. The vertical shift register 3 performing such an operation can be obtained, for example, in the same manner as the specific circuit configuration shown in FIG. That is, a signal synchronized with one horizontal cycle inversion may be supplied as the control signal CTL of the switching transistor 24 shown in FIG.

FIG. 5 shows the third embodiment of the active matrix type liquid crystal display device according to the present invention, and shows the case of one horizontal period inversion drive. The structure is basically the same as that of the embodiment shown in FIG. 4, and corresponding parts are designated by corresponding reference numbers or reference numerals to facilitate understanding. The difference from the embodiment shown in FIG. 4 is that a first vertical shift register 31 for outputting a high level gate pulse and a second vertical shift register 32 for outputting a low level gate pulse are used. One end of each gate line 1 is connected to a first vertical shift register driven by a high-level power supply voltage V _H via a transistor switch 33, and the other end is connected to a low-level power supply voltage via another transistor switch 34. It is connected to a second vertical shift register 32 driven by _VL . The gate electrodes of the plurality of transistor switches 33, which are respectively connected to one ends of the respective gate lines 1, are connected to a common control line and receive the control signal FRP. On the other hand, the gate electrodes of the other group of transistor switches 34 are connected to another common control line, and receive an inverted signal of the control signal FRP.

Finally, the operation of the active matrix type liquid crystal display device shown in FIG. 5 will be described in detail with reference to the timing chart of FIG. As described above, the image signal is inverted every horizontal period in each field with reference to the counter electrode potential. The voltage level of the control signal FRP is also switched alternately in synchronization with this one horizontal cycle inversion. For example, focusing on the first gate line, in the n-th field, the first control signal pulse FRP becomes high level, so that the transistor switch 33 on the first vertical shift register 31 side becomes conductive and the gate having the height of V _H. A pulse is output. For the next second gate line, the control signal FRP switches to the low level, so that the transistor switch 33 on the first vertical shift register 31 side becomes non-conductive while the transistor switch 34 on the second vertical shift register side. Becomes conductive in synchronization with the inverted signal of the control signal FRP, and a gate pulse having a height of V _L is output. Further, in the next n + 1 field, the phase relationship of the control signal FRP is inverted, so that a gate pulse having a height of V _L is supplied to the first gate line and V _H of the second gate line is supplied. A gate pulse having a height is provided.

[0021]

As described above, according to the present invention, in the active matrix type liquid crystal display device, when the signal charge is supplied from the signal line to the liquid crystal pixel through the driving transistor, the polarity of the signal line potential is reversed. Accordingly, the height of the gate pulse is changed at any time to control the difference between the potential of the image signal supplied and the potential of the gate pulse to the necessary minimum. With this configuration, the voltage drop of the pixel potential caused by the falling edge of the gate pulse can be suppressed to the minimum. Therefore, it is possible to suppress the pixel potential variation between the liquid crystal pixels,
In particular, there is an effect that it is possible to improve luminance unevenness in halftone display.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an active matrix type liquid crystal display device according to the present invention.

FIG. 2 is an operation explanatory diagram of the embodiment shown in FIG.

FIG. 3 is a schematic diagram showing a specific circuit configuration example of a vertical shift register included in the embodiment shown in FIG.

FIG. 4 is a circuit diagram showing a second embodiment of an active matrix type liquid crystal display device according to the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of an active matrix type liquid crystal display device according to the present invention.

FIG. 6 is a timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 7 is a circuit diagram showing an example of a conventional active matrix type liquid crystal display device.

FIG. 8 is a schematic diagram for explaining a problem of a conventional active matrix type liquid crystal display device.

[Explanation of symbols]

 1 gate line 2 signal line 3 vertical shift register 4 horizontal shift register LC liquid crystal pixel Tr drive transistor SW switching element Cs auxiliary capacitance

Claims (4)

[Claims] 1. Liquid crystal pixels arranged in a matrix,
In an active matrix liquid crystal display device including a transistor for driving each liquid crystal pixel and a signal line for supplying an image signal to the liquid crystal pixel through the transistor, a potential of an image signal supplied to the signal line An active matrix type liquid crystal display device characterized in that the height of a gate pulse for selecting a transistor is changed according to the above. 2. One frame of an image signal includes a first field for applying a positive potential and a second field for applying a negative potential.
2. The active matrix type liquid crystal display device according to claim 1, further comprising a field, wherein the height of the gate pulse is different between the first field and the second field. 3. The active matrix type liquid crystal display device according to claim 1, wherein the height of the gate pulse is changed in response to the polarity reversal of the image signal for each horizontal scanning or every several horizontal scanning. 4. The polarity of the image signal is inverted with reference to the counter electrode potential, and the height of the gate pulse when supplying a low level image signal to the liquid crystal pixel with respect to the counter electrode potential is the high level image. 2. The active matrix type liquid crystal display device according to claim 1, wherein the voltage is lower than that when a signal is supplied.