JPH06189336A - Video signal reproduction device and video signal recorder - Google Patents

Abstract

PURPOSE:To obtain the video signal reproduction device and the video signal recorder which process video signals such as CHSV and HDTV or the like accurately in a short time. CONSTITUTION:At first, a color difference signal in a field A of the CHSV is frozen in memories 22, 23. In this case, data of a VIT (Vertical Internal Test) in an R-Y signal are inputted to a CPU 105 and an address M1 at which the data of the VIT signal in the R-Y signal are maximized is held in a CPU 105. Then a signal of a field B is reproduced and the CPU 105 detects an address M2 at which the data of the VIT signal in the R-Y signal are maximized. An HD phase shifter 101 controls the phase of a horizontal direction address reset signal in the memories 22, 23 in response to the value M1-M2 and a color difference signal of a field B having no timewise deviation from the field A is frozen in the memories 22, 23. Since deviation of picture elements between lines is eliminated in this way, blur or ringing or the like in the picture is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal reproducing apparatus and a recording apparatus such as an electronic still camera.

[0002]

2. Description of the Related Art Image information of an image pickup device having a number of pixels of approximately 1300 (horizontal) × 1000 (vertical) is offset-sampled, the image information is recorded on four tracks on a video floppy, and is reproduced on an image memory. The same pixel information data as at the time of recording is constructed again, and after interpolation processing, HDTV
So-called CHSV (Compatible High Definition Television) that obtains high-definition images as high as (High Definition Television)
ll Vidio) method has already been applied by the applicant.

Next, an example of a conventional CHSV will be described. For convenience of description later, similar examples will be sequentially described as Conventional Example 1 to Conventional Example 5.

(Conventional Example 1) For example, Y is shown in FIG. 7A for a luminance signal from a CCD (image pickup device) having a color filter array as shown in FIG. 6 and having a pixel number of 1300 (horizontal) × 1000 (vertical). ), A ₁ , A ₂ , A
_3, the line and B ₁ of ......, B _2, B _3, simultaneously read information signals ...... line in the first field period,
Within the next field period, the lines C ₁ , C ₂ , C ₃ , ... And D ₁ , D ₂ , D ₃ ,.

The color signal is shown in FIG. 7 (b) C _B (B-
Y) and (c) C _R (R−Y) is read as sample information. In this case, the band of the color signal is set to ⅛ of the luminance signal Y, so that a value thinned out every 16 pixels is transmitted in the horizontal direction.

FIG. 8 shows a recording pattern on the video floppy.

Here, the luminance FM (Y-F) which is the recording signal
M) and color difference FM (C-FM) signals are set to frequency allocation according to the SV format, and B, D
Since the 1 / 2H sync signal is offset on the tracks, compatibility with the conventional device can be maintained by reproducing the B and D tracks with the frame head.

FIG. 9 is a circuit configuration block diagram of a camera having such a CCD. The CCD 50 has a filter array as shown in FIG. 6, and outputs the pixel information of each of Y, B, and R by the sampling clock from the SSG 51. A ₁ , A ₂ , A shown in FIG.
_{3, ......, D 1, D} 2, D 3, ...... of the signal is Y ₁ signal processing circuit _{52, B 1, B 2,} B 3, ......, C 1, C 2,
The signals C ₃ , ... Are the Y ₂ signal processing circuit 53, the B signals are the B signal processing circuit 54, and the R signals are the R signal processing circuit 5.
At 5, the processes such as γ correction and white balance are performed. Reference numerals 56 and 57 are adders for producing BY color signals.

The Y ₁ and Y ₂ signals are added to V by adders 58 and 59.
IT (Vertical Interval Test) or HIT (Hori
zontal Interval Test) pulse is added. This pulse serves as a phase reference when sampling the pixels shown in FIG. 7, and is also used for checking the distortion of the transmission path, correcting the Y, _{CR / B} time difference, and the like.

The Y ₁ and Y ₂ signals are fed to the LPF 60,
Bandwidth is limited by 61, and C-SYNC is performed by adders 62 and 63.
(Composite synchronization signal) is added.

On the other hand, the color difference signals B-Y ₁ and R-Y ₂ are band-limited by the band-limiting filters 64 and 65, respectively,
VIT or H as well as Y signal by adders 66 and 67
The IT pulse is added to the sample hold circuits 68, 6
9, the sampling is performed so as to obtain the sample patterns of C _B and C _R shown in FIG. And switch S
_After line sequentialization is performed with ₁ and S ₂ and the transmission band is limited with LPFs 70 and 71, pre-emphasis is applied with pre-emphasis circuits 72 and 73, and FM modulators 74 and 75 are provided.
After being FM-modulated by, the signal is input to adders 76 and 77. The Y ₁ and Y ₂ signals that have passed through the pre-emphasis circuits 78 and 79 and the FM modulators 80 and 81 are input to the adders 76 and 77.

The pilot signals output from the SSG 51 are further input to the adders 76 and 77. This pilot signal serves as a reference for time-axis fluctuations that occur in the disc rotation system during recording and reproduction.

Y-FM mixed by adders 76 and 77,
The C-FM and pilot signals are transmitted to the recording amplifier 82,
It is amplified to an appropriate recording current at 83 and video floppy 84
The magnetic heads 85 and 86 make one rotation (1 / 60s
In step ec), the A and B tracks shown in FIG. 8 are formed, and then the magnetic head moves two tracks to similarly form the D and C tracks.

Next, a reproducing apparatus for reproducing the video signal thus recorded will be described.

FIG. 10 is a circuit configuration block diagram thereof.
The reproducing magnetic head 1 first contacts the A track shown in FIG. 8 to reproduce the video signal recorded on the A track.

First, the Y signal will be described. From the RF signal amplified to an appropriate level by the regenerative amplifier 2, HP
The Y-FM signal separated from the C-FM signal by F3 is
The signal is demodulated by the FM demodulator 4, the high-frequency component is suppressed by the de-emphasis circuit 5, and the original baseband signal is restored. The sync signal is separated by the sync separation circuit 6, and the Y signal is input to the transmission line equalization circuit 7 in the next stage. In the transmission line equalization circuit 7, the total transmission characteristics of recording and reproduction are corrected so as to satisfy the Nyquist first standard. The Y signal whose amplitude characteristic and phase characteristic are corrected by the transmission line equalization circuit 7 is DC-clamped by the clamp circuit 8 and is A / D converted by the A / D converter 9. A sampling clock generated by the PLL circuit 10 and adjusted in sampling phase by the phase shifter 11 is input to the A / D converter 9. Therefore, the data shown in FIG. 7A is reconstructed in the memory 12.

Next, the color signal will be described.

The C-FM signal is sent to the Y-FM by the LPF 13.
After being separated from the signal and demodulated by the FM demodulation circuit 14, high-frequency suppression is applied by the de-emphasis circuit 15 to restore the original BY, RY line sequential signal. Then, like the Y signal, the transmission line equalization circuit 16 performs amplitude correction and phase correction, and then inputs to the BY, RY switching switch S3. The switching signal output from the BY and RY line determination circuit 17 is input to the switch S3, and BY is selected.
The signal is input to the clamp circuit 18 and the RY signal is input to the clamp circuit 19, and the signals are input to the A / D converters 20 and 21, respectively.
/ D converted. Then, in the memories 22 and 23, as shown in FIG.
The data is stored so that the pixel arrays shown in (b) and (c) are obtained.

In the same manner, the signals recorded on the B, D and C tracks are frozen in the memories 12, 22 and 23.

Next, the interpolation processing will be described. The Y signal interpolation processing is performed by the interpolation processing circuit 24, and the color difference signal interpolation processing is performed by the interpolation processing circuit 25. As shown in FIG. 11, when interpolating a black circle pixel, the Y signal is interpolated using effective pixel data (white circles) in the upper and lower two lines of the pixel to be interpolated and the three pixels in the horizontal direction. The color difference signal is VIT (HI
The position of the effective pixel (FIGS. 7B and 7C) is discriminated by the CPU (not shown) based on the T) signal, and first, the average value interpolation only in the vertical direction is performed. That is, as shown in FIG. 12A, first, B ′ is obtained from the upper and lower pixel data, and
As shown in FIG. 2 (b), B ″ is calculated from B ′ and B. Subsequent 7 pixels in the horizontal direction are replaced with the same data as they are. The same applies to RY. Time difference correction is also performed.

After the interpolation processing is performed as described above,
If data is read from the read clock generator 26 at a constant clock and converted into analog signals by the D / A converters 27, 28, 29, analog Y, BY, RY at the output terminals 30, 31, 32, respectively. The signal is obtained. Then, by passing through an RGB decoder (not shown), HD
(High definition) It is possible to output to a monitor or the like.

(Conventional Example 2) Pixel information data indicated by ◯ shown in FIG. 17 is sampled from the output of the image pickup device (offset sampling) and recorded on four tracks on the video floppy as shown in FIG. Data is resampled and reconstructed on the image memory, and the pixels marked with X are interpolated.

FIG. 19 is a circuit block diagram of the still video camera of the above system. For the sake of simplicity, it is assumed that the monochrome image pickup device 250 is mounted. The pixel information of A and B of the image sensor 250 having the number of pixels of 1000 × 1300 as shown in FIG.
The information of A is converted into a video signal by the camera signal processing circuit 1/252, and the information of B is converted into a video signal by the camera signal processing circuit 2/253.
Then, the VIT signal is added by the adders 254 and 255.

The VIT signal is a signal generated by the VIT generation circuit 256 and added to several lines in each field at a position that does not interfere with the video signal within the V-BLK period or outside the V-BLK period. It is a solitary wave having a width twice the cycle of the sampling clock of the mark. VI
T is used as a distortion check of the transmission system and as a sampling phase reference during recording.

The video signal added with VIT is input to the transmission path correction filters 1, 2, 257 and 258 in the next stage.
The transmission line correction filters 257 and 258 are filters for making correction so that the total transmission system including the reproduction system satisfies the Nyquist first standard. The video signal band-limited and amplitude-corrected by the transmission path correction filters 257 and 258 is passed through the switches S ₁ and S ₂ and pre-emphasized by the recording signal processing circuits 1, 2, 259 and 260 in the next stage.
FM modulation and the like are applied, and the adders 261 and 262 of the next stage are provided.
Is added to the pilot signal which serves as a TBC reference signal during reproduction. 263 is a pilot signal generation circuit. Then, after being set to an appropriate recording current by the recording amplifiers 264 and 265, the A field signal is transferred to the magnetic head 26.
6, the B field signal is simultaneously recorded by the magnetic head 267 during one rotation of the video floppy 268 (1/60 sec). At this time, the switches S ₁ and S ₂ are both set to the a side.

Next, the pixel information of C and D is obtained by the image pickup device 250.
After being output, and subjected to similar signal processing, they are simultaneously recorded on the video floppy 268. At this time, the switches S ₁ and S ₂ are controlled by the CPU (not shown) to be on the side b, so that the recording pattern is as shown in FIG.
With such a recording pattern, if the B and D tracks are reproduced, it is possible to reproduce the same frame picture signal of NTSC level as the conventional one.

Next, a reproducing apparatus for reproducing a video signal recorded by such a camera will be described. FIG. 20 shows a circuit block diagram thereof. First, the magnetic head 270 is brought into contact with the A track of the video floppy and reproduces the information of the A track, that is, the A field. The reproduction RF signal from the magnetic head 270 is supplied to the reproduction signal processing circuit 271 and PL.
It is input to the L circuit 272. In the reproduction signal processing circuit 271, demodulation and de-emphasis processing is performed to restore the base band signal.

On the other hand, the PLL circuit 272 extracts the pilot signal which is frequency-multiplexed and recorded together with the video signal, and P
By the LL method, a sampling clock (CK) having the same time axis fluctuation as the video signal is generated. The demodulated video signal has its sync signal separated by the sync separation circuit 273, and the gate circuit 274 extracts the VIT signal by the separated sync signal. VIT output from the gate circuit 274
The signal is A / D converted by the A / D converter 275 at the next stage, and the data is input to the VIT peak detection circuit 276. Here, the maximum value (D) of data at several sampling points near the frozen VIT is held for each rotation of the video floppy, and the sampling clock phase shifter 277 is controlled for each freeze to change the clock phase. Then, freeze and phase shift are repeated until D becomes the maximum, that is, sampling is performed at the peak point of VIT (resampling is performed at the same point as when recording).

When the sampling point is determined through the above process, the video signal is resampled at the same position as the sampling point at the time of recording by the A / D converter 278 and stored in the memory 279 as digital data. . After the freeze of the video signal of the A track is completed, the magnetic head 270 moves to the B track by the head moving mechanism 280, and the video information data of the B track is stored in the memory 279 in the same manner. In this way, after the video information of 4 fields is taken into the memory 279,
The interpolation processing circuit 281 performs interpolation processing to construct one screen.

(Prior art example 3) Taking a monochrome image pickup device as an example for simplification of description, pixel information data indicated by a circle shown in FIG. 23 is recorded on four tracks on a video floppy disk as SV as shown in FIG. The data is recorded according to the format, and the so-called “sample value analog transmission” is performed, in which the data marked with a circle is resampled during playback. Then, in the memory space, the data of X mark is interpolated from the pixel data of the surrounding ○ mark, and HD
It is intended to obtain high-definition image information similar to TV.

In this case, the total transmission path including the electromagnetic conversion system must satisfy the Nyquist's first standard, and in order to perform resampling at the correct phase, highly accurate time-axis fluctuation correction (TBC) is required.

This sampling phase reference signal HIT is
As shown in FIG. 25, it is a solitary wave of the period T of the sampling clock and is added to the first part of the effective period of each line.

FIG. 26 shows the HIT pulse waveform before A / D conversion during reproduction, and the black points in the figure must be sampled.

FIG. 27 is a block diagram of an automatic phase adjustment circuit that automatically shifts the sampling phase to an optimum position based on the A / D converted HIT data. In the figure, reference numeral 451 denotes a phase shift circuit for shifting the clock phase based on a control signal from the CPU 456.
52 is an A / D converter for converting a video signal into digital data, 453 is an image memory, and 454 is a HIT of several lines.
It is a memory for adding data and holding the data. 455 is a control pulse generation circuit that generates a control pulse for controlling the data adder 454,
A CPU (microprocessor) 456 performs a predetermined calculation based on the digital data from the data adder 454, controls the phase shift circuit 451 based on the result, and shifts the sampling clock phase to an optimum position. 457 is a C-SYNC (composite synchronizing signal) input terminal,
Reference numeral 458 is a reproduction signal input terminal and 459 is a sampling clock input terminal.

Next, the operation will be described.

The control is performed using the data of several points near the HIT in the video signal converted into digital data by the A / D converter 452. That is, first, the control pulse generation circuit generates a gate pulse (GP) for extracting data in the vicinity of HIT from C-SYNC input to the controller 455. This is Figure 28
As shown in (c), a signal in the vicinity of HIT is a high level signal and is output only during a continuous number H of 1V periods.

When the GP pulse goes high, the data adder 454 sequentially fetches eight pieces of data as shown in FIG. 28, for example. Here, the reason for widening the range in which the HIT data is taken is that H-sync is for H-SYNC (horizontal synchronization signal).
This is so that the position of the IT signal is not affected even if it shifts by several clocks.

The fetched data is sequentially stored in eight data storage locations in the memory 454. Then, the HIT data of the next line is also added to the data of the same point on the previous line and similarly stored at the same address. Similarly, four lines of data are fetched and the data of each point from 1 to 8 is added for four lines. The four lines of HIT data thus captured in the memory 454 are output to the CPU 456.

The CPU 456 uses the HIT data 1 to 8
The average value of each point up to is calculated, and the address (one of 1 to 8) having the maximum value is obtained from the result. Here, for example, when the data at the fourth address is detected to be the maximum as shown in FIG. 28 (a), the difference between the data at the addresses before and after the fourth address is obtained, and as shown in FIG. If the difference d ₁ between the data at address 3 and the data at address 3 is larger than the difference d ₂ between the data at address 4 and address 5, the phase shift circuit 451 is controlled to advance the clock, and in the opposite case to delay it.

Here, the phase shift circuit 451 is composed of a tap delay line and a multiplexer each having a step of 1/10 of one clock cycle, and advances or delays the clock by selecting the terminal output of the tap delay line. (See FIG. 15).

In this way, the freeze is repeated until the difference between d ₁ and d ₂ becomes less than the predetermined value.

(Conventional Example 4) For details of the CHSV system, see Technical Report of the Television Society [Vol.14 No.76 P1-12 Dec 199].
0] Briefly, pixels are recorded on four tracks in the specified track order, sample value analog recording / reproduction (sample value analog transmission) is stored in the image memory, and pixels lacking in an image composed of 1300 × 1000 pixels are recorded. Is reproduced to reproduce an image of approximately 1300 × 1000 pixels.

To realize sampled value analog transmission, a highly accurate TBC is required. For that reason, a pilot signal is added in a burst form in the synchronous blanking period in the vicinity of 2.5 MHz of the transmission signal.

FIG. 33 shows the relationship between pixels and tracks. At the time of recording and reproduction, it is necessary to properly match the relationship between this pixel and the track.

(Prior art example 5) As shown in FIG.
Of the image pickup device or the image memory data having pixel information of 00 (horizontal) × 1000 (vertical), pixel information data of O mark (in the case of black-and-white information) is recorded on four tracks on the video floppy as shown in FIG. , When replaying, the data marked with ○ is resampled and reconstructed on the semiconductor memory.
The pixels marked with X are interpolated from the surrounding data. At this time, the total transmission line of the recording / reproducing system including the electromagnetic conversion system must satisfy the so-called Nyquist characteristic as shown in FIG.

For the purpose of checking the amplitude characteristic and phase characteristic of the transmission line and obtaining the sampling phase reference, 1
One HIT signal of the T width (T = 1 / fs) is added to the video signal immediately after the blanking period, one in H (horizontal synchronization period).

FIG. 41 is a circuit block diagram of a recording / reproducing apparatus for once capturing a high-definition image such as an HDTV signal into a memory for recording / reproducing by the CHSV system or recording / reproducing a normal NTSC signal.

The case of recording an NTSC signal will be described first.

Reference numeral 901 denotes an NTSC video signal input terminal.
Reference numeral 902 denotes an NTSC digital signal processing unit composed of a frame memory, a duder, etc., and a switch S for recording.
_The Y + S signal is output to the a terminal of 2 and the color difference line sequential signal is output to the a terminal of the switch S ₃ . The Y + S signal and the color difference line sequential signal are subjected to pre-emphasis processing by the pre-emphasis circuits 903 and 904, respectively, and then the FM modulation circuit 90.
5 and 906 perform FM modulation, and an adder 907 adds the ID signal generated from the ID signal generator 908 at an appropriate level ratio. Then, after a proper recording level is set by the recording amplifier 909, one field signal is recorded by one rotation on the video floppy 912 which is rotating at a constant speed by the spindle motor 911 by the magnetic head 910.

When recording a frame signal, the magnetic head 910 is moved to the head moving mechanism 9 after recording one field.
One track is moved by 13 and thereafter the signal of the remaining one field is output from the NTSC digital signal processing circuit 902 and similarly recorded during one rotation of the video floppy.
The switch S ₁ is set to the b side during recording.

Next, the case of recording the HDTV signal by the CHSV system will be described.

The RGB signal input from the HD analog input terminal 914 or the digital input / output terminal 915 is approximately 1000 (vertical) × 2000 (horizontal) × 8.
Bit x 3 planes A semiconductor memory with a total capacity of 6 Mbytes, RGB → color difference signal, color difference signal → RGB calculation,
DSP (Digital Sign) that digitally performs interpolation processing, etc.
input to a CHSV digital signal processing circuit 916 composed of an al procedure or the like. Here, when the HD signal is recorded by the CHSV method, when the 1000 × 1300 information in the central portion of the 1000 × 2000 pixel information is black and white, the information indicated by a circle in FIG. 38 and the color difference signal are shown in FIG. As shown in 42, information thinned out every 16 pixels (○
Mark) is output from the memory. Then, in the CHSV recording signal processing circuit 917, the HIT signal is added, F special correction and the like are performed, input to the b terminals of the switches S ₂ and S ₃ , and recorded on the video floppy 912 as in the case of NTSC. It However, in this case, the pilot signal generator 9
The adder 907 adds the pilot signals, which are the time-axis fluctuation reference output from No. 18. And FIG.
As shown in, recording is sequentially performed so that one screen is composed of four tracks.

Next, the operation during reproduction will be described.

First, the normal SV reproduction will be described. During reproduction, the switch S ₁ is set to the a side. The RF signal reproduced from the magnetic head 910 is reproduced by the reproduction amplifier 91.
After being amplified to an appropriate level at 9 and band-separated by a filter (not shown), the video signal is demodulated by the Y signal demodulation circuit 920 and the color difference signal demodulation circuit 921. The de-emphasis circuits 922 and 923 de-emphasize the Y signal and the color difference signal, respectively, and freeze one field in the memory in the NTSC digital signal processing unit 902. When the ID signal is detected by the ID detection circuit 924 and it is determined that the frame signal is recorded, the information is sent to the CPU 925, the magnetic head 910 is moved by one track, and the other field signal is processed. Freeze the memory in section 902. Then, the NTSC digital signal processing circuit 902 performs line synchronization, matrix calculation, etc., and outputs as RGB output to the terminal 926.
Output to the outside.

Next, CHSV reproduction will be described.

The RF signal recorded by the CHSV system is
Since the pilot signal is multiplex-recorded between 2.5 and 3 MHz, the BPF 92 for extracting the pilot signal
The presence or absence of the No. 7 output signal is detected by the pilot signal detection circuit 928. That is, reproduction is sequentially performed from the outer peripheral side (one track), and if a pilot signal is detected, it is determined that the following three tracks including that track are CHSV recording. And the de-emphasis circuit 922, 92
The output signal of 3 is F in the CHSV reproduction signal processing circuit 929.
The special correction and the phase correction are performed, and the memory in the CHSV digital signal processing circuit 916 is frozen to have the pixel relationship as shown in FIG. The sampling clock at this time is generated from the pilot signal by the PLL circuit 930.

Pixel information in which the Y signal and the color difference signal are not transmitted after the video signal of 4 fields is frozen in the memory in the processing unit 916 (X mark in FIG. 38, ● mark in FIG. 42)
Is interpolated from surrounding pixel information, converted into an RGB signal, and then D / A converted at an HDTV read clock rate to be output as an HD signal to the terminal 931.

[0058]

[Problems to be Solved by the Invention] (Regarding Conventional Example 1)
However, in the prior art example 1, since the color difference signals are line-sequentialized by the switches S ₁ and S ₂ as shown in FIG. 9, the delay characteristics of the LPFs 70 and 71 are different or after FM modulation (not shown). If there is a difference in the delay characteristics of the LPFs, the same BY signal (RY) is frozen in the memories 22 and 23 shown in FIG.

When the signal data having a time difference every several lines is vertically interpolated in this way, there arises a problem that ringing or periodic moire occurs at the edge portion and the resolution deteriorates.

(Regarding Conventional Example 2) In Conventional Example 2,
Since the sampling phase is adjusted for each field reproduction, for example, when the peak point is detected by the mountain climbing method, at least 4V (1V is 1/60 sec) time is required to freeze the image of one field. If the head movement time is further added, it takes 16V (267 msec) or more to freeze one screen.

(Regarding Conventional Example 3) In Conventional Example 3, there are the following problems.

That is, when a dropout occurs in the reproduced signal, in a normal SV reproducing apparatus, the portion having the dropout is replaced with the signal 1H before, so that the HIT of the portion for which the sampling phase adjustment is just performed.
HIT 1H before even if the signal drops out
It will be replaced by a signal. At this time, when the accuracy of the 1H delay line is insufficient, the replaced HIT signal has a time lag S from the other three HIT signals, and the correct peak point cannot be detected. There is a problem that it ends up.

(Regarding Conventional Example 4) As the output format of the signal recorded as CHSV, high band field output, frame output and HD (High Definition) output can be considered.

When CHSV dubbing is considered, there are two possible methods: dubbing once for each field, that is, for each track, via the HD signal format.

However, is the image after the interpolation is performed, and if the image is dubbed, the image quality may be greatly deteriorated by that amount. Needs to be very careful about which track is being output so as not to make a mistake.
Since it is difficult to do by hand (it is easy to make an error), it is necessary to automate it. For that purpose, a signal identifying which of the four tracks that currently make up CHSV and the dubbing of one track are finished, As a result, a signal for moving the output side by one track is required, and it is necessary to define their standards. This standard is completely independent of other standards, and there is a problem that it is not easy because it needs to be newly set regardless of whether it is a signal standard or a mechanical standard of a connector.

(Regarding Conventional Example 5) With a recording / reproducing apparatus having an image memory as shown in FIG. 41, dubbing is possible with one unit. That is, after the image to be dubbed is stored in the memory, the head may be moved to the track to be dubbed for recording, or it may be changed to a new video floppy for dubbing.

In this case, the normal SV image can be dubbed only as the normal SV image. However, the CHSV image can be a field image or a frame image as a normal SV image in addition to the case of dubbing as the CHSV image. Dubbing of the middle two tracks of 39) is possible.

As for the CHSV signal, as shown in FIG. 43, since the HIT signal is added to a part of the video signal of each line, when the CHSV signal is dubbed as a normal SV signal, the HIT signal is added. There is a problem that it is dubbed in the state and vertical lines are visible on the left edge of the monitor screen, making it very observable.

The present invention has been made under such circumstances, and provides a video signal reproducing apparatus and a video signal recording apparatus capable of accurately processing a video signal of CHSV, HDTV or the like in a short time. The purpose is.

[0070]

In order to achieve the above-mentioned object, the present invention provides a video signal reproducing apparatus with the following (1) to (1).
It is constructed as in (6) and the video signal recording device is constructed as in (7) and (8) below.

(1) A video signal reproducing apparatus which reproduces a video signal from a recording medium, writes the video signal in an image memory and performs an interpolation process on the image memory, and a VIT added to each color difference signal in a field unit. Signal or HIT signal, the peak points of the signals added to the same color difference signal in different fields are compared, and the time difference detecting means for detecting the time difference and the image memory based on the output of the time difference detecting means. And a control means for controlling the phase of the horizontal address reset signal for writing in.

(2) The video signal reproducing apparatus according to (1), wherein the recording medium is a disc-shaped recording medium in which each color difference signal is recorded via the signal processing circuits of two systems.

(3) A video signal reproducing apparatus for reproducing a video signal from a recording medium, performing analog-digital conversion and writing the image signal in an image memory, wherein the VI added to the video signal.
A sampling phase control means for controlling the sampling phase of the analog-digital conversion by a control signal based on the T signal or the HIT signal and a holding means for holding the control signal are provided, and the sampling phase control means are the same recording system. A video signal reproducing device for performing control using the output of the holding means as a control signal during analog-digital conversion of a field passing through.

(4) A video signal reproducing apparatus for reproducing a video signal from a recording medium, performing analog-digital conversion at a predetermined sampling phase based on a HIT signal added to the video signal, and writing the analog video into an image memory. The HIT signals of several lines that have been set are taken in and the analog-
First control means for controlling the sampling phase of digital conversion to be the predetermined sampling phase, detection means for detecting that dropout has occurred in a part of the HIT signals of the several lines, and this detection means Depending on the output, the HI taken into the first control means before this output
The data of the T signal is invalidated and H of several lines after this output
A video signal reproducing apparatus comprising: second control means for allowing the IT signal to be taken into the first control means.

(5) Of the video signals of a plurality of fields reproduced from the recording medium, a signal adding means for adding a field identification signal to a predetermined one field video signal, and a field to which the field identification signal is added by this signal adding means And a control means for outputting the video signals of a plurality of fields including the above in a predetermined order.

(6) The video signal reproducing device according to the above (5), wherein the plurality of fields are four fields forming a CHSV signal.

(7) A first image memory that stores a video signal to which a HIT signal is added, which forms one frame in four fields, and a second image that stores a video signal that forms one frame in two fields. A memory, a first recording system for reading and recording a video signal of four fields or a video signal of a partial field of four fields from the first image memory, and a video of two fields from the second image memory. A video signal recording apparatus having a second recording system for reading and recording a signal or a video signal for each field.

(8) The first recording system is provided with HIT signal removing means for removing the HIT signal added to the video signal when recording the video signal for each partial field of four fields. (7) The video signal recording device as described above.

[0079]

With the configurations (1) and (2), the pixel position shift between the same color difference signals in different fields is eliminated. With the configuration of (3), the previous signal is used as the control signal for controlling the sampling phase at the time of analog-digital conversion of the field passing through the same recording system. According to the configuration of (4), when dropout occurs in a part of the HIT signal of several lines, the data of the HIT signal before the dropout becomes invalid, and the video signal based on the data of the HIT signal of several lines thereafter is invalidated. Analog-to-digital conversion is performed.

In the configurations of (5) and (6) above, the predetermined 1
Video signals of a plurality of fields with the identification signals added to the fields are output. In the configurations of (7) and (8), a video signal for every four fields or a video signal for every one field of four fields is read out from the image memory that stores the video signal forming one frame in four fields. Then, the video signals of two fields or the video signals of one field are read and recorded from the image memory in which the video signals forming one frame in two fields are stored. In the configuration of (8) above,
Further, when recording a video signal for each partial field of four fields, the HIT signal is removed.

[0081]

EXAMPLES The present invention will be described in detail below with reference to examples.
The following examples correspond to the conventional examples, such as the first example and the conventional example 1 and the second example and the conventional example 2.

(Embodiment 1) FIG. 1 is a block diagram of a main part (color difference signal reproduction system) of a "video signal reproduction apparatus" according to Embodiment 1. In FIG. Those having the same functions as those in FIG. 10 are designated by the same reference numerals, and have the same configuration as that in FIG. 10 except for the color difference signal reproducing system.

In FIG. 1, 101 is a sync separation circuit 6
The HD (horizontal drive signal) signal output from the output signal and the clock ck input from the phase shifter 11 are input signals, and C
The HD phase shifter generates a signal (HD ') having a phase different from that of the input HD in units of one clock by a control signal T from the PU 105. 102 is a VI added to the RY signal by the gate pulse output from the sync separation circuit 6.
A gate circuit for extracting the T (or HIT) pulse, 103 an A / D converter for A / D converting the VIT (or HIT) signal, 104 a memory controller for controlling the memories 22 and 23, and 105 a system C which controls the whole and also performs the main control of this embodiment
It is PU.

The operation will be described below with reference to FIGS. 2, 3, 4, and 5.

First, the magnetic head 1 shown in FIG. 10 is brought into contact with the A track to reproduce the A signal. First, the color difference signals in the A track are distributed to the memories 22 and 23 and frozen (see FIG. 2). Step 1). At this time, VIT in the RY signal extracted by the gate circuit 102
(Or HIT) signal is clock ck and A / D converter 1
A / D conversion is performed by 03. And the data is C
It is input to the PU 105. The HD ′ signal output from the HD phaser 101 is input to the CPU 105.
The HD ′ signal at this time is a signal having the same phase as the input HD signal. Here, in the CPU 105, FIG.
As shown in, A / A from the rising edge of HD '(HD)
The address M ₁ at which the D-converted VIT (or HIT) data has the maximum value is obtained, and the data is held in the internal memory (step 2 in FIG. 2).

During this time, the Y signal is stored in the memory 12 shown in FIG.
Has been incorporated into.

Next, the magnetic head 1 contacts the B track,
The signal of the B track is reproduced (step 3). At this time,
Although the color difference signals are not frozen in the memories 22 and 23, the VIT (or HIT) signal is A / D converted in the A / D converter 103, and the data is CP.
The address M ₂ of the maximum value of VIT in the RY signal input to U105 is obtained (FIG. 3 (c)), (step 4).

Next, the CPU 105 determines the difference D between M ₁ and M ₂ .
(= M ₁ −M ₂ ) is calculated (step 5). If the absolute value of D is 1 or less (step 6, YES), that is, if the time difference of the transmission path is within the sampling clock width of the Y signal, it is determined that the output image is not affected, and C
A control signal for starting freeze is output from the PU 105 to the memory controller 104, and the memories 22 and 23 freeze the color difference signals (step 7). As the memory horizontal address reset signal at this time, the same HD signal as when the A track signal is frozen is used.

When the absolute value of D is larger than 1 (step 6, NO), it is judged in step 8 shown in FIG. 2 whether D is larger than 1. Here, when D is greater than 1 (step 8, YES), that is, as shown in FIG. 4, for example, when D = 3, the signal in the A field is delayed by 3 clocks from the signal in the B field. At this time, the control signal is input from the CPU 105 to the HD phase shifter 101, and the HD ′ phase is advanced by 3 clocks (step 9). As a result, the horizontal address reset signal HD 'becomes as shown in FIG. 4 (d). By using this HD' signal as the horizontal address reset signal, the color difference signal having no time difference from the A field is frozen.

When D <−1 (step 8, N
O), in this case, as shown in FIG. 5, the signal in the A field leads the signal in the B field. At this time, as shown in step 10, the value of | D | (in this case, 2) Freeze only by delaying the HD signal.

After the freeze of the color difference signal of the B track is completed in this way, the phase of HD 'is reset to the original phase in step 11, and the C track and the D track are reproduced in the same manner.

As described above, according to this embodiment,
V added in the color difference signal via different transmission paths
A means for detecting the time difference of the IT peak point is provided, and when the time difference is one cycle or more of the sampling clock, the phase of the horizontal address reset signal at the time of memory writing is changed in clock cycle units. There is no time difference for each line, ringing and blurring are eliminated after interpolation, and a high-quality output image can be obtained.

In the first embodiment, VIT (or HI
A) is newly added to A / D conversion of T).
The color difference signal A / D converter 20 or 21 is provided.
Frozen in memory 22 or 23 using
The IT (or HIT) data may be taken into the CPU 105.

Further, since the signals of the D and C tracks pass through the same transmission paths as the signals of the A and B tracks, respectively, during reproduction of the D and C tracks, the VIT shown in the first embodiment is used.
(Or HIT) peak address detection is not performed, and the detection result (D) on the B track is held in the CPU 105,
When reproducing the C track, HD 'may be generated based on the data.

(Second Embodiment) FIG. 13 is a circuit block diagram of a "video signal reproducing device" according to a second embodiment. Figure 20
Those having the same function as are given the same reference numerals.

The operation will be described below with reference to FIG.
The magnetic head 270 is driven by the head moving mechanism 280 and first comes into contact with the A track to reproduce the video signal recorded on the A track. VIT signal (a) in video signal
Is extracted from the video signal by the gate pulse (b) (c) and input to the A / D converter 275. The A / D converter 275 A / D-converts the VIT signal with a clock ck whose frequency synchronized with the pilot signal by the PLL circuit 272 is 21.47 MHz (double the sampling clock frequency). An enlarged view of the sampling points at that time is shown in (d). At this time,
The phase shift amount of the phase shifter 277 is set to a predetermined initial value.

[0097] The maximum value in this case the data is because it is D _0, and stores the configured data storage unit the value of D ₀ in VIT peak detection circuit 276 inside the semiconductor memory or the like. Next, the VIT peak detection circuit 276 outputs a signal N ₁ for controlling the phase shifter 277. The control signal N ₁ is, for example, a 4-bit digital signal and is input to the phase shifter 277 via the control signal holding circuit 282. Phase shifter 2
Reference numeral 77 denotes a tap delay line 277-1 with a step size of 3 nsec and 4-bit data (A to D) as shown in FIG.
Is composed of a multiplexer 277-2 for selecting an input signal. The delay amount is controlled by the control signal N _{1 so as} to increase (advance ck) by 3 nsec from the initial setting value, and then the VIT signal is again A / D in the period of 1V.
Convert. Figure 14 shows the sampling points at this time.
It shows in (e). The maximum value in this case is D ₁ and D ₁ >
Since it is D ₀ , the control signal of N ₂ = N ₁ +1 is applied to the phase shifter 27.
7 is input, and 3 nsec ck is advanced. Then, similarly, the VIT signal is frozen again (f). The maximum value at this time is D ₂ , and this time D ₂ <D ₁ , so the control signal N ₃ = N ₂ −1, and the same value of N ₁ is input to the phase shifter 277. At this time, the VIT peak detection circuit 27
A pulse P is output from 6 and the switch S ₃ is turned on.

As for the value of N ₁ , the sampling point is VI
Phase shifter 277 so as to sample almost the maximum point of T
The video signal is sampled by the A / D converter 278 in the same sampling phase as the above (controlling the delay in the gate circuit 274 can be ignored).

Further, at this time, the pulse P is also input to the control signal holding circuit 282 to latch the data of N ₁ and hold the value in the internal memory. When the freeze of the video signal of the A track to the memory 279 is completed, a control signal is input to the head moving mechanism 280 from a CPU (not shown) that controls the entire system, and the magnetic head 270 contacts the B track. Similarly, the phase of the sampling clock is controlled so that sampling is performed at the peak of VIT, and the video signal is frozen in the memory 279 after the optimum control signal N ₁ ′ is determined. At this time, similarly, N ₁ ′ is held in the internal memory of the control signal holding circuit 282.

Here, N ₁ and N ₁ ′ may not be the same value because the transmission paths of the recording system are different between A and B.
That is, the transmission line correction filters 257 and 25 shown in FIG.
This is because the phase of the pilot signal and VIT do not always become the same between A and B (C, D) due to the difference in the group delay characteristics of No. 8.

However, since the difference in the delay characteristics of the circuit blocks other than the transmission line correction filter is so small that it can be ignored, the A, C signals and B, D signals passing through the same transmission line correction filter have the phases of VIT and the pilot signal. The relationships are considered to be almost equal. Therefore, when the video signal of the A track and the video signal of the C track are reproduced, and when the video signal of the B track is reproduced and the video signal of the D track is reproduced, the control signal N of the phase shifter N
Can be the same value.

Therefore, after the magnetic head 270 is brought into contact with the D track after the freeze of the video signal of the B track is completed, the routine for obtaining the peak of VIT is not performed, and the control signal holding circuit 282 outputs N ₁ ′. The value is output and the switch S ₃ is immediately set to the ON state and immediately D
The video signal of the track is frozen in the memory. Thereafter, the magnetic head 270 is brought into contact with the C track, the value of N ₁ is output from the control signal holding circuit 282, and similarly, the video signal of the C track is immediately frozen in the memory 279.

As described above, according to the present invention, 4
In a still video camera that configures one screen in a field, it has a means for holding signal data for controlling the sampling clock phase at the time of reproduction, and when reproducing a field signal that passes through the same recording system as the reproduction signal, Since the sampling phase is adjusted by the control data, the signals of 4 fields can be frozen in the memory in a short time.

In the second embodiment, since the recording camera has a 2-channel head and the signal processing system is 2 systems, the phase control can be performed only twice. However, as shown in FIG. If a memory is installed, the signal processing system becomes one system, and the reproduction system may use the optimum control data N on the A track for the other three tracks.

Further, in the second embodiment, the peak value of VIT is obtained as a means for obtaining the optimum sampling point of VIT, but the symmetry of VIT is used so that the data on both sides of the peak point of VIT are the same. To ck
May be controlled (see Example 3 described later).

Further, although the tap type delay line is used as the phase shifter in the second embodiment, the delay amount may be changed in an analog manner by using a varicap.

(Third Embodiment) FIG. 21 is a circuit block diagram showing a third embodiment. In the figure, 401 is a reproduction RF signal input terminal from a magnetic head (not shown), 402 is a preamplifier, 403 is a reproduction signal processing circuit including an equalizer circuit, a demodulation circuit, a de-emphasis circuit, and 404.
Is an A / D converter, 405 is a sampling clock generation circuit that extracts a time axis correction pilot signal that is frequency-multiplexed and recorded together with a video signal during recording, and generates a sampling clock by the PLL method. 406 is a sampling phase with a correct sampling clock. To become a CPU
A phase shift circuit controlled by a control signal from 415, 407 is a sync signal separation circuit for separating a sync signal from the demodulated video signal.

Reference numeral 408 is a dropout detection circuit that detects the RF output from the preamplifier 402 and outputs a high level signal only during the dropout period. Reference numeral 409 is a register 4
A control pulse generation circuit for outputting a control signal for controlling the signal 13, 410 an AND circuit, 411 a monostable multivibrator (MM), 412 a data adder, and 413 a RAM of 8 words × 8 bits Registers 414 are image memories for storing image information data.

Reference numeral 415 is a CPU for controlling the phase shift circuit 406 so that the added HIT data for four lines from the register 413 is read and a predetermined calculation is performed so that the sampling phase of the HIT becomes a correct phase. 416 is a switch S that is set on the side of the period b of the output pulse from the MM 411, and 417 is an OR circuit.

Next, the operation will be described with reference to FIG.

As the HIT pulse for automatic phase adjustment, the one added to lines 100 to 103 is used, and the number of HITs to be taken out is eight in the section as shown in FIG. Then, the case where the dropout occurs in the GP section of 102 lines will be described.

When the GP pulse shown in FIG. 22A is output from the control pulse generation circuit 409 on the 100th line, the register 413 synchronizes with the clock and outputs eight A / D data in this section sequentially to the address of the register. Store in 1-8. At this time, the upper 6 bits of the 8-bit data from the A / D converter 404 are fetched. Next, when the GP pulse of 101 lines (FIG. 22B) is output from the control pulse generation circuit 409, the H pulse of 100 lines is output from the register 413 in synchronization with the clock ck.
The IT data is output in the order in which it is stored, that is, the data at address 1 is sequentially output, and the HI at the same point on 101 line
The higher 6 bits of T data and the adder 412 add
Addresses 1 to 8 are sequentially stored again. That is, at this point, HIT neighborhood data of 100 lines and 101 lines (data of points 1 to 8 shown in FIG. 28)
The added data of is stored in the register 413.

It is assumed that dropout occurs on the 102nd line after the period P from the rise of the GP pulse, as shown in (c). Dropout detection circuit 408
The dropout pulse (DOP) from is gated by the AND circuit 410 only during the GP pulse period and input to the MM circuit 411 in the next stage. And from the MM circuit 411, DO
C with a time width equal to the GP pulse width from the rising edge of the P pulse
The LP pulse (d) is output. The CLP pulse controls the switch S to the b side and is further input to the OR circuit 417. The GP pulse is input to the other input of the OR circuit 417, and the output thereof is the pulse (GP ′) as shown in (e), and this control pulse is input to the register 413. The register 413 reads and writes data as described above during the GP ′ period, but since the input data is set to 0 during the CLP pulse period, the register 41
The data of 3 are all cleared to 0.

On the other hand, the control pulse generation circuit 409
When a dropout pulse is input, outputs the GP pulse for four lines again from the next line. That is, 1 from 103 lines as shown in (f) to (i)
The GP pulse is output during the 06th line and the data of the HIT pulse in the 103rd to 106th lines is taken in.

In this way, H added by four lines is added.
When the IT data is stored in the register 413, the CPU 4
15 takes in 8 sets of data, first performs averaging, and then calculates the point (address) at which the maximum data value is obtained. Then, the difference between the data of the points before and after that and the data of the maximum value is obtained, it is judged whether the clock is delayed or advanced, and the control signal is sent to the phase shift circuit 406. Then, the freeze for one field is performed again, and the same control is repeated until the difference between d ₁ and d ₂ becomes equal to or less than the predetermined value by the same control, and the video signal is sampled at the correct sampling phase.

As described above, in this embodiment, the HIT pulse, which is the sampling phase reference signal added to each line, is A / D converted, data of a predetermined number of lines is fetched, and the CPU optimizes it. In a device that automatically obtains the sampling phase, if a dropout occurs in a part of the HIT signal to be captured, the HIT data of the line before the dropout exists is invalidated,
HIT of the line next to the line where the dropout exists
Since the data for the number of lines that has been set again is loaded, the automatic adjustment of the sampling phase can be surely performed even if there is a dropout in the HIT portion.

Although the monostable multivibrator MM11 is used for the CLP pulse in the third embodiment, it may be constituted by a counter.

Further, in the third embodiment, the sampling phase adjustment is performed by using the HIT data of the 4th line from the 100th line, but the HIT data of more lines are taken in to improve the accuracy. Good.
It is not limited to the 100th line. And H
Although eight data are sampled in the vicinity of IT, if the position accuracy of the HIT signal from H-SYNC is sufficient, a smaller number of samples may be used.

(Embodiment 4) FIG. 30 is a block diagram of essential parts of a "video signal reproducing apparatus" according to Embodiment 4. In FIG.

In the figure, reference numeral 703 denotes a recording medium (2-inch video floppy), the output of which is taken out by the head 702, and the CHSV reproduction processing unit 703 performs de-emphasis.
FM demodulation is performed, analog-digital conversion is performed by the A / D converter 704, and the result is stored in the memory 705. In this way, the pixels of each field of ABCD are stored in the memory 705. D is fetched from the memory 705 by a clock.
A / A converter 706 performs digital-analog conversion and outputs. The output signals are A, B, C, D, A,
It is a repeating signal of B, C, D .... At the same time, the output of the clock generator 707 is also stopped by the A track identification signal adding circuit 708 so that the clock is also stopped for a certain period of V blanking when the A track image signal is output.

FIG. 31 shows the CHSV according to the output of the fourth embodiment.
It is a block diagram in the case of dubbing recording.

The Y + S signal and the line-sequential color difference signal are subjected to emphasis processing and FM modulation processing by the SV signal recording signal processing circuit 801 according to the SV high band format. On the other hand, the clock signal is the pilot signal control circuit 802.
And the pilot signal is output only during the synchronous blanking period.

Output of pilot signal control circuit 802 and S
The outputs of the V recording signal processing circuit 801 are added by the adder 803 and recorded on the recording medium 805 by the head 804. A system controller (not shown) determines which track among A, B, C, and D, and records it at the corresponding track position based on that.

A detailed description of the pilot signal control circuit 802 is shown in FIG.

The clock signal is frequency-divided by the frequency divider 810 to be the frequency of the pilot signal and the phase comparator 809.
to go into. The output of the phase comparator 809 is held by the sample and hold circuit 808 for A track identification so as not to malfunction while there is no clock signal temporarily.
The output of S / H808 enters VCO806 and VCO80
Control frequency of 6. The output of the VCO 806 enters the gate circuit 807 and the phase comparator 809. In the gate circuit 807, the pilot signal is transmitted only during the synchronous blanking period.

As described above, according to this embodiment,
Dubbing can be done in a more general format. For example, current T
Similar to the general signal transfer format for V signals, dubbing can be performed by transferring only with a BNC cable.

In the fourth embodiment, as the identification of the A track,
Although a temporary cutoff of the clock signal is used, various means such as applying a direct current gettering or dropping a part of the cycle can be adopted.

Although the clock signal is sent in the fourth embodiment, a pilot signal may be sent.

(Embodiment 5) FIG. 34 is a circuit block diagram of essential parts of a "video signal recording / reproducing apparatus" according to Embodiment 5. In FIG.

For the sake of simplicity, only the block of the recording system is shown. Elements having the same functions as those in FIG. 41 are designated by the same reference numerals.

In FIG. 34, reference numeral 801 denotes a dubbing mode setting switch, which has the mode shown in FIG. SW
₁ and SW ₂ are the CHSV digital signal processing circuit 916.
Y + S signal and color difference signal (a side) from the CHSV recording signal processing circuit 917 and the color difference signal (b) from the CHSV recording signal processing circuit 917.
The HIT signal is added to the signal passing through the CHSV recording signal processing circuit 917, and the HIT signal is not added when not passing.

Next, each dubbing mode will be described.

In the case of A in FIG. 35, since the dubbing is the normal SV, the switches S ₂ and S ₃ are set to the side a in this case. At this time, in the case of frame recording, CPU 925
Then, a control signal is sent to the ID signal generator 908 and an ID signal (Odd / Even) is added.

In the case of B, since CHSV dubbing is performed, the switches S ₂ and S ₃ are set to the b side, and the switch SW
₁ and SW ₂ are set to the b side. Further, a control signal is sent from the CPU 925 to the pilot signal generator 918 and the pilot signal is added. Further, an ID signal (Odd / Even information) is added at the time of recording two tracks in the center.

In the case of C, each field of the CHSV4 field is recorded as a normal SV field image, and the switches S ₂ and S ₃ are on the b side, and the switch SW.
₁ and SW ₂ are set to the a side and are dubbed as a video signal without a HIT signal.

In the case of D, the central 2 fields (1 frame) of the CHSV 4 fields are dubbed as an SV 1 frame image, and the switches S ₂ and S are used.
₃ is set on the b side, and switches SW ₁ and SW ₂ are set on the a side. In this case, the HIT signal is removed and the ID signal (Od
d / Even) is added.

As described above, according to this embodiment,
A setting switch for switching the dubbing mode is provided, and C
When dubbing the HSV playback signal as a normal SV field signal or frame signal, the CHSV signal dubbed as a normal SV is removed because the HIT signal added to a part of the video signal is removed in the CHSV system. Even when viewed on a TV monitor or the like, an image without vertical lines or the like is obtained on a part of the left side of the screen.

In the fifth embodiment, since the HIT signal is added by the CHSV recording signal processing circuit 917, it is possible to switch between CHSV dubbing and CHSV normal SV dubbing with a signal passing through this circuit and a signal not passing through this circuit. However, as shown in FIG. 36, the HIT portion of the output from the CHSV recording signal processing circuit 917 is connected to the gate circuit 80.
2-1 and 802-2 may be used for blanking. 37 (a) is a Y + S signal output from the CHSV recording signal processing circuit 917, (b) is a color difference signal, (c) is a gate pulse GP-1, (d) is GP-2, (e),
(F) is Y + S in which the HIT signal is muted,
It is a color difference signal.

Further, in the above description, CHSV is an ordinary S
Although the HIT signal is removed in the case of dubbing as V, the CHSV digital signal processing circuit 91
HD (High Definitio) input to the HD compatible memory of 6
n) It is effective even when the signal is recorded as a normal SV.

Although each of the above embodiments relates to a still image, the present invention is not limited to this and can be applied to a moving image.

[0141]

As described above, according to the present invention,
Video signals of CHSV, HDTV, etc. can be processed accurately in a short time.

Specifically, according to the first and second aspects of the present invention, ringing, bleeding, etc. in the image are eliminated. According to the invention of claim 3, the image signal can be reproduced in a short time. According to the invention described in claim 4, even if there is a dropout of HIT, automatic adjustment of the sampling phase can be reliably performed. According to the fifth and sixth aspects of the invention, the signal can be delivered without fail in a general signal delivery format. According to claims 7 and 8, video signals of various dubbing modes can be obtained. In the invention according to claim 8, the HIT signal is deleted when dubbing as a normal SV, and vertical lines and the like do not appear on a part of the left side of the screen.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a first embodiment.

FIG. 2 is a flowchart showing the operation of the first embodiment.

FIG. 3 is a diagram showing an example of a VIT waveform according to the first embodiment.

FIG. 4 is a diagram showing an example of a VIT waveform according to the first embodiment.

FIG. 5 is a diagram showing an example of a VIT waveform according to the first embodiment.

FIG. 6 is a diagram showing a color filter array in Conventional Example 1.

FIG. 7 is a diagram showing pixels to be transmitted in Conventional Example 1.

FIG. 8 is a diagram showing a transmission pattern on a floppy in Conventional Example 1.

FIG. 9 is a block diagram of a camera according to Conventional Example 1.

FIG. 10 is a block diagram of a playback device in Conventional Example 1.

FIG. 11 is an explanatory diagram of Y signal interpolation processing.

FIG. 12 is an explanatory diagram of color difference signal interpolation processing.

FIG. 13 is a block diagram of the second embodiment.

FIG. 14 is an operation explanatory diagram of the second embodiment.

FIG. 15 is a configuration diagram of a phase shifter used in the second embodiment.

FIG. 16 is a block diagram of a modification of the second embodiment.

FIG. 17 is an explanatory diagram of sampling in Conventional Example 2.

FIG. 18 is a diagram showing a recording pattern on a floppy disk in Conventional Example 2.

FIG. 19 is a block diagram of a camera according to Conventional Example 2.

FIG. 20 is a block diagram of a playback device in Conventional Example 2.

FIG. 21 is a block diagram of the third embodiment.

FIG. 22 is an operation explanatory diagram of the third embodiment.

FIG. 23 is a diagram showing pixels to be transmitted in Conventional Example 3.

FIG. 24 is a diagram showing a recording pattern on a floppy disk in Conventional Example 3.

FIG. 25 is a diagram showing a HIT signal.

FIG. 26 is a diagram showing correct sampling points.

FIG. 27 is a block diagram of an automatic phase adjustment circuit in Conventional Example 3.

FIG. 28 is a diagram showing points of sampled HIT data.

FIG. 29 is an explanatory diagram when a dropout occurs in HIT in Conventional Example 3.

FIG. 30 is a block diagram of the fourth embodiment.

FIG. 31 is a diagram showing a configuration in a case where CHSV dubbing recording is shown by the output of the fourth embodiment.

32 is a detailed block diagram of the pilot signal control circuit in FIG.

FIG. 33 is a diagram showing a recording pattern of CHSV.

FIG. 34 is a block diagram of a main part of the fifth embodiment.

FIG. 35 is a diagram showing a dubbing mode according to the fifth embodiment.

FIG. 36 is an explanatory diagram of a modification of the fifth embodiment.

FIG. 37 is a signal waveform diagram of each part of FIG. 36.

38 is a diagram showing pixels to be transmitted in Conventional Example 5. FIG.

FIG. 39 is a diagram showing a recording pattern on a floppy disk in Conventional Example 5.

FIG. 40 is a diagram showing Nyquist characteristics.

FIG. 41 is a block diagram of a recording / reproducing apparatus in Conventional Example 5.

42 is a diagram showing pixels of a color signal transmitted in Conventional Example 5. FIG.

FIG. 43 is a diagram showing a HIT signal.

[Explanation of symbols]

 22, 23 memory 101 HD phase shifter 104 memory controller 105 CPU

Claims (8)

[Claims] 1. A video signal reproducing apparatus for reproducing a video signal from a recording medium, writing the video signal in an image memory, and performing an interpolation process on the image memory, wherein the VIT signal is added to each color difference signal in field units. Alternatively, among the HIT signals, the peak points of the signals added to the same color difference signal in different fields are compared, and the time difference detection means for detecting the time difference and the output of the time difference detection means are used to detect the time difference in the image memory. A video signal reproducing device, comprising: a control means for controlling the phase of a horizontal address reset signal for writing. 2. The video signal reproducing apparatus according to claim 1, wherein the recording medium is a disc-shaped recording medium in which each color difference signal is recorded via two systems of signal processing circuits. 3. A video signal reproducing apparatus for reproducing a video signal from a recording medium, converting the analog signal into a digital signal and writing the converted image signal into an image memory, wherein a control signal based on a VIT signal or a HIT signal added to the video signal, Sampling phase control means for controlling the sampling phase of the analog-digital conversion, and holding means for holding the control signal, the sampling phase control means,
A video signal reproducing apparatus characterized in that, when analog-digital conversion of a field via the same recording system, control is performed by using the output of the holding means as a control signal. 4. A video signal reproducing apparatus for reproducing a video signal from a recording medium, performing analog-digital conversion at a predetermined sampling phase based on a HIT signal added to the video signal, and writing the analog video signal in an image memory, wherein the preset setting is made. Dropout occurs in a part of the HIT signal of a few lines, and first control means for taking in the HIT signal of the aforesaid several lines to control so that the sampling phase of the analog-digital conversion becomes the predetermined sampling phase. According to the detection means for detecting the fact and the output of this detection means,
Before this output, the data of the HIT signal taken in by the first control means is invalidated, and the HIT of several lines after this output is
A video signal reproducing apparatus comprising: a second control means for causing a signal to be taken into the first control means. 5. A signal adding means for adding a field identification signal to a predetermined one field video signal among a plurality of field video signals reproduced from a recording medium, and a field added with the field identification signal by this signal adding means. A video signal reproducing apparatus comprising: a control unit that outputs video signals of a plurality of fields including the video signals in a predetermined order. 6. The video signal reproducing apparatus according to claim 5, wherein the plurality of fields are four fields forming a CHSV signal. 7. A frame is formed by 4 fields,
A first image memory for storing a video signal to which a HIT signal is added, a second image memory for storing a video signal forming one frame in two fields, and an image for each four fields from the first image memory A first recording system for reading and recording a signal or a video signal for each partial field of four fields; and a second recording system for reading out and recording a video signal for every two fields or a video signal for every one field from the second image memory. A video signal recording device comprising a recording system. 8. The first recording system comprises HIT signal removing means for removing a HIT signal added to a video signal when recording a video signal for each partial field of four fields. The video signal recording device according to claim 7, which is characterized in that.