JPH06188361A - Multichip module substrate - Google Patents

Multichip module substrate

Info

Publication number
JPH06188361A
JPH06188361A JP11660692A JP11660692A JPH06188361A JP H06188361 A JPH06188361 A JP H06188361A JP 11660692 A JP11660692 A JP 11660692A JP 11660692 A JP11660692 A JP 11660692A JP H06188361 A JPH06188361 A JP H06188361A
Authority
JP
Japan
Prior art keywords
chip
tab
heat sink
substrate
hollowed out
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP11660692A
Other languages
Japanese (ja)
Inventor
Yoshikazu Ichiba
義和 市場
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP11660692A priority Critical patent/JPH06188361A/en
Publication of JPH06188361A publication Critical patent/JPH06188361A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)

Abstract

PURPOSE:To obtain a device capable of high density mounting and application to a high speed device wherein a bare chip can be effectively cooled, by a method wherein mounting pads are arranged in a step type, two TAB chips are stacked and mounted, and heat sinks are independently formed on the surface and the rear. CONSTITUTION:Lamination boards are stacked in a state that a part of the board is hollowed out, mounting pads 5, 7 are arranged in a step type, and two TAB chips 4, 6 are stacked and mounted. A heat sink 1 is directly brought into contact with the upper TAB chip 4 and fixed. Copper pads 8, 9 are arranged just under the lower TAB chip 6 and on the surface of a substrate 13 wherein the rear side is hollowed out, and connected via a through hole. A metal slab 11 is buried in the part where the rear of the substrate 13 is hallowed out, and is connected with the copper foil pad 9 on the surface wherein the rear of the substrate 13 is hollowed out. A heat sink 12 is connected with the buried metal slab 11. For example, the upper TAB chip 4 wherein an adhesive agent 3 is spread on the rear is mounted with its face down, and the heat sink 1 is bonded to the chip 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はマルチチップモジュール
(以下MCMと略す)基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module (hereinafter abbreviated as MCM) substrate.

【0002】[0002]

【従来の技術】図2は従来の一例を示す断面図である。
基板1にTAB2をボンディングワイヤー5で接続し、
基板1中にメタルスラグ3を埋込み、これを裏面に露出
させてヒートシンク4に接続する。TAB2は封止樹脂
7で封止する。
2. Description of the Related Art FIG. 2 is a sectional view showing a conventional example.
Connect the TAB 2 to the substrate 1 with the bonding wire 5,
The metal slug 3 is embedded in the substrate 1, exposed on the back surface, and connected to the heat sink 4. The TAB 2 is sealed with the sealing resin 7.

【0003】[0003]

【発明が解決しようとする課題】従来の技術は、ワイヤ
ーボンディング接続したベアチップを樹脂で封止する必
要があり、リペア処理できないのと両面実装のようにベ
アチップを重ねて配置できないという欠点がある。
The conventional technique has a drawback in that the bare chip connected by wire bonding needs to be sealed with a resin, so that the repair process cannot be performed and the bare chips cannot be arranged in an overlapped manner like double-sided mounting.

【0004】[0004]

【課題を解決するための手段】本発明のMCM基板は2
つのTABチップLSIを重ねて搭載するため、搭載パ
ッドを階段上に2つ持つことと、下部のヒートシンクを
接続するメタルスラグと、下部のTABチップ下の金属
パッドと下部に埋込まれたメタルスラグを接続するスル
ーホールを持つことと、上部のTABチップを冷却する
ヒートシンクと、下部のメタルスラグを介して下部のT
ABチップを冷却するヒートシンクにより構成される。
The MCM substrate of the present invention has two
Since two TAB chip LSIs are mounted on top of each other, two mounting pads are provided on the stairs, a metal slug for connecting a heat sink in the lower part, a metal pad under the TAB chip in the lower part and a metal slug embedded in the lower part. Has a through hole for connecting the TAB chip, a heat sink for cooling the TAB chip on the upper side, and a lower T via the metal slug on the lower side.
It is composed of a heat sink that cools the AB chip.

【0005】[0005]

【実施例】本発明について図面を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.

【0006】図1は本発明の一実施例の断面図である。
基板13はエッチング処理された配線パターンを持つセ
ラミック基板、もしくはPWBである。あらかじめ第1
層に上部のTABチップ4の冷却用のヒートシートシン
ク1を固定するためのパッド2を設けておく、第2層に
は上部TABチップ4をはんだ接続するパッド5を設け
ておく。第3層には下部TABチップ6をはんだ接続す
るパッド7を設けておく。また第3層下部TABチップ
の下に銅箔パッド8を設けておく。第4層にもメタルス
ラグ11と接触させるための銅箔パッドを設けておく。
FIG. 1 is a sectional view of an embodiment of the present invention.
The substrate 13 is a ceramic substrate having an etched wiring pattern or PWB. First in advance
A pad 2 for fixing the heat sheet sink 1 for cooling the upper TAB chip 4 is provided in the layer, and a pad 5 for solder-connecting the upper TAB chip 4 is provided in the second layer. A pad 7 for soldering the lower TAB chip 6 is provided on the third layer. Further, a copper foil pad 8 is provided below the third layer lower TAB chip. A copper foil pad for contacting the metal slug 11 is also provided in the fourth layer.

【0007】次に第1層と第2層に狭まれた銅張積層板
について上部TABチップ搭載パッド5を積層後に上部
に露出させておくためにフライス盤で上部TABチップ
搭載パッド5の上部の部分を削っておく。同様に第2層
と第3層に狭まれた銅張積層板についても下部TABチ
ップ搭載パッド7を積層後に上部に露出させておくため
にフライス盤で下部TABチップ搭載パッド7を上部の
部分を削っておく。第4層と第5層に狭まれた銅張積層
板についてはメタルスラグ11をはめ込む部分について
フライス盤で削っておく。
Next, regarding the copper-clad laminate sandwiched between the first layer and the second layer, a part of the upper portion of the upper TAB chip mounting pad 5 is milled with a milling machine to expose the upper TAB chip mounting pad 5 to the upper side after the lamination. Cut off. Similarly, for the copper clad laminate sandwiched between the second layer and the third layer, the upper portion of the lower TAB chip mounting pad 7 is ground with a milling machine to expose the lower TAB chip mounting pad 7 to the upper side after lamination. Keep it. With respect to the copper clad laminate narrowed between the fourth layer and the fifth layer, the portion where the metal slug 11 is fitted is ground with a milling machine.

【0008】次に、第3層と第4層で狭まれた銅張積層
板について、第3層の下部TABチップ6を接触させる
ための銅箔パッド8と第4層のメタルスラグ11を接触
させる銅箔パッド9を接続させるためにドリルで複数個
のスルーホールを設けた後、スルーホール内をめっきす
る。これは下部TABチップ6の熱をメタルスラグ11
を介してヒートシンク12へ逃がすためである。
Next, regarding the copper clad laminate sandwiched between the third layer and the fourth layer, the copper foil pad 8 for contacting the lower TAB chip 6 of the third layer and the metal slug 11 of the fourth layer are contacted. After providing a plurality of through holes with a drill for connecting the copper foil pads 9 to be formed, the inside of the through holes is plated. This heats the lower TAB chip 6 with metal slag 11
This is because it escapes to the heat sink 12 via the.

【0009】こうしてできた各銅張積層板を積層プレス
機で加圧加熱処理して1枚の基板にした後、メタルスラ
グ11を第4層のメタルスラグ接続パッド9に接着剤1
4を付着させてからはめ込む。次にTABチップを基板
に実装する。まず下部TABチップ6の下に接着剤15
を付着してから第3層の銅箔パッド8に固定する。次に
下部TABチップ6のリードを第3層の下部TABチッ
プ搭載パッド7にはんだ接続する。次に上部TABチッ
プ4のリードを第2層の上部TABチップ搭載パッド5
にダウンフェースにしてはんだ接続する。上部TABチ
ップの裏側には接着剤3を付けておき、ヒートシンク1
を接着させる。ヒートシンク1は第1層のヒートシンク
固定用パッド上ではんだ止めして固定する。基板の裏側
にはめ込んだメタルスラグに接着剤14を付けてからヒ
ートシンク12を接着し固定する。TABチップの発す
る熱は、上部TABチップ4については直接ヒートシン
ク1を通じて空気中へ放散させ、下部TABチップ6に
ついてはスルーホール10とメタルスラグ11を通じて
裏側のヒートシンク12へ伝導させてから空気中に放散
させる。
Each of the copper clad laminates thus produced is pressure-heated by a laminating press to form one substrate, and then the metal slug 11 is attached to the metal slug connection pad 9 of the fourth layer by the adhesive 1
Attach 4 and then fit. Next, the TAB chip is mounted on the substrate. First, glue 15 under the lower TAB chip 6.
And then fixed to the third layer copper foil pad 8. Next, the lead of the lower TAB chip 6 is soldered to the lower TAB chip mounting pad 7 of the third layer. Next, the leads of the upper TAB chip 4 are connected to the upper TAB chip mounting pads 5 of the second layer.
Make a down face and solder connect. Adhesive 3 is attached to the back side of the upper TAB chip, and the heat sink 1
To adhere. The heat sink 1 is fixed by soldering on the heat sink fixing pad of the first layer. An adhesive 14 is attached to the metal slug fitted on the back side of the substrate, and then the heat sink 12 is adhered and fixed. The heat generated by the TAB chip is dissipated into the air through the heat sink 1 for the upper TAB chip 4, and is conducted to the heat sink 12 on the back side through the through hole 10 and the metal slug 11 for the lower TAB chip 6 before being dissipated in the air. Let

【0010】[0010]

【発明の効果】以上説明したように本発明は2つのベア
チップを重ねて実装できるので狭い面積に多くのベアチ
ップを実装できる。そのため、ベアチップ間の実装密度
が高められ、配線長も短くできるのでより高速の装置に
適用できる。また、表裏にヒートシンクを独立してもつ
ことができるので高熱を発するベアチップを効率よく冷
却することが可能である。更にベアチップをTABチッ
プで一括はんだ接続するのでワイヤーボンディング接続
するより効率がよい。また下部のTABチップとメタル
スラグ間をスルーホールを介して熱伝導させるので直接
TABチップとメタルスラグを接触させた場合より失わ
れるチップ間の配線領域を最小限にすることができると
いう効果がある。
As described above, according to the present invention, since two bare chips can be mounted in an overlapping manner, many bare chips can be mounted in a small area. Therefore, the packaging density between bare chips can be increased and the wiring length can be shortened, so that it can be applied to a higher speed device. In addition, since heat sinks can be independently provided on the front and back sides, it is possible to efficiently cool bare chips that generate high heat. Further, since the bare chips are collectively solder-connected with the TAB chips, it is more efficient than the wire bonding connection. Further, since heat is conducted between the lower TAB chip and the metal slug through the through hole, there is an effect that the wiring area between the chips which is lost can be minimized as compared with the case where the TAB chip and the metal slug are directly contacted with each other. .

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.

【図2】従来の一例を示す断面図である。FIG. 2 is a cross-sectional view showing a conventional example.

【符号の説明】[Explanation of symbols]

1 ヒートシンク 2 ヒートシンク固定用パッド 3 接着剤 4 TABチップ 5 上部TABチップ搭載パッド 6 TABチップ 7 下部TABチップ搭載パッド 8 TABチップ接続用銅箔パッド 9 メタルスラグ接続用銅箔パッド 10 スルーホール 11 メタルスラグ 12 ヒートシンク 13 基板 14 接着剤 1 Heat Sink 2 Pad for Fixing Heat Sink 3 Adhesive 4 TAB Chip 5 Upper TAB Chip Mounting Pad 6 TAB Chip 7 Lower TAB Chip Mounting Pad 8 TAB Chip Connecting Copper Foil Pad 9 Metal Slug Connecting Copper Foil Pad 10 Through Hole 11 Metal Slug 12 heat sink 13 substrate 14 adhesive

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 23/36 H05K 7/20 D 8727−4E ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI Technical display location H01L 23/36 H05K 7/20 D 8727-4E

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 積層板の一部をくり抜いた状態で積層
し、搭載パッドを階段状に設けて2つのTABチップを
重ねて実装する手段と、上部のTABチップに直接ヒー
トシンクを接続して固定する手段と、下部のTABチッ
プの直下と基板の裏側をくり抜いた面に銅箔パッドを設
けてスルーホールで接続する手段と、基板の裏側のくり
抜いた部分に金属片を埋め込み基板の裏側のくり抜いた
面の銅箔パッドに接続させる手段と、埋込んだ金属片に
ヒートシンクを接続する手段とを含むことを特徴とする
マルチチップモジュール基板。
1. A means for stacking a plurality of laminated plates in a hollowed-out state, providing mounting pads in a staircase shape and mounting two TAB chips in an overlapping manner, and directly fixing a heat sink to the upper TAB chip to fix it. Means, a means to connect a through hole by providing a copper foil pad on the surface of the lower side of the TAB chip and the back side of the board which are hollowed out, and a metal piece is embedded in the hollowed out part of the back side of the board, and the back side of the board is hollowed out. A multi-chip module substrate comprising means for connecting to a copper foil pad on the exposed surface and means for connecting a heat sink to the embedded metal piece.
JP11660692A 1992-05-11 1992-05-11 Multichip module substrate Withdrawn JPH06188361A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11660692A JPH06188361A (en) 1992-05-11 1992-05-11 Multichip module substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11660692A JPH06188361A (en) 1992-05-11 1992-05-11 Multichip module substrate

Publications (1)

Publication Number Publication Date
JPH06188361A true JPH06188361A (en) 1994-07-08

Family

ID=14691332

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11660692A Withdrawn JPH06188361A (en) 1992-05-11 1992-05-11 Multichip module substrate

Country Status (1)

Country Link
JP (1) JPH06188361A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0694968A3 (en) * 1994-07-26 1996-09-11 Nec Corp Multi-chip module semiconductor device
KR100521330B1 (en) * 1998-07-11 2006-01-12 삼성전자주식회사 a radiator structure for Computer System

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0694968A3 (en) * 1994-07-26 1996-09-11 Nec Corp Multi-chip module semiconductor device
KR100521330B1 (en) * 1998-07-11 2006-01-12 삼성전자주식회사 a radiator structure for Computer System

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990803