JPH06187269A - Data processor - Google Patents

Abstract

PURPOSE:To make it possible to make the device of a reception side recognize the termination of a transfer request rightly even when the transfer of packets on the way is suppressed when plural packets are transferred by a signal transfer request. CONSTITUTION:A fault display means (30) is made to display a fault by a transfer processing part when a fault due to a program exception or hardware damage occurs while the transfer processing based on a transfer request which is possible to be referred and deleted by an instruction processing part is performed. For the fault display period of the fault display means (30), the transfer processing to be performed by taking out the transfer request enqueued by a transfer request queue is inhibited. After a fault recovery processing is performed in an instruction processing part, the display of the fault of the fault display means (30) is deleted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to a data processing device for mutually transferring data via a network.

[0002]

2. Description of the Related Art In a data processing system such as a parallel computer system in which a plurality of data processing devices are connected via a network or the like, data is transferred between the plurality of data processing devices to execute parallel data processing.

In the conventional system, when transferring the contents of the storage area of an arbitrary data processing device to another data processing device, a transfer request queue for queuing a data transfer request to another data processing device is provided, and an instruction is provided. The user program executed in the processing unit sequentially enqueues the transfer requests in the transfer request queue, and as long as the transfer processing unit operating independently of the instruction processing unit enqueues the transfer requests in the transfer request queue, the transfer requests are transferred from the queue. Has been proposed to perform the transfer process by reading the. In this method, the instruction processing unit and the transfer processing unit operate independently, so that the load and overhead of the instruction processing unit are reduced, and a great improvement in performance is obtained.

[0004]

In the above conventional method, a series of data is divided into a plurality of packets and transferred, and the receiving side polls the arrival of the final data packet to monitor the end of the transfer. , If the transmission side suppresses the transmission of this packet due to a program exception or a machine check during the transfer processing of a packet in the middle of a series of data, the process proceeds to the next packet transfer processing. Therefore, there is a problem in that the receiving side does not know that the transfer of the packet in the middle of the above was not performed, and when the packet of the final data arrives, it is erroneously recognized that the transfer of all the data has ended normally. .

The present invention has been made in view of the above points,
Provided is a data processing device capable of correctly recognizing the end of a transfer request to a device on the receiving side even when transfer of a plurality of packets is suppressed on the way when a plurality of packets are transferred by a single transfer request. The purpose is to

[0006]

A data processing apparatus according to the present invention is mutually connected via a network, enqueues a transfer request of an instruction processing unit for performing data processing into a transfer request queue, and takes out from the transfer request queue. In a data processing device that transfers data between a storage device and the network in a transfer processing unit in accordance with a transfer request that can be referred to and erased by the instruction processing unit, and a failure occurs during the transfer processing based on the transfer request. The transfer processing unit has a failure display means for displaying a failure, and prohibits the transfer processing performed by extracting the transfer request enqueued in the transfer request queue during the failure display period of the failure display means,
After performing the failure recovery processing in the command processing section, the display of the failure on the failure display means is erased.

Further, a plurality of transfer request queues are provided, and a plurality of failure display means are provided corresponding to each of the plurality of transfer request queues, and a transfer request corresponding to the failure display means during a failure display period of an arbitrary failure display means. Prohibits transfer processing by transfer requests enqueued in the queue.

[0008]

According to the present invention, when a program exception or a hardware damage failure occurs during the transfer processing, the transfer processing performed by fetching the transfer request from the transfer request queue is prohibited by the failure display, and the failure is recovered after the failure recovery. Therefore, when multiple packets are transferred by a single transfer request, even if a program exception or a hardware damage failure occurs during the transfer of an intermediate packet and the transfer of this packet is suppressed, The transfer of the packet is prohibited, and the transfer of the above-mentioned packet and the remaining packet is restarted due to the failure recovery, or this transfer request is deleted, and the end of the transfer request is mistakenly recognized by the data processing device on the receiving side. Is prevented.

Further, by providing the failure display means corresponding to each of the plurality of transfer request queues, the transfer processing by the transfer request of the transfer request queue corresponding to the failure display means in which the failure is displayed is prohibited, and Transfer processing by the transfer request in the transfer request queue that has not occurred is continued, and even if a failure occurs when multiple packets are transferred by a single transfer request, the network of the receiving side can be used effectively while using the network effectively. It is possible to prevent the data processing device from erroneously recognizing the end of the transfer request.

[0010]

FIG. 2 is a block diagram of a parallel computer system to which the device of the present invention is applied. In the figure, the data processing apparatus 10 ₁ -
Each of the 10n is connected via the network 11. The data processing devices 10 _{1 to} 10 n mutually transfer data via the network 11 and individually perform data processing.

As shown in FIG. 3, each of the data processing units 10 _{1 to} 10 n comprises a transfer processing unit 15, an instruction processing unit 16, and a main memory 17. The transfer processing unit 15 performs a packet transfer process between the main memory 17 and the network 11 according to an instruction from the instruction processing unit 16. The transfer packet is composed of a memory access attribute in the data processing device on the transmission side and the reception side, a header which is information for designating the process in the data processing device on the reception side, and body data which is the transfer data body.

The instruction processing unit 16 reads out and executes the program stored in the main memory 17, and performs data processing of the data stored in the main memory 17.

FIG. 1 is a block diagram of a first embodiment of the transfer processing unit of the device of the present invention.

In the figure, the network transfer control unit 20 is
It is activated by a command supplied from the instruction processing unit 16 through the terminal 21, and starts the transfer process according to the values of the transfer queue read pointer 22 and the transfer queue write pointer 23, and the main memory for reading the header and body data of the transfer packet. A network 1 that issues a main memory access request to the access control unit 24 and is connected via a terminal 25
By controlling the interface with 1, the transfer packet is sent from the data buffer 26 to the network 11 via the terminal 27. When a packet exception or a machine check error occurs and packet transmission is suppressed, the interrupt display flag is set in the error display register and the error state is written. At the end of the transfer, the transfer queue read pointer 22 is incremented.

The main memory access control unit 24 accesses the main memory 17 via the terminal 28 according to a command from the network transfer control unit 20 and via the terminal 29 between the main memory 17 and the data buffer 26. Control data transfer. The data buffer 26 temporarily buffers data when data is transferred between the main memory 17 and the network 11, and the network transfer control unit 20 and the main memory access control unit 24 are required on the main memory 17. Buffer data temporarily when reading or writing the data.

The transfer queue base address register 31 can be referenced and updated by the instruction processing unit 16, and stores the start address of the transfer queue on the main memory 17. The transfer queue write pointer 23 manages to which position in the transfer queue the instruction processing unit 16 enqueues the transfer request,
The transfer queue read pointer manages to which position in the transfer queue the transfer process of the transfer request is completed.

When the transmission of a packet due to a fault is suppressed, the fault display register 30 requests an interrupt by the instruction processing unit 16 using the interrupt display flag, and also displays the state of the fault to manage the fault.

FIG. 4 is a block diagram of the network transfer control unit 20. In the figure, the instruction processing unit 1
The start / stop command coming from 6 is supplied to the reception state control unit 40 and the transmission state control unit 41.

The reception state control unit 40 is supplied with a reception start notification from the reception buffer control unit 42 and a reception access end via the terminal 43 from the main memory access control unit 24 in addition to the above-mentioned start / stop command, and the reception state is received. Is supplied to the bus adjustment processing unit 44, and the main memory access control unit 24 is supplied with a reception access control command.

In addition to the above-mentioned start / stop command, the transmission state control unit 41 receives from the main memory access control unit 24 the terminal 4
A register which is supplied with the end of the transmission access via 3 and manages the transmission state, and which is connected through the terminal 47,
The pointer read / write command is supplied to the bus adjustment processing unit 44, the reception access control command is supplied to the main memory access control unit 24, and the transmission end notification is supplied to the transmission buffer control unit 46.

The bus arbitration processing unit 44 arbitrates the commands from the reception state control unit 40 and the transmission state control unit 41, and transmits the fault register 30, the transfer queue base address register 31, the transfer queue read pointer 22, through the terminal 47. A bus control command is sent to a bus connected to the transfer queue write pointer 23 and the main memory access control unit 24.
Supply bus address and data.

The reception buffer control unit 42 is supplied with a reception valid signal and a reception end signal from the network 11 via the terminal 48, and receives the data reception buffer writing valid signal from the network 11 to the data buffer 26 via the terminal 49. The address is supplied, the transmission response signal is supplied to the network 11, the reception buffer read address is supplied to the data buffer 26, and the reception buffer read valid signal is supplied from the main memory access control unit 24 via the terminal 43.

The transmission buffer control unit 46 is supplied with a transmission buffer write enable signal from the main memory access control unit 24 via the terminal 43, supplies the transmission buffer write address to the data buffer 26 from the terminal 49, and also receives the data buffer. A transmission buffer read valid signal and an address are supplied to 26, a transmission valid signal is supplied to the network 11 via a terminal 48, and a response signal is supplied from the network 11. Further, upon receiving the transfer end notification, the transmission end signal is supplied to the network 11. Further, it is connected to a data buffer via a terminal 49 by a data bus, and performs predetermined inspection and modification of transfer request control information.

FIG. 5 is a block diagram of the main memory access controller 24. In the figure, the transmission request / address generation unit 51 is supplied with a bus control command and a bus address from the network transfer control unit 20 via a terminal 52, is connected to a data bus, and is connected via a terminal 53 to the network transfer control unit. 20 is supplied with a transmission access control command and a transmission buffer full signal, and is also supplied with a main memory read timing validator 54 with a main memory read data valid signal, and a transfer queue of the main memory 17 via a data buffer 26 via a terminal 55. Is supplied, the transmission request, the operation code, and the address are generated and supplied to the main memory access priority control unit 56,
The transmission transfer end is notified to the network transfer control unit 20 via the terminal 53.

The reception request / address generating unit 57 is supplied with the bus control command and the bus address from the network transfer control unit 20 via the terminal 52 and is connected by the data bus, and is also connected via the terminal 53 to the network transfer control unit 20. A reception access control command and a reception buffer full / empty signal are supplied from the main memory 17, and a reception buffer read valid signal is supplied from the main memory access priority control unit 56, and a transfer queue of the main memory 17 via the data buffer 26 via the terminal 55. Of the main memory access priority control unit 5 by generating a reception request, an operation code and an address.
6 to notify the network transfer control unit 20 of the reception access end via the terminal 53.

Main memory access priority control unit 56
Is supplied with a transmission request, a reception request and an operation code, selects one of them according to its priority (usually reception priority) and supplies the request, operation code and address to the main memory 17 through the terminal 58, Main memory read timing adjustment unit 54
, And supplies a reception buffer read valid signal to the data buffer 26 and the network transfer control unit 20.

The main memory read timing adjusting unit 54 generates a main memory read data valid signal and a transmission buffer write valid signal based on the above activation and supplies them to the data buffer 26 and the network transfer control unit 20.

Next, the operation of the transfer processing section 15 will be described.

The user program uses transfer request control information such as transfer request reception processing device designation, body data length, transmission address, and reception address as the transfer packet header format + transfer queue base address register 31 value +
The transfer queue write pointer 23 is written to the address on the main memory 17 which is indicated by the value of the header x length. After that, the transfer queue write pointer 23 is incremented. After that, the user program repeats writing control information of the transfer request to the transfer queue and incrementing the transfer queue write pointer 23 to end the enqueue process.

As a result, the transfer request control information is stored in the transfer queue of the main memory 17, as shown in FIG.

The network transfer control unit 20 is activated by a command from the instruction processing unit 16 and is in a waiting state for a transfer request enqueue. The value of the transfer queue read pointer 22 and the value of the transfer queue write pointer 23 are equal to each other. If not done, the transfer process is started assuming that there is an unprocessed transfer request, and the main memory access request is issued to the main memory access control unit 24 for reading the header of the transfer packet.

As a result, the main memory access control unit 24 calculates the value of the transfer queue base address register 31 + the value of the transfer queue read pointer 22 × the header length to obtain the main memory of the packet header of the oldest unprocessed transfer request. The address on 17 is obtained, and a read access is issued to the main memory 17. As a result, when the packet header is read from the main memory 17, the main memory access control unit 24 stores it in the data buffer 26 and notifies the network transfer control unit 20 of the completion of reading the packet header.

Subsequently, the main memory access control unit 24 extracts the control information of the transfer request from the main memory 17 via the data buffer 26, calculates the address of the body of the transfer packet, and reads the packet body from the main memory 17. Issue access. When the packet bodies are sequentially read from the main memory 17, the main memory access control unit 24 sequentially stores them in the data buffer 26, and at the same time, notifies the network transfer control unit 20 of the read amount of the packet bodies.

When the network transfer control unit 20 is notified by the main memory access control unit 24 that the reading of the packet header has been completed, the transfer request control information is fetched from the data buffer 26 and subjected to predetermined inspection and modification. The control information is written back to the data buffer 26.

Subsequently, the network transfer control unit 20 sends the packet header from the data buffer 26 to the network 11. Further, when the network transfer control unit 20 is sequentially notified of the read amount of the packet body from the main memory access control unit 24, the packet body stored in the data buffer 26 is sequentially transmitted to the network 11. When the transmission of the transfer packet to the network 11 is completed in this way, the network transfer control unit 20 increments the transfer queue read pointer 22.

Further, the network transfer control unit 20 checks the values of the transfer queue read pointer 22 and the transfer queue write pointer, and if there is an unprocessed transfer request, the next transfer process is started.

When a program exception or hardware damage related to the transfer process is detected during the transfer process, the network transfer control unit 20 sets the interrupt display flag of the failure display register 30, and Write the status of the detected fault. After that, even if there is a transfer request enqueued in the transfer request queue while the interrupt display flag is set, it is prohibited to take out the transfer request and perform the transfer processing.

When the user program executed by the instruction processing section 16 detects that the interrupt display flag is set in the failure display register 30 of the transfer processing section 15, the failure state written in the failure display register 30 is detected. Analyze the cause of the transfer failure from, etc., if possible recover the part that causes it and enqueue the transfer control information,
If recovery is not possible, the remaining transfer requests are erased, and the values of the transfer queue read pointer 22 and the transfer queue write pointer 23 are changed accordingly. After this, the user program erases the contents of the failure display register 30 and performs failure recovery processing.

When the failure can be recovered, the transfer processing unit 15 has the failure display register 3 because there are unprocessed transfer requests.
After detecting the erasure of 0, the remaining transfer processing is executed.

As described above, when a program exception or a hardware damage failure occurs during the transfer processing, the transfer processing performed by fetching the transfer request from the transfer request queue is prohibited by the failure display, and the prohibition is set after the failure recovery. Therefore, when multiple packets are transferred by a single transfer request, even if a program exception or a hardware damage failure occurs during the transfer of an intermediate packet and this packet transfer is suppressed, The transfer of packets is prohibited, the transfer of the above-mentioned packets and the rest of the packets is restarted due to failure recovery, or this transfer request is deleted, and the end of the transfer request may be mistakenly recognized by the data processing device on the receiving side. To be prevented.

FIG. 7 shows a block diagram of another embodiment of the transfer processing unit of the device of the present invention. In the figure, those parts which are the same as those corresponding parts in FIG. 1 are designated by the same reference numerals, and a description thereof will be omitted. In FIG. 7,
In addition to the fault display register 30, the transfer queue base address register 31, the transfer queue read pointer 22, and the transfer queue write pointer 23, a fault display register 60,
A transfer queue base address register 61, a transfer queue read pointer 62, and a transfer queue write pointer 63 are provided, and these are connected to the instruction processing unit 16, the network transfer control unit 20, and the main memory access control unit 24 by a bus for access. It is possible.

In this case, two transfer request queues are provided on the main memory 17, and the transfer processing is performed independently using each transfer request queue. For example, when a program exception or hardware damage related to the transfer processing by one of the transfer request queues corresponding to the failure display register 60 is detected, the interrupt display flag of the failure display register 60 is set and the failure status is written. While the interrupt display flag is set, the transfer note using the one transfer request queue is prohibited. However, if the transfer request is enqueued in the other transfer request queue corresponding to the failure display register 30, the transfer request is fetched from the other transfer request queue unless the interrupt display flag of the failure display register 30 is set. Execute the transfer process. For the transfer request in one of the transfer request queues in which a failure has occurred, the instruction processing unit 16 modifies the transfer control information and enqueues it, or performs the failure recovery process of deleting the remaining transfer requests. Same as the example.

As described above, by providing the failure display means corresponding to each of the plurality of transfer request queues, the transfer processing by the transfer request of the transfer request queue corresponding to the failure display means in which the failure is displayed is prohibited, Transfer processing by the transfer requests in the transfer request queue where no failure has occurred is continued, and even if a failure occurs when multiple packets are transferred by a single transfer request while using the network effectively, it is received. It is possible to prevent the data processing device on the side from erroneously recognizing the end of the transfer request.

[0044]

As described above, according to the data processing apparatus of the present invention, when a plurality of packets are transferred by a single transfer request, even if the transfer of the packet is suppressed midway, the transfer request is transmitted. The termination can be correctly recognized by the receiving device, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a block diagram of a transfer processing unit of an apparatus of the present invention.

FIG. 2 is a configuration diagram of a parallel computer system.

FIG. 3 is a block diagram of a data processing device of the present invention.

FIG. 4 is a block diagram of a network transfer control unit.

FIG. 5 is a block diagram of a main memory access control unit.

FIG. 6 is a configuration diagram of a transfer queue.

FIG. 7 is a block diagram of a transfer processing unit of the device of the present invention.

[Explanation of symbols]

10 _{1 to} 10 n Data processing device 11 Network 15 Transfer processing unit 16 Command processing unit 17 Main memory 20 Network transfer control unit 22, 62 Transfer queue read pointer 23, 63 Transfer queue write pointer 24 Main memory access control unit 26 Data buffer 30, 60 Fault display register 31, 61 Transfer queue base address register

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Haruhiko Kamino, Inventor Haruhiko Ueno, 1015 Kamiodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited (72) Teruo Utsumi, 1015, Kamiodanaka, Nakahara-ku, Kawasaki, Kanagawa, Fujitsu Limited ( 72) Inventor Kazushige Kobayakawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Masami Dewa 1015, Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor, Kenichi Ishizaka Kanagawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki Prefecture, Japan Within Fujitsu Limited

Claims (3)

[Claims] 1. A transfer request is enqueued in a transfer request queue of a command processing unit (16) which is connected to each other via a network (11) and performs data processing, and transfer processing is performed in accordance with the transfer request fetched from the transfer request queue. Division (15)
In the data processing device for transferring data between the storage device (17) and the network, the instruction processing unit (16) can be referred to and erased, and when a failure occurs during the transfer process based on the transfer request, Failure display means (3) for displaying a failure by the transfer processing unit
0), the transfer processing performed by fetching the transfer request enqueued in the transfer request queue during the failure display period of the failure display means is prohibited, and the failure processing is performed by the instruction processing unit, and then the failure is performed. A data processing device, characterized in that a display of a failure on a display means is erased. 2. The data processing device according to claim 1, wherein a plurality of transfer request queues are provided, and a plurality of failure display means (30, 6) are provided corresponding to each of the plurality of transfer request queues.
0) is provided, and the transfer processing by the transfer request enqueued in the transfer request queue corresponding to the failure display means is prohibited during the failure display period of the arbitrary failure display means. 3. A transfer request is enqueued in a transfer request queue of a command processing unit (16) connected to each other via a network (11) and performing data processing, and transfer processing is performed in accordance with the transfer request fetched from the transfer request queue. Division (15)
In the data processing device for transferring data between the main memory (17) and the network, the instruction processing unit (16) can refer to and erase the program exception or hardware damage during the transfer processing based on the transfer request. Has a failure display means (30) for displaying the failure by the transfer processing unit when the failure occurs, and the transfer request enqueued in the transfer request queue is taken out during the failure display period of the failure display means. A data processing device, wherein transfer processing is prohibited, and after the failure recovery processing is performed by the instruction processing section, the failure display of the failure display means is erased.